1.1 --- a/src/cpu/x86/vm/vm_version_x86.cpp Wed Aug 13 10:44:50 2014 +0200
1.2 +++ b/src/cpu/x86/vm/vm_version_x86.cpp Fri Mar 17 03:39:23 2017 -0700
1.3 @@ -406,6 +406,8 @@
1.4 _stepping = 0;
1.5 _cpuFeatures = 0;
1.6 _logical_processors_per_package = 1;
1.7 + // i486 internal cache is both I&D and has a 16-byte line size
1.8 + _L1_data_cache_line_size = 16;
1.9
1.10 if (!Use486InstrsOnly) {
1.11 // Get raw processor info
1.12 @@ -424,6 +426,7 @@
1.13 // Logical processors are only available on P4s and above,
1.14 // and only if hyperthreading is available.
1.15 _logical_processors_per_package = logical_processor_count();
1.16 + _L1_data_cache_line_size = L1_line_size();
1.17 }
1.18 }
1.19
1.20 @@ -1034,6 +1037,7 @@
1.21 if (PrintMiscellaneous && Verbose) {
1.22 tty->print_cr("Logical CPUs per core: %u",
1.23 logical_processors_per_package());
1.24 + tty->print_cr("L1 data cache line size: %u", L1_data_cache_line_size());
1.25 tty->print("UseSSE=%d", (int) UseSSE);
1.26 if (UseAVX > 0) {
1.27 tty->print(" UseAVX=%d", (int) UseAVX);
