1.1 --- a/src/cpu/x86/vm/assembler_x86_32.hpp Wed Jun 04 13:51:09 2008 -0700
1.2 +++ b/src/cpu/x86/vm/assembler_x86_32.hpp Thu Jun 05 15:57:56 2008 -0700
1.3 @@ -216,9 +216,11 @@
1.4 #endif // ASSERT
1.5
1.6 // accessors
1.7 - bool uses(Register reg) const {
1.8 - return _base == reg || _index == reg;
1.9 - }
1.10 + bool uses(Register reg) const { return _base == reg || _index == reg; }
1.11 + Register base() const { return _base; }
1.12 + Register index() const { return _index; }
1.13 + ScaleFactor scale() const { return _scale; }
1.14 + int disp() const { return _disp; }
1.15
1.16 // Convert the raw encoding form into the form expected by the constructor for
1.17 // Address. An index of 4 (rsp) corresponds to having no index, so convert
1.18 @@ -990,7 +992,8 @@
1.19 // on arguments should also go in here.
1.20
1.21 class MacroAssembler: public Assembler {
1.22 - friend class LIR_Assembler;
1.23 + friend class LIR_Assembler;
1.24 + friend class Runtime1; // as_Address()
1.25 protected:
1.26
1.27 Address as_Address(AddressLiteral adr);
1.28 @@ -1151,6 +1154,10 @@
1.29 void store_check(Register obj); // store check for obj - register is destroyed afterwards
1.30 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
1.31
1.32 + void g1_write_barrier_pre(Register obj, Register thread, Register tmp, Register tmp2, bool tosca_live );
1.33 + void g1_write_barrier_post(Register store_addr, Register new_val, Register thread, Register tmp, Register tmp2);
1.34 +
1.35 +
1.36 // split store_check(Register obj) to enhance instruction interleaving
1.37 void store_check_part_1(Register obj);
1.38 void store_check_part_2(Register obj);
