1.1 --- a/src/cpu/mips/vm/mips_64.ad Wed Mar 22 07:13:07 2017 -0400
1.2 +++ b/src/cpu/mips/vm/mips_64.ad Wed Mar 22 09:33:20 2017 -0400
1.3 @@ -1734,14 +1734,7 @@
1.4 // tertiary opcode. Only the opcode sections which a particular instruction
1.5 // needs for encoding need to be specified.
1.6 encode %{
1.7 -/*
1.8 -Alias:
1.9 -1044 b java.io.ObjectInputStream::readHandle (130 bytes)
1.10 - 118 B14: # B19 B15 <- B13 Freq: 0.899955
1.11 - 118 add S1, S2, V0 #@addP_reg_reg
1.12 - 11c lb S0, [S1 + #-8257524] #@loadB
1.13 - 120 BReq S0, #3, B19 #@branchConI_reg_imm P=0.100000 C=-1.000000
1.14 -*/
1.15 +
1.16 //Load byte signed
1.17 enc_class load_B_enc (mRegI dst, memory mem) %{
1.18 MacroAssembler _masm(&cbuf);
1.19 @@ -1752,50 +1745,10 @@
1.20 int disp = $mem$$disp;
1.21
1.22 if( index != 0 ) {
1.23 - if( Assembler::is_simm16(disp) ) {
1.24 - if( UseLoongsonISA ) {
1.25 - if (scale == 0) {
1.26 - __ gslbx(as_Register(dst), as_Register(base), as_Register(index), disp);
1.27 - } else {
1.28 - __ dsll(AT, as_Register(index), scale);
1.29 - __ gslbx(as_Register(dst), as_Register(base), AT, disp);
1.30 - }
1.31 - } else {
1.32 - if (scale == 0) {
1.33 - __ addu(AT, as_Register(base), as_Register(index));
1.34 - } else {
1.35 - __ dsll(AT, as_Register(index), scale);
1.36 - __ addu(AT, as_Register(base), AT);
1.37 - }
1.38 - __ lb(as_Register(dst), AT, disp);
1.39 - }
1.40 - } else {
1.41 - if (scale == 0) {
1.42 - __ addu(AT, as_Register(base), as_Register(index));
1.43 - } else {
1.44 - __ dsll(AT, as_Register(index), scale);
1.45 - __ addu(AT, as_Register(base), AT);
1.46 - }
1.47 - __ move(T9, disp);
1.48 - if( UseLoongsonISA ) {
1.49 - __ gslbx(as_Register(dst), AT, T9, 0);
1.50 - } else {
1.51 - __ addu(AT, AT, T9);
1.52 - __ lb(as_Register(dst), AT, 0);
1.53 - }
1.54 - }
1.55 + assert(UseLoongsonISA, "Only supported for Loongson CPUs");
1.56 + __ gslbx(as_Register(dst), as_Register(base), as_Register(index), disp);
1.57 } else {
1.58 - if( Assembler::is_simm16(disp) ) {
1.59 - __ lb(as_Register(dst), as_Register(base), disp);
1.60 - } else {
1.61 - __ move(T9, disp);
1.62 - if( UseLoongsonISA ) {
1.63 - __ gslbx(as_Register(dst), as_Register(base), T9, 0);
1.64 - } else {
1.65 - __ addu(AT, as_Register(base), T9);
1.66 - __ lb(as_Register(dst), AT, 0);
1.67 - }
1.68 - }
1.69 + __ lb(as_Register(dst), as_Register(base), disp);
1.70 }
1.71 %}
1.72
1.73 @@ -2999,50 +2952,11 @@
1.74 int disp = $mem$$disp;
1.75 Register dst_reg = as_Register($dst$$reg);
1.76
1.77 - /*********************2013/03/27**************************
1.78 - * Jin: $base may contain a null object.
1.79 - * Server JIT force the exception_offset to be the pos of
1.80 - * the first instruction.
1.81 - * I insert such a 'null_check' at the beginning.
1.82 - *******************************************************/
1.83 -
1.84 - __ lw(AT, as_Register(base), 0);
1.85 -
1.86 - /*********************2012/10/04**************************
1.87 - * Error case found in SortTest
1.88 - * 337 b java.util.Arrays::sort1 (401 bytes)
1.89 - * B73:
1.90 - * d34 lw T4.lo, [T4 + #16] #@loadL-lo
1.91 - * lw T4.hi, [T4 + #16]+4 #@loadL-hi
1.92 - *
1.93 - * The original instructions generated here are :
1.94 - * __ lw(dst_lo, as_Register(base), disp);
1.95 - * __ lw(dst_hi, as_Register(base), disp + 4);
1.96 - *******************************************************/
1.97 -
1.98 if( index != 0 ) {
1.99 - if (scale == 0) {
1.100 - __ daddu(AT, as_Register(base), as_Register(index));
1.101 - } else {
1.102 - __ dsll(AT, as_Register(index), scale);
1.103 - __ daddu(AT, as_Register(base), AT);
1.104 - }
1.105 - if( Assembler::is_simm16(disp) ) {
1.106 - __ ld(dst_reg, AT, disp);
1.107 - } else {
1.108 - __ move(T9, disp);
1.109 - __ daddu(AT, AT, T9);
1.110 - __ ld(dst_reg, AT, 0);
1.111 - }
1.112 + assert(UseLoongsonISA, "Only supported for Loongson CPUs");
1.113 + __ gsldx(dst_reg, as_Register(base), as_Register(index), disp);
1.114 } else {
1.115 - if( Assembler::is_simm16(disp) ) {
1.116 - __ move(AT, as_Register(base));
1.117 - __ ld(dst_reg, AT, disp);
1.118 - } else {
1.119 - __ move(T9, disp);
1.120 - __ daddu(AT, as_Register(base), T9);
1.121 - __ ld(dst_reg, AT, 0);
1.122 - }
1.123 + __ ld(dst_reg, as_Register(base), disp);
1.124 }
1.125 %}
1.126
1.127 @@ -3055,28 +2969,10 @@
1.128 Register src_reg = as_Register($src$$reg);
1.129
1.130 if( index != 0 ) {
1.131 - if (scale == 0) {
1.132 - __ daddu(AT, as_Register(base), as_Register(index));
1.133 - } else {
1.134 - __ dsll(AT, as_Register(index), scale);
1.135 - __ daddu(AT, as_Register(base), AT);
1.136 - }
1.137 - if( Assembler::is_simm16(disp) ) {
1.138 - __ sd(src_reg, AT, disp);
1.139 - } else {
1.140 - __ move(T9, disp);
1.141 - __ daddu(AT, AT, T9);
1.142 - __ sd(src_reg, AT, 0);
1.143 - }
1.144 + assert(UseLoongsonISA, "Only supported for Loongson CPUs");
1.145 + __ gssdx(src_reg, as_Register(base), as_Register(index), disp);
1.146 } else {
1.147 - if( Assembler::is_simm16(disp) ) {
1.148 - __ move(AT, as_Register(base));
1.149 - __ sd(src_reg, AT, disp);
1.150 - } else {
1.151 - __ move(T9, disp);
1.152 - __ daddu(AT, as_Register(base), T9);
1.153 - __ sd(src_reg, AT, 0);
1.154 - }
1.155 + __ sd(src_reg, as_Register(base), disp);
1.156 }
1.157 %}
1.158
1.159 @@ -3088,28 +2984,10 @@
1.160 int disp = $mem$$disp;
1.161
1.162 if( index != 0 ) {
1.163 - if (scale == 0) {
1.164 - __ daddu(AT, as_Register(base), as_Register(index));
1.165 - } else {
1.166 - __ dsll(AT, as_Register(index), scale);
1.167 - __ daddu(AT, as_Register(base), AT);
1.168 - }
1.169 - if( Assembler::is_simm16(disp) ) {
1.170 - __ sd(R0, AT, disp);
1.171 - } else {
1.172 - __ move(T9, disp);
1.173 - __ addu(AT, AT, T9);
1.174 - __ sd(R0, AT, 0);
1.175 - }
1.176 + assert(UseLoongsonISA, "Only supported for Loongson CPUs");
1.177 + __ gssdx(R0, as_Register(base), as_Register(index), disp);
1.178 } else {
1.179 - if( Assembler::is_simm16(disp) ) {
1.180 - __ move(AT, as_Register(base));
1.181 - __ sd(R0, AT, disp);
1.182 - } else {
1.183 - __ move(T9, disp);
1.184 - __ addu(AT, as_Register(base), T9);
1.185 - __ sd(R0, AT, 0);
1.186 - }
1.187 + __ sd(R0, as_Register(base), disp);
1.188 }
1.189 %}
1.190
