1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/src/cpu/mips/vm/templateTable_mips_64.hpp Fri Apr 29 00:06:10 2016 +0800
1.3 @@ -0,0 +1,40 @@
1.4 +/*
1.5 + * Copyright (c) 2003, 2012, Oracle and/or its affiliates. All rights reserved.
1.6 + * Copyright (c) 2015, 2016, Loongson Technology. All rights reserved.
1.7 + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
1.8 + *
1.9 + * This code is free software; you can redistribute it and/or modify it
1.10 + * under the terms of the GNU General Public License version 2 only, as
1.11 + * published by the Free Software Foundation.
1.12 + *
1.13 + * This code is distributed in the hope that it will be useful, but WITHOUT
1.14 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1.15 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1.16 + * version 2 for more details (a copy is included in the LICENSE file that
1.17 + * accompanied this code).
1.18 + *
1.19 + * You should have received a copy of the GNU General Public License version
1.20 + * 2 along with this work; if not, write to the Free Software Foundation,
1.21 + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
1.22 + *
1.23 + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
1.24 + * or visit www.oracle.com if you need additional information or have any
1.25 + * questions.
1.26 + *
1.27 + */
1.28 +
1.29 +#ifndef CPU_MIPS_VM_TEMPLATETABLE_MIPS_64_HPP
1.30 +#define CPU_MIPS_VM_TEMPLATETABLE_MIPS_64_HPP
1.31 + static void prepare_invoke(int byte_no, Register method, Register index = noreg, Register recv = noreg,
1.32 + Register flags = noreg);
1.33 + static void invokevirtual_helper(Register index, Register recv,
1.34 + Register flags);
1.35 + //static void volatile_barrier(Assembler::Membar_mask_bits order_constraint);
1.36 + static void volatile_barrier();
1.37 +
1.38 + // Helpers
1.39 + static void index_check(Register array, Register index);
1.40 + static void index_check_without_pop(Register array, Register index);
1.41 +
1.42 +#endif // CPU_MIPS_VM_TEMPLATETABLE_MIPS_64_HPP
1.43 +
