1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/src/cpu/mips/vm/globals_mips.hpp Fri Apr 29 00:06:10 2016 +0800
1.3 @@ -0,0 +1,202 @@
1.4 +/*
1.5 + * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved.
1.6 + * Copyright (c) 2015, 2016, Loongson Technology. All rights reserved.
1.7 + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
1.8 + *
1.9 + * This code is free software; you can redistribute it and/or modify it
1.10 + * under the terms of the GNU General Public License version 2 only, as
1.11 + * published by the Free Software Foundation.
1.12 + *
1.13 + * This code is distributed in the hope that it will be useful, but WITHOUT
1.14 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1.15 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1.16 + * version 2 for more details (a copy is included in the LICENSE file that
1.17 + * accompanied this code).
1.18 + *
1.19 + * You should have received a copy of the GNU General Public License version
1.20 + * 2 along with this work; if not, write to the Free Software Foundation,
1.21 + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
1.22 + *
1.23 + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
1.24 + * or visit www.oracle.com if you need additional information or have any
1.25 + * questions.
1.26 + *
1.27 + */
1.28 +
1.29 +#ifndef CPU_MIPS_VM_GLOBALS_MIPS_HPP
1.30 +#define CPU_MIPS_VM_GLOBALS_MIPS_HPP
1.31 +
1.32 +#include "utilities/globalDefinitions.hpp"
1.33 +#include "utilities/macros.hpp"
1.34 +
1.35 +//
1.36 +// Sets the default values for platform dependent flags used by the runtime system.
1.37 +// (see globals.hpp)
1.38 +//
1.39 +#ifdef CORE
1.40 +define_pd_global(bool, UseSSE, 0);
1.41 +#endif /* CORE */
1.42 +define_pd_global(bool, ConvertSleepToYield, true);
1.43 +define_pd_global(bool, ShareVtableStubs, true);
1.44 +define_pd_global(bool, CountInterpCalls, true);
1.45 +
1.46 +define_pd_global(bool, ImplicitNullChecks, true); // Generate code for implicit null checks
1.47 +define_pd_global(bool, TrapBasedNullChecks, false); // Not needed on x86.
1.48 +define_pd_global(bool, UncommonNullCast, true); // Uncommon-trap NULLs passed to check cast
1.49 +define_pd_global(bool, NeedsDeoptSuspend, false); // only register window machines need this
1.50 +
1.51 +// See 4827828 for this change. There is no globals_core_i486.hpp. I can't
1.52 +// assign a different value for C2 without touching a number of files. Use
1.53 +// #ifdef to minimize the change as it's late in Mantis. -- FIXME.
1.54 +// c1 doesn't have this problem because the fix to 4858033 assures us
1.55 +// the the vep is aligned at CodeEntryAlignment whereas c2 only aligns
1.56 +// the uep and the vep doesn't get real alignment but just slops on by
1.57 +// only assured that the entry instruction meets the 5 byte size requirement.
1.58 +define_pd_global(intx, CodeEntryAlignment, 32);
1.59 +define_pd_global(intx, OptoLoopAlignment, 16);
1.60 +define_pd_global(intx, InlineFrequencyCount, 100);
1.61 +define_pd_global(intx, InlineSmallCode, 1000);
1.62 +
1.63 +define_pd_global(uintx, TLABSize, 0);
1.64 +define_pd_global(uintx, NewSize, 1024 * K);
1.65 +define_pd_global(intx, PreInflateSpin, 10);
1.66 +
1.67 +define_pd_global(intx, PrefetchCopyIntervalInBytes, -1);
1.68 +define_pd_global(intx, PrefetchScanIntervalInBytes, -1);
1.69 +define_pd_global(intx, PrefetchFieldsAhead, -1);
1.70 +
1.71 +define_pd_global(intx, StackYellowPages, 2);
1.72 +define_pd_global(intx, StackRedPages, 1);
1.73 +define_pd_global(intx, StackShadowPages, 3 DEBUG_ONLY(+1));
1.74 +
1.75 +define_pd_global(bool, RewriteBytecodes, true);
1.76 +define_pd_global(bool, RewriteFrequentPairs, true);
1.77 +#ifdef _ALLBSD_SOURCE
1.78 +define_pd_global(bool, UseMembar, true);
1.79 +#else
1.80 +define_pd_global(bool, UseMembar, false);
1.81 +#endif
1.82 +// GC Ergo Flags
1.83 +define_pd_global(intx, CMSYoungGenPerWorker, 64*M); // default max size of CMS young gen, per GC worker thread
1.84 +
1.85 +define_pd_global(uintx, TypeProfileLevel, 111);
1.86 +
1.87 +// Only c2 cares about this at the moment
1.88 +define_pd_global(intx, AllocatePrefetchStyle, 2);
1.89 +define_pd_global(intx, AllocatePrefetchDistance, -1);
1.90 +
1.91 +#define ARCH_FLAGS(develop, product, diagnostic, experimental, notproduct) \
1.92 + \
1.93 + develop(bool, IEEEPrecision, true, \
1.94 + "Enables IEEE precision (for INTEL only)") \
1.95 + \
1.96 + product(intx, FenceInstruction, 0, \
1.97 + "(Unsafe,Unstable) Experimental") \
1.98 + \
1.99 + product(intx, ReadPrefetchInstr, 0, \
1.100 + "Prefetch instruction to prefetch ahead") \
1.101 + \
1.102 + product(bool, UseStoreImmI16, true, \
1.103 + "Use store immediate 16-bits value instruction on x86") \
1.104 + \
1.105 + product(intx, UseAVX, 99, \
1.106 + "Highest supported AVX instructions set on x86/x64") \
1.107 + \
1.108 + diagnostic(bool, UseIncDec, true, \
1.109 + "Use INC, DEC instructions on x86") \
1.110 + \
1.111 + product(bool, UseNewLongLShift, false, \
1.112 + "Use optimized bitwise shift left") \
1.113 + \
1.114 + product(bool, UseAddressNop, false, \
1.115 + "Use '0F 1F [addr]' NOP instructions on x86 cpus") \
1.116 + \
1.117 + product(bool, UseXmmLoadAndClearUpper, true, \
1.118 + "Load low part of XMM register and clear upper part") \
1.119 + \
1.120 + product(bool, UseXmmRegToRegMoveAll, false, \
1.121 + "Copy all XMM register bits when moving value between registers") \
1.122 + \
1.123 + product(bool, UseXmmI2D, false, \
1.124 + "Use SSE2 CVTDQ2PD instruction to convert Integer to Double") \
1.125 + \
1.126 + product(bool, UseXmmI2F, false, \
1.127 + "Use SSE2 CVTDQ2PS instruction to convert Integer to Float") \
1.128 + \
1.129 + product(bool, UseUnalignedLoadStores, false, \
1.130 + "Use SSE2 MOVDQU instruction for Arraycopy") \
1.131 + \
1.132 + /* assembler */ \
1.133 + product(bool, Use486InstrsOnly, false, \
1.134 + "Use 80486 Compliant instruction subset") \
1.135 + \
1.136 + product(bool, UseCountLeadingZerosInstruction, false, \
1.137 + "Use count leading zeros instruction") \
1.138 + \
1.139 + /* 2014/04/22 Fu: Added to improve the startup performance */ \
1.140 + product(intx, MaxCompileQueueSize, 64, \
1.141 + "The maximum size of compile queue") \
1.142 + \
1.143 + /* 2014/07/07 Fu: Added to implement the size-and-speed scheduling */ \
1.144 + product(intx, FactorOfSizeScheduling, 90, \
1.145 + "The impact factor of size in the size-and-speed scheduling") \
1.146 + \
1.147 + product(intx, MinWatchTime, 800, \
1.148 + "The min time to determine whether to remove a task in queue") \
1.149 + \
1.150 + product(intx, MinUpdateTime, 5, \
1.151 + "The min time to update the speed of a method") \
1.152 + \
1.153 + /* Use Restricted Transactional Memory for lock eliding */ \
1.154 + experimental(bool, UseRTMLocking, false, \
1.155 + "Enable RTM lock eliding for inflated locks in compiled code") \
1.156 + \
1.157 + experimental(bool, UseRTMForStackLocks, false, \
1.158 + "Enable RTM lock eliding for stack locks in compiled code") \
1.159 + \
1.160 + experimental(bool, UseRTMDeopt, false, \
1.161 + "Perform deopt and recompilation based on RTM abort ratio") \
1.162 + \
1.163 + experimental(uintx, RTMRetryCount, 5, \
1.164 + "Number of RTM retries on lock abort or busy") \
1.165 + \
1.166 + experimental(intx, RTMSpinLoopCount, 100, \
1.167 + "Spin count for lock to become free before RTM retry") \
1.168 + \
1.169 + experimental(intx, RTMAbortThreshold, 1000, \
1.170 + "Calculate abort ratio after this number of aborts") \
1.171 + \
1.172 + experimental(intx, RTMLockingThreshold, 10000, \
1.173 + "Lock count at which to do RTM lock eliding without " \
1.174 + "abort ratio calculation") \
1.175 + \
1.176 + experimental(intx, RTMAbortRatio, 50, \
1.177 + "Lock abort ratio at which to stop use RTM lock eliding") \
1.178 + \
1.179 + experimental(intx, RTMTotalCountIncrRate, 64, \
1.180 + "Increment total RTM attempted lock count once every n times") \
1.181 + \
1.182 + experimental(intx, RTMLockingCalculationDelay, 0, \
1.183 + "Number of milliseconds to wait before start calculating aborts " \
1.184 + "for RTM locking") \
1.185 + \
1.186 + experimental(bool, UseRTMXendForLockBusy, true, \
1.187 + "Use RTM Xend instead of Xabort when lock busy") \
1.188 + \
1.189 + product(intx, MaxUpdateTime, 80, \
1.190 + "The max time to update the speed of a method") \
1.191 + \
1.192 + product(intx, InvocationOldThreshold, 12000, \
1.193 + "The invocation counter threshold for an old method") \
1.194 + \
1.195 + product(intx, LoopOldThreshold, 20000, \
1.196 + "The backedge counter threshold for an old method") \
1.197 + \
1.198 + product(bool, UseCountTrailingZerosInstruction, false, \
1.199 + "Use count trailing zeros instruction") \
1.200 + \
1.201 + product(bool, UseBMI1Instructions, false, \
1.202 + "Use BMI instructions")
1.203 +
1.204 +#endif // CPU_MIPS_VM_GLOBALS_MIPS_HPP
1.205 +
