1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/src/cpu/mips/vm/c1_Defs_mips.hpp Fri Apr 29 00:06:10 2016 +0800
1.3 @@ -0,0 +1,86 @@
1.4 +/*
1.5 + * Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved.
1.6 + * Copyright (c) 2015, 2016, Loongson Technology. All rights reserved.
1.7 + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
1.8 + *
1.9 + * This code is free software; you can redistribute it and/or modify it
1.10 + * under the terms of the GNU General Public License version 2 only, as
1.11 + * published by the Free Software Foundation.
1.12 + *
1.13 + * This code is distributed in the hope that it will be useful, but WITHOUT
1.14 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1.15 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1.16 + * version 2 for more details (a copy is included in the LICENSE file that
1.17 + * accompanied this code).
1.18 + *
1.19 + * You should have received a copy of the GNU General Public License version
1.20 + * 2 along with this work; if not, write to the Free Software Foundation,
1.21 + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
1.22 + *
1.23 + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
1.24 + * or visit www.oracle.com if you need additional information or have any
1.25 + * questions.
1.26 + *
1.27 + */
1.28 +
1.29 +#ifndef CPU_MIPS_VM_C1_DEFS_MIPS_HPP
1.30 +#define CPU_MIPS_VM_C1_DEFS_MIPS_HPP
1.31 +
1.32 +// native word offsets from memory address (little endian)
1.33 +enum {
1.34 + pd_lo_word_offset_in_bytes = 0,
1.35 + pd_hi_word_offset_in_bytes = BytesPerWord
1.36 +};
1.37 +
1.38 +// explicit rounding operations are required to implement the strictFP mode
1.39 +// i486 is true here, i dont think gs2 need this
1.40 +// by yjl 8/15/2005
1.41 +enum {
1.42 + pd_strict_fp_requires_explicit_rounding = false
1.43 +};
1.44 +
1.45 +
1.46 +// registers
1.47 +enum {
1.48 + pd_nof_cpu_regs_frame_map = 32, // number of registers used during code emission
1.49 + // v0, v1, t0-t7, s0-s7
1.50 + // now, we just think s# as caller saved. maybe we should change this to allow cache local
1.51 + // pd_nof_caller_save_cpu_regs_frame_map = 18, // number of registers killed by calls
1.52 + // t0-t7, s0-s7, v0, v1
1.53 +
1.54 + pd_nof_caller_save_cpu_regs_frame_map = 18, // number of registers killed by calls
1.55 + pd_nof_cpu_regs_reg_alloc = 18, // number of registers that are visible to register allocator
1.56 + pd_nof_cpu_regs_linearscan = 32, // number of registers visible to linear scan
1.57 + pd_first_cpu_reg = 0,
1.58 + pd_last_cpu_reg = 31,
1.59 + pd_last_allocatable_cpu_reg=20,
1.60 + pd_first_callee_saved_reg = 0,
1.61 + pd_last_callee_saved_reg = 13,
1.62 +
1.63 +#ifdef _LP64
1.64 + pd_nof_fpu_regs_frame_map = 32, // number of registers used during code emission
1.65 + pd_nof_fpu_regs_reg_alloc = 32, // number of registers that are visible to register allocator
1.66 + pd_nof_caller_save_fpu_regs_frame_map = 32, // number of fpu registers killed by calls
1.67 + pd_nof_fpu_regs_linearscan = 32,// number of registers visible linear scan
1.68 +#else
1.69 + pd_nof_fpu_regs_frame_map = 16, // number of registers used during code emission
1.70 + pd_nof_fpu_regs_reg_alloc = 16, // number of registers that are visible to register allocator
1.71 + pd_nof_caller_save_fpu_regs_frame_map = 16, // number of fpu registers killed by calls
1.72 + pd_nof_fpu_regs_linearscan = 16,// number of registers visible linear scan
1.73 +#endif
1.74 + pd_first_fpu_reg = pd_nof_cpu_regs_frame_map,
1.75 + pd_last_fpu_reg = pd_nof_cpu_regs_frame_map + pd_nof_fpu_regs_frame_map - 1,
1.76 +
1.77 + pd_nof_xmm_regs_linearscan = 0,
1.78 + pd_nof_caller_save_xmm_regs = 0,
1.79 + pd_first_xmm_reg = -1,
1.80 + pd_last_xmm_reg = -1
1.81 +};
1.82 +
1.83 +
1.84 +// encoding of float value in debug info:
1.85 +enum {
1.86 + pd_float_saved_as_double = true
1.87 +};
1.88 +
1.89 +#endif // CPU_MIPS_VM_C1_DEFS_MIPS_HPP
