1.1 --- a/src/cpu/mips/vm/mips_64.ad Mon Feb 20 09:17:43 2017 +0800 1.2 +++ b/src/cpu/mips/vm/mips_64.ad Mon Feb 20 13:00:42 2017 +0800 1.3 @@ -12387,28 +12387,66 @@ 1.4 int disp = $mem$$disp; 1.5 1.6 if( index != 0 ) { 1.7 - if(scale != 0) { 1.8 - __ dsll(T9, as_Register(index), scale); 1.9 - __ addu(AT, as_Register(base), T9); 1.10 - } else { 1.11 - __ daddu(AT, as_Register(base), as_Register(index)); 1.12 - } 1.13 - if( Assembler::is_simm16(disp) ) { 1.14 - __ sw(R0, AT, disp); 1.15 - } else { 1.16 - __ move(T9, disp); 1.17 - __ addu(AT, AT, T9); 1.18 - __ sw(R0, AT, 0); 1.19 - } 1.20 - 1.21 - } else { 1.22 - if( Assembler::is_simm16(disp) ) { 1.23 - __ sw(R0, as_Register(base), disp); 1.24 - } else { 1.25 - __ move(T9, disp); 1.26 - __ addu(AT, as_Register(base), T9); 1.27 - __ sw(R0, AT, 0); 1.28 - } 1.29 + if ( UseLoongsonISA ) { 1.30 + if ( Assembler::is_simm(disp, 8) ) { 1.31 + if ( scale == 0 ) { 1.32 + __ gsswx(R0, as_Register(base), as_Register(index), disp); 1.33 + } else { 1.34 + __ dsll(T9, as_Register(index), scale); 1.35 + __ gsswx(R0, as_Register(base), T9, disp); 1.36 + } 1.37 + } else if ( Assembler::is_simm16(disp) ) { 1.38 + if ( scale == 0 ) { 1.39 + __ daddu(AT, as_Register(base), as_Register(index)); 1.40 + } else { 1.41 + __ dsll(T9, as_Register(index), scale); 1.42 + __ daddu(AT, as_Register(base), T9); 1.43 + } 1.44 + __ sw(R0, AT, disp); 1.45 + } else { 1.46 + if ( scale == 0 ) { 1.47 + __ move(T9, disp); 1.48 + __ daddu(AT, as_Register(index), T9); 1.49 + __ gsswx(R0, as_Register(base), AT, 0); 1.50 + } else { 1.51 + __ dsll(T9, as_Register(index), scale); 1.52 + __ move(AT, disp); 1.53 + __ daddu(AT, AT, T9); 1.54 + __ gsswx(R0, as_Register(base), AT, 0); 1.55 + } 1.56 + } 1.57 + } else { //not use loongson isa 1.58 + if(scale != 0) { 1.59 + __ dsll(T9, as_Register(index), scale); 1.60 + __ daddu(AT, as_Register(base), T9); 1.61 + } else { 1.62 + __ daddu(AT, as_Register(base), as_Register(index)); 1.63 + } 1.64 + if( Assembler::is_simm16(disp) ) { 1.65 + __ sw(R0, AT, disp); 1.66 + } else { 1.67 + __ move(T9, disp); 1.68 + __ daddu(AT, AT, T9); 1.69 + __ sw(R0, AT, 0); 1.70 + } 1.71 + } 1.72 + } else { //index is 0 1.73 + if ( UseLoongsonISA ) { 1.74 + if ( Assembler::is_simm16(disp) ) { 1.75 + __ sw(R0, as_Register(base), disp); 1.76 + } else { 1.77 + __ move(T9, disp); 1.78 + __ gsswx(R0, as_Register(base), T9, 0); 1.79 + } 1.80 + } else { 1.81 + if( Assembler::is_simm16(disp) ) { 1.82 + __ sw(R0, as_Register(base), disp); 1.83 + } else { 1.84 + __ move(T9, disp); 1.85 + __ daddu(AT, as_Register(base), T9); 1.86 + __ sw(R0, AT, 0); 1.87 + } 1.88 + } 1.89 } 1.90 %} 1.91 ins_pipe( ialu_storeI );