src/cpu/sparc/vm/templateTable_sparc.cpp

changeset 2816
286c498ae0d4
parent 2811
08ccee2c4dbf
parent 2784
92add02409c9
child 2982
ddd894528dbc
     1.1 --- a/src/cpu/sparc/vm/templateTable_sparc.cpp	Thu Apr 28 14:00:13 2011 -0700
     1.2 +++ b/src/cpu/sparc/vm/templateTable_sparc.cpp	Fri Apr 29 11:15:30 2011 -0700
     1.3 @@ -57,7 +57,11 @@
     1.4      case BarrierSet::G1SATBCT:
     1.5      case BarrierSet::G1SATBCTLogging:
     1.6        {
     1.7 -        __ g1_write_barrier_pre( base, index, offset, tmp, /*preserve_o_regs*/true);
     1.8 +        // Load and record the previous value.
     1.9 +        __ g1_write_barrier_pre(base, index, offset,
    1.10 +                                noreg /* pre_val */,
    1.11 +                                tmp, true /*preserve_o_regs*/);
    1.12 +
    1.13          if (index == noreg ) {
    1.14            assert(Assembler::is_simm13(offset), "fix this code");
    1.15            __ store_heap_oop(val, base, offset);

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