1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/src/cpu/x86/vm/vm_version_x86.cpp Mon Feb 23 12:02:30 2009 -0800
1.3 @@ -0,0 +1,514 @@
1.4 +/*
1.5 + * Copyright 1997-2009 Sun Microsystems, Inc. All Rights Reserved.
1.6 + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
1.7 + *
1.8 + * This code is free software; you can redistribute it and/or modify it
1.9 + * under the terms of the GNU General Public License version 2 only, as
1.10 + * published by the Free Software Foundation.
1.11 + *
1.12 + * This code is distributed in the hope that it will be useful, but WITHOUT
1.13 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1.14 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1.15 + * version 2 for more details (a copy is included in the LICENSE file that
1.16 + * accompanied this code).
1.17 + *
1.18 + * You should have received a copy of the GNU General Public License version
1.19 + * 2 along with this work; if not, write to the Free Software Foundation,
1.20 + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
1.21 + *
1.22 + * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
1.23 + * CA 95054 USA or visit www.sun.com if you need additional information or
1.24 + * have any questions.
1.25 + *
1.26 + */
1.27 +
1.28 +# include "incls/_precompiled.incl"
1.29 +# include "incls/_vm_version_x86.cpp.incl"
1.30 +
1.31 +
1.32 +int VM_Version::_cpu;
1.33 +int VM_Version::_model;
1.34 +int VM_Version::_stepping;
1.35 +int VM_Version::_cpuFeatures;
1.36 +const char* VM_Version::_features_str = "";
1.37 +VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, };
1.38 +
1.39 +static BufferBlob* stub_blob;
1.40 +static const int stub_size = 300;
1.41 +
1.42 +extern "C" {
1.43 + typedef void (*getPsrInfo_stub_t)(void*);
1.44 +}
1.45 +static getPsrInfo_stub_t getPsrInfo_stub = NULL;
1.46 +
1.47 +
1.48 +class VM_Version_StubGenerator: public StubCodeGenerator {
1.49 + public:
1.50 +
1.51 + VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {}
1.52 +
1.53 + address generate_getPsrInfo() {
1.54 + // Flags to test CPU type.
1.55 + const uint32_t EFL_AC = 0x40000;
1.56 + const uint32_t EFL_ID = 0x200000;
1.57 + // Values for when we don't have a CPUID instruction.
1.58 + const int CPU_FAMILY_SHIFT = 8;
1.59 + const uint32_t CPU_FAMILY_386 = (3 << CPU_FAMILY_SHIFT);
1.60 + const uint32_t CPU_FAMILY_486 = (4 << CPU_FAMILY_SHIFT);
1.61 +
1.62 + Label detect_486, cpu486, detect_586, std_cpuid1;
1.63 + Label ext_cpuid1, ext_cpuid5, done;
1.64 +
1.65 + StubCodeMark mark(this, "VM_Version", "getPsrInfo_stub");
1.66 +# define __ _masm->
1.67 +
1.68 + address start = __ pc();
1.69 +
1.70 + //
1.71 + // void getPsrInfo(VM_Version::CpuidInfo* cpuid_info);
1.72 + //
1.73 + // LP64: rcx and rdx are first and second argument registers on windows
1.74 +
1.75 + __ push(rbp);
1.76 +#ifdef _LP64
1.77 + __ mov(rbp, c_rarg0); // cpuid_info address
1.78 +#else
1.79 + __ movptr(rbp, Address(rsp, 8)); // cpuid_info address
1.80 +#endif
1.81 + __ push(rbx);
1.82 + __ push(rsi);
1.83 + __ pushf(); // preserve rbx, and flags
1.84 + __ pop(rax);
1.85 + __ push(rax);
1.86 + __ mov(rcx, rax);
1.87 + //
1.88 + // if we are unable to change the AC flag, we have a 386
1.89 + //
1.90 + __ xorl(rax, EFL_AC);
1.91 + __ push(rax);
1.92 + __ popf();
1.93 + __ pushf();
1.94 + __ pop(rax);
1.95 + __ cmpptr(rax, rcx);
1.96 + __ jccb(Assembler::notEqual, detect_486);
1.97 +
1.98 + __ movl(rax, CPU_FAMILY_386);
1.99 + __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
1.100 + __ jmp(done);
1.101 +
1.102 + //
1.103 + // If we are unable to change the ID flag, we have a 486 which does
1.104 + // not support the "cpuid" instruction.
1.105 + //
1.106 + __ bind(detect_486);
1.107 + __ mov(rax, rcx);
1.108 + __ xorl(rax, EFL_ID);
1.109 + __ push(rax);
1.110 + __ popf();
1.111 + __ pushf();
1.112 + __ pop(rax);
1.113 + __ cmpptr(rcx, rax);
1.114 + __ jccb(Assembler::notEqual, detect_586);
1.115 +
1.116 + __ bind(cpu486);
1.117 + __ movl(rax, CPU_FAMILY_486);
1.118 + __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
1.119 + __ jmp(done);
1.120 +
1.121 + //
1.122 + // At this point, we have a chip which supports the "cpuid" instruction
1.123 + //
1.124 + __ bind(detect_586);
1.125 + __ xorl(rax, rax);
1.126 + __ cpuid();
1.127 + __ orl(rax, rax);
1.128 + __ jcc(Assembler::equal, cpu486); // if cpuid doesn't support an input
1.129 + // value of at least 1, we give up and
1.130 + // assume a 486
1.131 + __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset())));
1.132 + __ movl(Address(rsi, 0), rax);
1.133 + __ movl(Address(rsi, 4), rbx);
1.134 + __ movl(Address(rsi, 8), rcx);
1.135 + __ movl(Address(rsi,12), rdx);
1.136 +
1.137 + __ cmpl(rax, 3); // Is cpuid(0x4) supported?
1.138 + __ jccb(Assembler::belowEqual, std_cpuid1);
1.139 +
1.140 + //
1.141 + // cpuid(0x4) Deterministic cache params
1.142 + //
1.143 + __ movl(rax, 4);
1.144 + __ xorl(rcx, rcx); // L1 cache
1.145 + __ cpuid();
1.146 + __ push(rax);
1.147 + __ andl(rax, 0x1f); // Determine if valid cache parameters used
1.148 + __ orl(rax, rax); // eax[4:0] == 0 indicates invalid cache
1.149 + __ pop(rax);
1.150 + __ jccb(Assembler::equal, std_cpuid1);
1.151 +
1.152 + __ lea(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset())));
1.153 + __ movl(Address(rsi, 0), rax);
1.154 + __ movl(Address(rsi, 4), rbx);
1.155 + __ movl(Address(rsi, 8), rcx);
1.156 + __ movl(Address(rsi,12), rdx);
1.157 +
1.158 + //
1.159 + // Standard cpuid(0x1)
1.160 + //
1.161 + __ bind(std_cpuid1);
1.162 + __ movl(rax, 1);
1.163 + __ cpuid();
1.164 + __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
1.165 + __ movl(Address(rsi, 0), rax);
1.166 + __ movl(Address(rsi, 4), rbx);
1.167 + __ movl(Address(rsi, 8), rcx);
1.168 + __ movl(Address(rsi,12), rdx);
1.169 +
1.170 + __ movl(rax, 0x80000000);
1.171 + __ cpuid();
1.172 + __ cmpl(rax, 0x80000000); // Is cpuid(0x80000001) supported?
1.173 + __ jcc(Assembler::belowEqual, done);
1.174 + __ cmpl(rax, 0x80000004); // Is cpuid(0x80000005) supported?
1.175 + __ jccb(Assembler::belowEqual, ext_cpuid1);
1.176 + __ cmpl(rax, 0x80000007); // Is cpuid(0x80000008) supported?
1.177 + __ jccb(Assembler::belowEqual, ext_cpuid5);
1.178 + //
1.179 + // Extended cpuid(0x80000008)
1.180 + //
1.181 + __ movl(rax, 0x80000008);
1.182 + __ cpuid();
1.183 + __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset())));
1.184 + __ movl(Address(rsi, 0), rax);
1.185 + __ movl(Address(rsi, 4), rbx);
1.186 + __ movl(Address(rsi, 8), rcx);
1.187 + __ movl(Address(rsi,12), rdx);
1.188 +
1.189 + //
1.190 + // Extended cpuid(0x80000005)
1.191 + //
1.192 + __ bind(ext_cpuid5);
1.193 + __ movl(rax, 0x80000005);
1.194 + __ cpuid();
1.195 + __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset())));
1.196 + __ movl(Address(rsi, 0), rax);
1.197 + __ movl(Address(rsi, 4), rbx);
1.198 + __ movl(Address(rsi, 8), rcx);
1.199 + __ movl(Address(rsi,12), rdx);
1.200 +
1.201 + //
1.202 + // Extended cpuid(0x80000001)
1.203 + //
1.204 + __ bind(ext_cpuid1);
1.205 + __ movl(rax, 0x80000001);
1.206 + __ cpuid();
1.207 + __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset())));
1.208 + __ movl(Address(rsi, 0), rax);
1.209 + __ movl(Address(rsi, 4), rbx);
1.210 + __ movl(Address(rsi, 8), rcx);
1.211 + __ movl(Address(rsi,12), rdx);
1.212 +
1.213 + //
1.214 + // return
1.215 + //
1.216 + __ bind(done);
1.217 + __ popf();
1.218 + __ pop(rsi);
1.219 + __ pop(rbx);
1.220 + __ pop(rbp);
1.221 + __ ret(0);
1.222 +
1.223 +# undef __
1.224 +
1.225 + return start;
1.226 + };
1.227 +};
1.228 +
1.229 +
1.230 +void VM_Version::get_processor_features() {
1.231 +
1.232 + _cpu = 4; // 486 by default
1.233 + _model = 0;
1.234 + _stepping = 0;
1.235 + _cpuFeatures = 0;
1.236 + _logical_processors_per_package = 1;
1.237 +
1.238 + if (!Use486InstrsOnly) {
1.239 + // Get raw processor info
1.240 + getPsrInfo_stub(&_cpuid_info);
1.241 + assert_is_initialized();
1.242 + _cpu = extended_cpu_family();
1.243 + _model = extended_cpu_model();
1.244 + _stepping = cpu_stepping();
1.245 +
1.246 + if (cpu_family() > 4) { // it supports CPUID
1.247 + _cpuFeatures = feature_flags();
1.248 + // Logical processors are only available on P4s and above,
1.249 + // and only if hyperthreading is available.
1.250 + _logical_processors_per_package = logical_processor_count();
1.251 + }
1.252 + }
1.253 +
1.254 + _supports_cx8 = supports_cmpxchg8();
1.255 +
1.256 +#ifdef _LP64
1.257 + // OS should support SSE for x64 and hardware should support at least SSE2.
1.258 + if (!VM_Version::supports_sse2()) {
1.259 + vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported");
1.260 + }
1.261 +#endif
1.262 +
1.263 + // If the OS doesn't support SSE, we can't use this feature even if the HW does
1.264 + if (!os::supports_sse())
1.265 + _cpuFeatures &= ~(CPU_SSE|CPU_SSE2|CPU_SSE3|CPU_SSSE3|CPU_SSE4A|CPU_SSE4_1|CPU_SSE4_2);
1.266 +
1.267 + if (UseSSE < 4) {
1.268 + _cpuFeatures &= ~CPU_SSE4_1;
1.269 + _cpuFeatures &= ~CPU_SSE4_2;
1.270 + }
1.271 +
1.272 + if (UseSSE < 3) {
1.273 + _cpuFeatures &= ~CPU_SSE3;
1.274 + _cpuFeatures &= ~CPU_SSSE3;
1.275 + _cpuFeatures &= ~CPU_SSE4A;
1.276 + }
1.277 +
1.278 + if (UseSSE < 2)
1.279 + _cpuFeatures &= ~CPU_SSE2;
1.280 +
1.281 + if (UseSSE < 1)
1.282 + _cpuFeatures &= ~CPU_SSE;
1.283 +
1.284 + if (logical_processors_per_package() == 1) {
1.285 + // HT processor could be installed on a system which doesn't support HT.
1.286 + _cpuFeatures &= ~CPU_HT;
1.287 + }
1.288 +
1.289 + char buf[256];
1.290 + jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
1.291 + cores_per_cpu(), threads_per_core(),
1.292 + cpu_family(), _model, _stepping,
1.293 + (supports_cmov() ? ", cmov" : ""),
1.294 + (supports_cmpxchg8() ? ", cx8" : ""),
1.295 + (supports_fxsr() ? ", fxsr" : ""),
1.296 + (supports_mmx() ? ", mmx" : ""),
1.297 + (supports_sse() ? ", sse" : ""),
1.298 + (supports_sse2() ? ", sse2" : ""),
1.299 + (supports_sse3() ? ", sse3" : ""),
1.300 + (supports_ssse3()? ", ssse3": ""),
1.301 + (supports_sse4_1() ? ", sse4.1" : ""),
1.302 + (supports_sse4_2() ? ", sse4.2" : ""),
1.303 + (supports_mmx_ext() ? ", mmxext" : ""),
1.304 + (supports_3dnow() ? ", 3dnow" : ""),
1.305 + (supports_3dnow2() ? ", 3dnowext" : ""),
1.306 + (supports_sse4a() ? ", sse4a": ""),
1.307 + (supports_ht() ? ", ht": ""));
1.308 + _features_str = strdup(buf);
1.309 +
1.310 + // UseSSE is set to the smaller of what hardware supports and what
1.311 + // the command line requires. I.e., you cannot set UseSSE to 2 on
1.312 + // older Pentiums which do not support it.
1.313 + if( UseSSE > 4 ) UseSSE=4;
1.314 + if( UseSSE < 0 ) UseSSE=0;
1.315 + if( !supports_sse4_1() ) // Drop to 3 if no SSE4 support
1.316 + UseSSE = MIN2((intx)3,UseSSE);
1.317 + if( !supports_sse3() ) // Drop to 2 if no SSE3 support
1.318 + UseSSE = MIN2((intx)2,UseSSE);
1.319 + if( !supports_sse2() ) // Drop to 1 if no SSE2 support
1.320 + UseSSE = MIN2((intx)1,UseSSE);
1.321 + if( !supports_sse () ) // Drop to 0 if no SSE support
1.322 + UseSSE = 0;
1.323 +
1.324 + // On new cpus instructions which update whole XMM register should be used
1.325 + // to prevent partial register stall due to dependencies on high half.
1.326 + //
1.327 + // UseXmmLoadAndClearUpper == true --> movsd(xmm, mem)
1.328 + // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem)
1.329 + // UseXmmRegToRegMoveAll == true --> movaps(xmm, xmm), movapd(xmm, xmm).
1.330 + // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm), movsd(xmm, xmm).
1.331 +
1.332 + if( is_amd() ) { // AMD cpus specific settings
1.333 + if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) {
1.334 + // Use it on new AMD cpus starting from Opteron.
1.335 + UseAddressNop = true;
1.336 + }
1.337 + if( supports_sse2() && FLAG_IS_DEFAULT(UseNewLongLShift) ) {
1.338 + // Use it on new AMD cpus starting from Opteron.
1.339 + UseNewLongLShift = true;
1.340 + }
1.341 + if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
1.342 + if( supports_sse4a() ) {
1.343 + UseXmmLoadAndClearUpper = true; // use movsd only on '10h' Opteron
1.344 + } else {
1.345 + UseXmmLoadAndClearUpper = false;
1.346 + }
1.347 + }
1.348 + if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
1.349 + if( supports_sse4a() ) {
1.350 + UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h'
1.351 + } else {
1.352 + UseXmmRegToRegMoveAll = false;
1.353 + }
1.354 + }
1.355 + if( FLAG_IS_DEFAULT(UseXmmI2F) ) {
1.356 + if( supports_sse4a() ) {
1.357 + UseXmmI2F = true;
1.358 + } else {
1.359 + UseXmmI2F = false;
1.360 + }
1.361 + }
1.362 + if( FLAG_IS_DEFAULT(UseXmmI2D) ) {
1.363 + if( supports_sse4a() ) {
1.364 + UseXmmI2D = true;
1.365 + } else {
1.366 + UseXmmI2D = false;
1.367 + }
1.368 + }
1.369 + }
1.370 +
1.371 + if( is_intel() ) { // Intel cpus specific settings
1.372 + if( FLAG_IS_DEFAULT(UseStoreImmI16) ) {
1.373 + UseStoreImmI16 = false; // don't use it on Intel cpus
1.374 + }
1.375 + if( cpu_family() == 6 || cpu_family() == 15 ) {
1.376 + if( FLAG_IS_DEFAULT(UseAddressNop) ) {
1.377 + // Use it on all Intel cpus starting from PentiumPro
1.378 + UseAddressNop = true;
1.379 + }
1.380 + }
1.381 + if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
1.382 + UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus
1.383 + }
1.384 + if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
1.385 + if( supports_sse3() ) {
1.386 + UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus
1.387 + } else {
1.388 + UseXmmRegToRegMoveAll = false;
1.389 + }
1.390 + }
1.391 + if( cpu_family() == 6 && supports_sse3() ) { // New Intel cpus
1.392 +#ifdef COMPILER2
1.393 + if( FLAG_IS_DEFAULT(MaxLoopPad) ) {
1.394 + // For new Intel cpus do the next optimization:
1.395 + // don't align the beginning of a loop if there are enough instructions
1.396 + // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp)
1.397 + // in current fetch line (OptoLoopAlignment) or the padding
1.398 + // is big (> MaxLoopPad).
1.399 + // Set MaxLoopPad to 11 for new Intel cpus to reduce number of
1.400 + // generated NOP instructions. 11 is the largest size of one
1.401 + // address NOP instruction '0F 1F' (see Assembler::nop(i)).
1.402 + MaxLoopPad = 11;
1.403 + }
1.404 +#endif // COMPILER2
1.405 + if( FLAG_IS_DEFAULT(UseXMMForArrayCopy) ) {
1.406 + UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus
1.407 + }
1.408 + if( supports_sse4_2() && supports_ht() ) { // Newest Intel cpus
1.409 + if( FLAG_IS_DEFAULT(UseUnalignedLoadStores) && UseXMMForArrayCopy ) {
1.410 + UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
1.411 + }
1.412 + }
1.413 + }
1.414 + }
1.415 +
1.416 + assert(0 <= ReadPrefetchInstr && ReadPrefetchInstr <= 3, "invalid value");
1.417 + assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 3, "invalid value");
1.418 +
1.419 + // set valid Prefetch instruction
1.420 + if( ReadPrefetchInstr < 0 ) ReadPrefetchInstr = 0;
1.421 + if( ReadPrefetchInstr > 3 ) ReadPrefetchInstr = 3;
1.422 + if( ReadPrefetchInstr == 3 && !supports_3dnow() ) ReadPrefetchInstr = 0;
1.423 + if( !supports_sse() && supports_3dnow() ) ReadPrefetchInstr = 3;
1.424 +
1.425 + if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0;
1.426 + if( AllocatePrefetchInstr > 3 ) AllocatePrefetchInstr = 3;
1.427 + if( AllocatePrefetchInstr == 3 && !supports_3dnow() ) AllocatePrefetchInstr=0;
1.428 + if( !supports_sse() && supports_3dnow() ) AllocatePrefetchInstr = 3;
1.429 +
1.430 + // Allocation prefetch settings
1.431 + intx cache_line_size = L1_data_cache_line_size();
1.432 + if( cache_line_size > AllocatePrefetchStepSize )
1.433 + AllocatePrefetchStepSize = cache_line_size;
1.434 + if( FLAG_IS_DEFAULT(AllocatePrefetchLines) )
1.435 + AllocatePrefetchLines = 3; // Optimistic value
1.436 + assert(AllocatePrefetchLines > 0, "invalid value");
1.437 + if( AllocatePrefetchLines < 1 ) // set valid value in product VM
1.438 + AllocatePrefetchLines = 1; // Conservative value
1.439 +
1.440 + AllocatePrefetchDistance = allocate_prefetch_distance();
1.441 + AllocatePrefetchStyle = allocate_prefetch_style();
1.442 +
1.443 + if( AllocatePrefetchStyle == 2 && is_intel() &&
1.444 + cpu_family() == 6 && supports_sse3() ) { // watermark prefetching on Core
1.445 +#ifdef _LP64
1.446 + AllocatePrefetchDistance = 384;
1.447 +#else
1.448 + AllocatePrefetchDistance = 320;
1.449 +#endif
1.450 + }
1.451 + assert(AllocatePrefetchDistance % AllocatePrefetchStepSize == 0, "invalid value");
1.452 +
1.453 +#ifdef _LP64
1.454 + // Prefetch settings
1.455 + PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
1.456 + PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
1.457 + PrefetchFieldsAhead = prefetch_fields_ahead();
1.458 +#endif
1.459 +
1.460 +#ifndef PRODUCT
1.461 + if (PrintMiscellaneous && Verbose) {
1.462 + tty->print_cr("Logical CPUs per core: %u",
1.463 + logical_processors_per_package());
1.464 + tty->print_cr("UseSSE=%d",UseSSE);
1.465 + tty->print("Allocation: ");
1.466 + if (AllocatePrefetchStyle <= 0 || UseSSE == 0 && !supports_3dnow()) {
1.467 + tty->print_cr("no prefetching");
1.468 + } else {
1.469 + if (UseSSE == 0 && supports_3dnow()) {
1.470 + tty->print("PREFETCHW");
1.471 + } else if (UseSSE >= 1) {
1.472 + if (AllocatePrefetchInstr == 0) {
1.473 + tty->print("PREFETCHNTA");
1.474 + } else if (AllocatePrefetchInstr == 1) {
1.475 + tty->print("PREFETCHT0");
1.476 + } else if (AllocatePrefetchInstr == 2) {
1.477 + tty->print("PREFETCHT2");
1.478 + } else if (AllocatePrefetchInstr == 3) {
1.479 + tty->print("PREFETCHW");
1.480 + }
1.481 + }
1.482 + if (AllocatePrefetchLines > 1) {
1.483 + tty->print_cr(" %d, %d lines with step %d bytes", AllocatePrefetchDistance, AllocatePrefetchLines, AllocatePrefetchStepSize);
1.484 + } else {
1.485 + tty->print_cr(" %d, one line", AllocatePrefetchDistance);
1.486 + }
1.487 + }
1.488 +
1.489 + if (PrefetchCopyIntervalInBytes > 0) {
1.490 + tty->print_cr("PrefetchCopyIntervalInBytes %d", PrefetchCopyIntervalInBytes);
1.491 + }
1.492 + if (PrefetchScanIntervalInBytes > 0) {
1.493 + tty->print_cr("PrefetchScanIntervalInBytes %d", PrefetchScanIntervalInBytes);
1.494 + }
1.495 + if (PrefetchFieldsAhead > 0) {
1.496 + tty->print_cr("PrefetchFieldsAhead %d", PrefetchFieldsAhead);
1.497 + }
1.498 + }
1.499 +#endif // !PRODUCT
1.500 +}
1.501 +
1.502 +void VM_Version::initialize() {
1.503 + ResourceMark rm;
1.504 + // Making this stub must be FIRST use of assembler
1.505 +
1.506 + stub_blob = BufferBlob::create("getPsrInfo_stub", stub_size);
1.507 + if (stub_blob == NULL) {
1.508 + vm_exit_during_initialization("Unable to allocate getPsrInfo_stub");
1.509 + }
1.510 + CodeBuffer c(stub_blob->instructions_begin(),
1.511 + stub_blob->instructions_size());
1.512 + VM_Version_StubGenerator g(&c);
1.513 + getPsrInfo_stub = CAST_TO_FN_PTR(getPsrInfo_stub_t,
1.514 + g.generate_getPsrInfo());
1.515 +
1.516 + get_processor_features();
1.517 +}
