1.1 --- a/src/cpu/mips/vm/assembler_mips.cpp Mon Apr 10 15:46:40 2017 +0800 1.2 +++ b/src/cpu/mips/vm/assembler_mips.cpp Mon Apr 10 14:48:12 2017 -0400 1.3 @@ -555,6 +555,19 @@ 1.4 } 1.5 } 1.6 1.7 +int MacroAssembler::insts_for_general_jump(address target) { 1.8 + if (reachable_from_cache(target)) { 1.9 + //j(target); 1.10 + //nop(); 1.11 + return 2; 1.12 + } else { 1.13 + //set64(T9, (long)target); 1.14 + //jr(T9); 1.15 + //nop(); 1.16 + return insts_for_set64((jlong)target) + 2; 1.17 + } 1.18 +} 1.19 + 1.20 void MacroAssembler::patchable_jump(address target) { 1.21 if (reachable_from_cache(target)) { 1.22 nop(); 1.23 @@ -570,6 +583,10 @@ 1.24 } 1.25 } 1.26 1.27 +int MacroAssembler::insts_for_patchable_jump(address target) { 1.28 + return 6; 1.29 +} 1.30 + 1.31 void MacroAssembler::general_call(address target) { 1.32 if (reachable_from_cache(target)) { 1.33 jal(target); 1.34 @@ -581,6 +598,19 @@ 1.35 } 1.36 } 1.37 1.38 +int MacroAssembler::insts_for_general_call(address target) { 1.39 + if (reachable_from_cache(target)) { 1.40 + //jal(target); 1.41 + //nop(); 1.42 + return 2; 1.43 + } else { 1.44 + //set64(T9, (long)target); 1.45 + //jalr(T9); 1.46 + //nop(); 1.47 + return insts_for_set64((jlong)target) + 2; 1.48 + } 1.49 +} 1.50 + 1.51 void MacroAssembler::patchable_call(address target) { 1.52 if (reachable_from_cache(target)) { 1.53 nop(); 1.54 @@ -596,6 +626,10 @@ 1.55 } 1.56 } 1.57 1.58 +int MacroAssembler::insts_for_patchable_call(address target) { 1.59 + return 6; 1.60 +} 1.61 + 1.62 void MacroAssembler::beq_far(Register rs, Register rt, address entry) 1.63 { 1.64 u_char * cur_pc = pc();