1.1 --- a/src/cpu/x86/vm/interp_masm_x86_64.cpp Mon Jul 23 13:04:59 2012 -0700
1.2 +++ b/src/cpu/x86/vm/interp_masm_x86_64.cpp Tue Jul 24 10:51:00 2012 -0700
1.3 @@ -256,8 +256,12 @@
1.4 // little-endian machines allow us that.
1.5 movl(bytecode, Address(cache, index, Address::times_ptr, constantPoolCacheOopDesc::base_offset() + ConstantPoolCacheEntry::indices_offset()));
1.6 const int shift_count = (1 + byte_no) * BitsPerByte;
1.7 + assert((byte_no == TemplateTable::f1_byte && shift_count == ConstantPoolCacheEntry::bytecode_1_shift) ||
1.8 + (byte_no == TemplateTable::f2_byte && shift_count == ConstantPoolCacheEntry::bytecode_2_shift),
1.9 + "correct shift count");
1.10 shrl(bytecode, shift_count);
1.11 - andl(bytecode, 0xFF);
1.12 + assert(ConstantPoolCacheEntry::bytecode_1_mask == ConstantPoolCacheEntry::bytecode_2_mask, "common mask");
1.13 + andl(bytecode, ConstantPoolCacheEntry::bytecode_1_mask);
1.14 }
1.15
1.16
