1.1 --- a/src/cpu/x86/vm/x86_32.ad Tue Aug 16 11:53:57 2011 -0700
1.2 +++ b/src/cpu/x86/vm/x86_32.ad Tue Aug 16 16:59:46 2011 -0700
1.3 @@ -7325,8 +7325,9 @@
1.4 ins_cost(100);
1.5
1.6 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %}
1.7 - opcode(0x0F, 0x0d); /* Opcode 0F 0d /0 */
1.8 - ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem));
1.9 + ins_encode %{
1.10 + __ prefetchr($mem$$Address);
1.11 + %}
1.12 ins_pipe(ialu_mem);
1.13 %}
1.14
1.15 @@ -7336,8 +7337,9 @@
1.16 ins_cost(100);
1.17
1.18 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %}
1.19 - opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */
1.20 - ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem));
1.21 + ins_encode %{
1.22 + __ prefetchnta($mem$$Address);
1.23 + %}
1.24 ins_pipe(ialu_mem);
1.25 %}
1.26
1.27 @@ -7347,8 +7349,9 @@
1.28 ins_cost(100);
1.29
1.30 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %}
1.31 - opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */
1.32 - ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem));
1.33 + ins_encode %{
1.34 + __ prefetcht0($mem$$Address);
1.35 + %}
1.36 ins_pipe(ialu_mem);
1.37 %}
1.38
1.39 @@ -7358,8 +7361,9 @@
1.40 ins_cost(100);
1.41
1.42 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %}
1.43 - opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */
1.44 - ins_encode(OpcP, OpcS, RMopc_Mem(0x03,mem));
1.45 + ins_encode %{
1.46 + __ prefetcht2($mem$$Address);
1.47 + %}
1.48 ins_pipe(ialu_mem);
1.49 %}
1.50
1.51 @@ -7374,46 +7378,86 @@
1.52 %}
1.53
1.54 instruct prefetchw( memory mem ) %{
1.55 - predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch() || AllocatePrefetchInstr==3);
1.56 + predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch());
1.57 match( PrefetchWrite mem );
1.58 ins_cost(100);
1.59
1.60 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %}
1.61 - opcode(0x0F, 0x0D); /* Opcode 0F 0D /1 */
1.62 - ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem));
1.63 + ins_encode %{
1.64 + __ prefetchw($mem$$Address);
1.65 + %}
1.66 ins_pipe(ialu_mem);
1.67 %}
1.68
1.69 instruct prefetchwNTA( memory mem ) %{
1.70 - predicate(UseSSE>=1 && AllocatePrefetchInstr==0);
1.71 + predicate(UseSSE>=1);
1.72 match(PrefetchWrite mem);
1.73 ins_cost(100);
1.74
1.75 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %}
1.76 - opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */
1.77 - ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem));
1.78 + ins_encode %{
1.79 + __ prefetchnta($mem$$Address);
1.80 + %}
1.81 ins_pipe(ialu_mem);
1.82 %}
1.83
1.84 -instruct prefetchwT0( memory mem ) %{
1.85 +// Prefetch instructions for allocation.
1.86 +
1.87 +instruct prefetchAlloc0( memory mem ) %{
1.88 + predicate(UseSSE==0 && AllocatePrefetchInstr!=3);
1.89 + match(PrefetchAllocation mem);
1.90 + ins_cost(0);
1.91 + size(0);
1.92 + format %{ "Prefetch allocation (non-SSE is empty encoding)" %}
1.93 + ins_encode();
1.94 + ins_pipe(empty);
1.95 +%}
1.96 +
1.97 +instruct prefetchAlloc( memory mem ) %{
1.98 + predicate(AllocatePrefetchInstr==3);
1.99 + match( PrefetchAllocation mem );
1.100 + ins_cost(100);
1.101 +
1.102 + format %{ "PREFETCHW $mem\t! Prefetch allocation into L1 cache and mark modified" %}
1.103 + ins_encode %{
1.104 + __ prefetchw($mem$$Address);
1.105 + %}
1.106 + ins_pipe(ialu_mem);
1.107 +%}
1.108 +
1.109 +instruct prefetchAllocNTA( memory mem ) %{
1.110 + predicate(UseSSE>=1 && AllocatePrefetchInstr==0);
1.111 + match(PrefetchAllocation mem);
1.112 + ins_cost(100);
1.113 +
1.114 + format %{ "PREFETCHNTA $mem\t! Prefetch allocation into non-temporal cache for write" %}
1.115 + ins_encode %{
1.116 + __ prefetchnta($mem$$Address);
1.117 + %}
1.118 + ins_pipe(ialu_mem);
1.119 +%}
1.120 +
1.121 +instruct prefetchAllocT0( memory mem ) %{
1.122 predicate(UseSSE>=1 && AllocatePrefetchInstr==1);
1.123 - match(PrefetchWrite mem);
1.124 + match(PrefetchAllocation mem);
1.125 ins_cost(100);
1.126
1.127 - format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for write" %}
1.128 - opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */
1.129 - ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem));
1.130 + format %{ "PREFETCHT0 $mem\t! Prefetch allocation into L1 and L2 caches for write" %}
1.131 + ins_encode %{
1.132 + __ prefetcht0($mem$$Address);
1.133 + %}
1.134 ins_pipe(ialu_mem);
1.135 %}
1.136
1.137 -instruct prefetchwT2( memory mem ) %{
1.138 +instruct prefetchAllocT2( memory mem ) %{
1.139 predicate(UseSSE>=1 && AllocatePrefetchInstr==2);
1.140 - match(PrefetchWrite mem);
1.141 + match(PrefetchAllocation mem);
1.142 ins_cost(100);
1.143
1.144 - format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for write" %}
1.145 - opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */
1.146 - ins_encode(OpcP, OpcS, RMopc_Mem(0x03,mem));
1.147 + format %{ "PREFETCHT2 $mem\t! Prefetch allocation into L2 cache for write" %}
1.148 + ins_encode %{
1.149 + __ prefetcht2($mem$$Address);
1.150 + %}
1.151 ins_pipe(ialu_mem);
1.152 %}
1.153
