1.1 --- a/src/cpu/x86/vm/vm_version_x86.hpp Tue Sep 09 19:18:13 2014 +0000
1.2 +++ b/src/cpu/x86/vm/vm_version_x86.hpp Tue Sep 02 12:48:45 2014 -0700
1.3 @@ -209,7 +209,9 @@
1.4 erms : 1,
1.5 : 1,
1.6 rtm : 1,
1.7 - : 20;
1.8 + : 7,
1.9 + adx : 1,
1.10 + : 12;
1.11 } bits;
1.12 };
1.13
1.14 @@ -260,7 +262,8 @@
1.15 CPU_CLMUL = (1 << 21), // carryless multiply for CRC
1.16 CPU_BMI1 = (1 << 22),
1.17 CPU_BMI2 = (1 << 23),
1.18 - CPU_RTM = (1 << 24) // Restricted Transactional Memory instructions
1.19 + CPU_RTM = (1 << 24), // Restricted Transactional Memory instructions
1.20 + CPU_ADX = (1 << 25)
1.21 } cpuFeatureFlags;
1.22
1.23 enum {
1.24 @@ -465,10 +468,16 @@
1.25 }
1.26 // Intel features.
1.27 if(is_intel()) {
1.28 + if(_cpuid_info.sef_cpuid7_ebx.bits.adx != 0)
1.29 + result |= CPU_ADX;
1.30 if(_cpuid_info.sef_cpuid7_ebx.bits.bmi2 != 0)
1.31 result |= CPU_BMI2;
1.32 if(_cpuid_info.ext_cpuid1_ecx.bits.lzcnt_intel != 0)
1.33 result |= CPU_LZCNT;
1.34 + // for Intel, ecx.bits.misalignsse bit (bit 8) indicates support for prefetchw
1.35 + if (_cpuid_info.ext_cpuid1_ecx.bits.misalignsse != 0) {
1.36 + result |= CPU_3DNOW_PREFETCH;
1.37 + }
1.38 }
1.39
1.40 return result;
1.41 @@ -621,6 +630,7 @@
1.42 static bool supports_rtm() { return (_cpuFeatures & CPU_RTM) != 0; }
1.43 static bool supports_bmi1() { return (_cpuFeatures & CPU_BMI1) != 0; }
1.44 static bool supports_bmi2() { return (_cpuFeatures & CPU_BMI2) != 0; }
1.45 + static bool supports_adx() { return (_cpuFeatures & CPU_ADX) != 0; }
1.46 // Intel features
1.47 static bool is_intel_family_core() { return is_intel() &&
1.48 extended_cpu_family() == CPU_FAMILY_INTEL_CORE; }
