src/cpu/mips/vm/macroAssembler_mips.hpp

changeset 9705
0b27fc8adf1b
parent 9576
1cee9b02d46f
child 9932
86ea9a02a717
     1.1 --- a/src/cpu/mips/vm/macroAssembler_mips.hpp	Wed Sep 11 12:40:06 2019 +0800
     1.2 +++ b/src/cpu/mips/vm/macroAssembler_mips.hpp	Fri Sep 27 11:31:13 2019 +0800
     1.3 @@ -217,6 +217,9 @@
     1.4    void store_check(Register obj);                // store check for obj - register is destroyed afterwards
     1.5    void store_check(Register obj, Address dst);   // same as above, dst is exact store location (reg. is destroyed)
     1.6  
     1.7 + void resolve_jobject(Register value, Register thread, Register tmp);
     1.8 + void clear_jweak_tag(Register possibly_jweak);
     1.9 +
    1.10  #if INCLUDE_ALL_GCS
    1.11  
    1.12    void g1_write_barrier_pre(Register obj,

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