1.1 --- a/src/share/vm/c1/c1_LIR.hpp Thu Aug 06 00:08:57 2015 -0700
1.2 +++ b/src/share/vm/c1/c1_LIR.hpp Tue Oct 17 12:58:25 2017 +0800
1.3 @@ -22,6 +22,12 @@
1.4 *
1.5 */
1.6
1.7 +/*
1.8 + * This file has been modified by Loongson Technology in 2015. These
1.9 + * modifications are Copyright (c) 2015 Loongson Technology, and are made
1.10 + * available on the same license terms set forth above.
1.11 + */
1.12 +
1.13 #ifndef SHARE_VM_C1_C1_LIR_HPP
1.14 #define SHARE_VM_C1_C1_LIR_HPP
1.15
1.16 @@ -456,6 +462,14 @@
1.17 FloatRegister as_float_reg () const;
1.18 FloatRegister as_double_reg () const;
1.19 #endif
1.20 +#ifdef MIPS64
1.21 + FloatRegister as_float_reg () const;
1.22 + FloatRegister as_double_reg () const;
1.23 +
1.24 + FloatRegister as_fpu_lo () const;
1.25 + FloatRegister as_fpu_hi () const;
1.26 +
1.27 +#endif
1.28
1.29 jint as_jint() const { return as_constant_ptr()->as_jint(); }
1.30 jlong as_jlong() const { return as_constant_ptr()->as_jlong(); }
1.31 @@ -528,7 +542,11 @@
1.32 , _type(type)
1.33 , _disp(0) { verify(); }
1.34
1.35 +#ifndef MIPS64
1.36 LIR_Address(LIR_Opr base, intx disp, BasicType type):
1.37 +#else
1.38 + LIR_Address(LIR_Opr base, int disp, BasicType type):
1.39 +#endif
1.40 _base(base)
1.41 , _index(LIR_OprDesc::illegalOpr())
1.42 , _scale(times_1)
1.43 @@ -659,6 +677,13 @@
1.44 LIR_OprDesc::cpu_register |
1.45 LIR_OprDesc::double_size); }
1.46 #endif // PPC
1.47 +#ifdef MIPS64
1.48 + static LIR_Opr double_fpu(int reg) { return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
1.49 + (reg << LIR_OprDesc::reg2_shift) |
1.50 + LIR_OprDesc::double_type |
1.51 + LIR_OprDesc::fpu_register |
1.52 + LIR_OprDesc::double_size); }
1.53 +#endif
1.54
1.55 static LIR_Opr virtual_register(int index, BasicType type) {
1.56 LIR_Opr res;
1.57 @@ -924,8 +949,10 @@
1.58 , lir_return
1.59 , lir_leal
1.60 , lir_neg
1.61 +#ifndef MIPS64
1.62 , lir_branch
1.63 , lir_cond_float_branch
1.64 +#endif
1.65 , lir_move
1.66 , lir_prefetchr
1.67 , lir_prefetchw
1.68 @@ -939,7 +966,13 @@
1.69 , lir_unwind
1.70 , end_op1
1.71 , begin_op2
1.72 +#ifdef MIPS64
1.73 + , lir_branch
1.74 + , lir_cond_float_branch
1.75 + , lir_null_check_for_branch
1.76 +#else
1.77 , lir_cmp
1.78 +#endif
1.79 , lir_cmp_l2i
1.80 , lir_ucmp_fd2i
1.81 , lir_cmp_fd2i
1.82 @@ -973,6 +1006,9 @@
1.83 , lir_xchg
1.84 , end_op2
1.85 , begin_op3
1.86 +#ifdef MIPS64
1.87 + , lir_frem
1.88 +#endif
1.89 , lir_idiv
1.90 , lir_irem
1.91 , end_op3
1.92 @@ -1422,6 +1458,7 @@
1.93 };
1.94
1.95
1.96 +#ifndef MIPS64
1.97 class LIR_OpBranch: public LIR_Op {
1.98 friend class LIR_OpVisitState;
1.99
1.100 @@ -1464,6 +1501,7 @@
1.101 virtual LIR_OpBranch* as_OpBranch() { return this; }
1.102 virtual void print_instr(outputStream* out) const PRODUCT_RETURN;
1.103 };
1.104 +#endif
1.105
1.106
1.107 class ConversionStub;
1.108 @@ -1514,6 +1552,7 @@
1.109 };
1.110
1.111
1.112 +#ifndef MIPS64
1.113 // LIR_OpAllocObj
1.114 class LIR_OpAllocObj : public LIR_Op1 {
1.115 friend class LIR_OpVisitState;
1.116 @@ -1557,6 +1596,56 @@
1.117 virtual LIR_OpAllocObj * as_OpAllocObj () { return this; }
1.118 virtual void print_instr(outputStream* out) const PRODUCT_RETURN;
1.119 };
1.120 +#else
1.121 +class LIR_OpAllocObj : public LIR_Op1 {
1.122 + friend class LIR_OpVisitState;
1.123 +
1.124 + private:
1.125 + LIR_Opr _tmp1;
1.126 + LIR_Opr _tmp2;
1.127 + LIR_Opr _tmp3;
1.128 + LIR_Opr _tmp4;
1.129 + LIR_Opr _tmp5;
1.130 + LIR_Opr _tmp6;
1.131 + int _hdr_size;
1.132 + int _obj_size;
1.133 + CodeStub* _stub;
1.134 + bool _init_check;
1.135 +
1.136 + public:
1.137 + LIR_OpAllocObj(LIR_Opr klass, LIR_Opr result,
1.138 + LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4,LIR_Opr t5, LIR_Opr t6,
1.139 + int hdr_size, int obj_size, bool init_check, CodeStub* stub)
1.140 + : LIR_Op1(lir_alloc_object, klass, result)
1.141 + , _tmp1(t1)
1.142 + , _tmp2(t2)
1.143 + , _tmp3(t3)
1.144 + , _tmp4(t4)
1.145 + , _tmp5(t5)
1.146 + , _tmp6(t6)
1.147 + , _hdr_size(hdr_size)
1.148 + , _obj_size(obj_size)
1.149 + , _init_check(init_check)
1.150 + , _stub(stub) { }
1.151 +
1.152 + LIR_Opr klass() const { return in_opr(); }
1.153 + LIR_Opr obj() const { return result_opr(); }
1.154 + LIR_Opr tmp1() const { return _tmp1; }
1.155 + LIR_Opr tmp2() const { return _tmp2; }
1.156 + LIR_Opr tmp3() const { return _tmp3; }
1.157 + LIR_Opr tmp4() const { return _tmp4; }
1.158 + LIR_Opr tmp5() const { return _tmp5; }
1.159 + LIR_Opr tmp6() const { return _tmp6; }
1.160 + int header_size() const { return _hdr_size; }
1.161 + int object_size() const { return _obj_size; }
1.162 + bool init_check() const { return _init_check; }
1.163 + CodeStub* stub() const { return _stub; }
1.164 +
1.165 + virtual void emit_code(LIR_Assembler* masm);
1.166 + virtual LIR_OpAllocObj * as_OpAllocObj () { return this; }
1.167 + virtual void print_instr(outputStream* out) const PRODUCT_RETURN;
1.168 +};
1.169 +#endif
1.170
1.171
1.172 // LIR_OpRoundFP
1.173 @@ -1627,6 +1716,7 @@
1.174 void print_instr(outputStream* out) const PRODUCT_RETURN;
1.175 };
1.176
1.177 +#ifndef MIPS64
1.178 // LIR_Op2
1.179 class LIR_Op2: public LIR_Op {
1.180 friend class LIR_OpVisitState;
1.181 @@ -1735,7 +1825,138 @@
1.182 virtual LIR_Op2* as_Op2() { return this; }
1.183 virtual void print_instr(outputStream* out) const PRODUCT_RETURN;
1.184 };
1.185 -
1.186 +#else
1.187 + class LIR_Op2: public LIR_Op {
1.188 + //friend class LIR_Optimizer;
1.189 + friend class LIR_OpVisitState;
1.190 + protected:
1.191 + LIR_Opr _opr1;
1.192 + LIR_Opr _opr2;
1.193 + BasicType _type;
1.194 + LIR_Opr _tmp1;
1.195 + LIR_Opr _tmp2;
1.196 + LIR_Opr _tmp3;
1.197 + LIR_Opr _tmp4;
1.198 + LIR_Opr _tmp5;
1.199 +
1.200 + virtual void verify() const;
1.201 + public:
1.202 + LIR_Op2(LIR_Code code, LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2,
1.203 + CodeEmitInfo* info = NULL, BasicType type = T_ILLEGAL)
1.204 + : LIR_Op(code, LIR_OprFact::illegalOpr, info),
1.205 + _opr1(opr1), _opr2(opr2),
1.206 + _type(type),
1.207 + _tmp1(LIR_OprFact::illegalOpr),
1.208 + _tmp2(LIR_OprFact::illegalOpr),
1.209 + _tmp3(LIR_OprFact::illegalOpr),
1.210 + _tmp4(LIR_OprFact::illegalOpr),
1.211 + _tmp5(LIR_OprFact::illegalOpr) {
1.212 + }
1.213 +
1.214 + LIR_Op2(LIR_Code code, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result = LIR_OprFact::illegalOpr,
1.215 + CodeEmitInfo* info = NULL, BasicType type = T_ILLEGAL)
1.216 + : LIR_Op(code, result, info),
1.217 + _opr1(opr1), _opr2(opr2),
1.218 + _type(type),
1.219 + _tmp1(LIR_OprFact::illegalOpr),
1.220 + _tmp2(LIR_OprFact::illegalOpr),
1.221 + _tmp3(LIR_OprFact::illegalOpr),
1.222 + _tmp4(LIR_OprFact::illegalOpr),
1.223 + _tmp5(LIR_OprFact::illegalOpr) {
1.224 +
1.225 + assert(is_in_range(code, begin_op2, end_op2), "code check");
1.226 + }
1.227 +
1.228 +
1.229 + LIR_Op2(LIR_Code code, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, LIR_Opr tmp1, LIR_Opr tmp2 = LIR_OprFact::illegalOpr, LIR_Opr tmp3 = LIR_OprFact::illegalOpr, LIR_Opr tmp4 = LIR_OprFact::illegalOpr, LIR_Opr tmp5 = LIR_OprFact::illegalOpr)
1.230 + : LIR_Op(code, result, NULL),
1.231 + _opr1(opr1), _opr2(opr2),
1.232 + _type(T_ILLEGAL),
1.233 + _tmp1(tmp1),
1.234 + _tmp2(tmp2),
1.235 + _tmp3(tmp3),
1.236 + _tmp4(tmp4),
1.237 + _tmp5(tmp5) {
1.238 + assert(is_in_range(code, begin_op2, end_op2), "code check");
1.239 + }
1.240 +
1.241 + LIR_Opr in_opr1() const { return _opr1; }
1.242 + LIR_Opr in_opr2() const { return _opr2; }
1.243 + BasicType type() const { return _type; }
1.244 + LIR_Opr tmp1_opr() const { return _tmp1; }
1.245 + LIR_Opr tmp2_opr() const { return _tmp2; }
1.246 + LIR_Opr tmp3_opr() const { return _tmp3; }
1.247 + LIR_Opr tmp4_opr() const { return _tmp4; }
1.248 + LIR_Opr tmp5_opr() const { return _tmp5; }
1.249 +
1.250 +
1.251 + void set_in_opr1(LIR_Opr opr) { _opr1 = opr; }
1.252 + void set_in_opr2(LIR_Opr opr) { _opr2 = opr; }
1.253 + // where is the defination of LIR_AbstractAssembler?, 12/21,2006, jerome
1.254 + //virtual void emit_code(LIR_AbstractAssembler* masm);
1.255 + virtual void emit_code(LIR_Assembler* masm);
1.256 + virtual LIR_Op2* as_Op2() { return this; }
1.257 +
1.258 + // virtual void print_instr() const PRODUCT_RETURN;
1.259 + virtual void print_instr(outputStream* out) const PRODUCT_RETURN;
1.260 + };
1.261 +
1.262 +
1.263 + class LIR_OpBranch: public LIR_Op2 {
1.264 + friend class LIR_OpVisitState;
1.265 + public:
1.266 +
1.267 + private:
1.268 + LIR_Condition _cond;
1.269 + BasicType _type;
1.270 + Label* _label;
1.271 + BlockBegin* _block; // if this is a branch to a block, this is the block
1.272 + BlockBegin* _ublock; // if this is a float branch , this is the unorder block
1.273 + CodeStub* _stub; // if this is a branch to a stub, this is the stub
1.274 +
1.275 + public:
1.276 + // these are temporary constructors until we start using the conditional register
1.277 + LIR_OpBranch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, Label* lbl)
1.278 + : LIR_Op2(lir_branch, left, right, LIR_OprFact::illegalOpr, (CodeEmitInfo*)(NULL)),
1.279 + _cond(cond), _label(lbl), _block(NULL), _ublock(NULL),_stub(NULL)
1.280 + {
1.281 + }
1.282 +
1.283 + LIR_OpBranch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, BasicType type, BlockBegin* block);
1.284 +
1.285 + LIR_OpBranch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, BasicType type, CodeStub* stub);
1.286 +
1.287 + //LIR_OpBranch(LIR_Condition cond, BasicType type, CodeStub* stub);
1.288 +
1.289 + LIR_OpBranch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, BasicType type,
1.290 + BlockBegin *block,BlockBegin *ublock);
1.291 +
1.292 + LIR_Condition cond() const { return _cond; }
1.293 + BasicType type() const { return _type; }
1.294 + LIR_Opr left() const { return in_opr1(); }
1.295 + LIR_Opr right() const { return in_opr2(); }
1.296 + Label* label() const { return _label; }
1.297 + BlockBegin* block() const { return _block; }
1.298 + BlockBegin* ublock() const { return _ublock; }
1.299 + CodeStub* stub() const { return _stub; }
1.300 +
1.301 +
1.302 + void change_block(BlockBegin* b);
1.303 + void change_ublock(BlockBegin* b);
1.304 + void negate_cond();
1.305 +
1.306 +
1.307 + // 12/21,06,jerome
1.308 + //virtual void emit_code(LIR_AbstractAssembler* masm);
1.309 + virtual void emit_code(LIR_Assembler* masm);
1.310 + virtual LIR_OpBranch* as_OpBranch() { return this; }
1.311 + //virtual void print_instr() const PRODUCT_RETURN;
1.312 + virtual void print_instr(outputStream* out) const PRODUCT_RETURN;
1.313 +
1.314 + };
1.315 +#endif
1.316 +
1.317 +#ifndef MIPS64
1.318 class LIR_OpAllocArray : public LIR_Op {
1.319 friend class LIR_OpVisitState;
1.320
1.321 @@ -1775,6 +1996,50 @@
1.322 virtual LIR_OpAllocArray * as_OpAllocArray () { return this; }
1.323 virtual void print_instr(outputStream* out) const PRODUCT_RETURN;
1.324 };
1.325 +#else
1.326 +class LIR_OpAllocArray : public LIR_Op {
1.327 + friend class LIR_OpVisitState;
1.328 +
1.329 + private:
1.330 + LIR_Opr _klass;
1.331 + LIR_Opr _len;
1.332 + LIR_Opr _tmp1;
1.333 + LIR_Opr _tmp2;
1.334 + LIR_Opr _tmp3;
1.335 + LIR_Opr _tmp4;
1.336 + LIR_Opr _tmp5;
1.337 + BasicType _type;
1.338 + CodeStub* _stub;
1.339 +
1.340 + public:
1.341 + LIR_OpAllocArray(LIR_Opr klass, LIR_Opr len, LIR_Opr result, LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4, LIR_Opr t5, BasicType type, CodeStub* stub)
1.342 + : LIR_Op(lir_alloc_array, result, NULL)
1.343 + , _klass(klass)
1.344 + , _len(len)
1.345 + , _tmp1(t1)
1.346 + , _tmp2(t2)
1.347 + , _tmp3(t3)
1.348 + , _tmp4(t4)
1.349 + , _tmp5(t5)
1.350 + , _type(type)
1.351 + , _stub(stub) {}
1.352 +
1.353 + LIR_Opr klass() const { return _klass; }
1.354 + LIR_Opr len() const { return _len; }
1.355 + LIR_Opr obj() const { return result_opr(); }
1.356 + LIR_Opr tmp1() const { return _tmp1; }
1.357 + LIR_Opr tmp2() const { return _tmp2; }
1.358 + LIR_Opr tmp3() const { return _tmp3; }
1.359 + LIR_Opr tmp4() const { return _tmp4; }
1.360 + LIR_Opr tmp5() const { return _tmp5; }
1.361 + BasicType type() const { return _type; }
1.362 + CodeStub* stub() const { return _stub; }
1.363 +
1.364 + virtual void emit_code(LIR_Assembler* masm);
1.365 + virtual LIR_OpAllocArray * as_OpAllocArray () { return this; }
1.366 + virtual void print_instr(outputStream* out) const PRODUCT_RETURN;
1.367 +};
1.368 +#endif
1.369
1.370
1.371 class LIR_Op3: public LIR_Op {
1.372 @@ -2168,6 +2433,7 @@
1.373 void push(LIR_Opr opr) { append(new LIR_Op1(lir_push, opr)); }
1.374 void pop(LIR_Opr reg) { append(new LIR_Op1(lir_pop, reg)); }
1.375
1.376 +#ifndef MIPS64
1.377 void cmp(LIR_Condition condition, LIR_Opr left, LIR_Opr right, CodeEmitInfo* info = NULL) {
1.378 append(new LIR_Op2(lir_cmp, condition, left, right, info));
1.379 }
1.380 @@ -2182,12 +2448,46 @@
1.381 append(new LIR_Op2(lir_cmove, condition, src1, src2, dst, type));
1.382 }
1.383
1.384 +#else
1.385 + void null_check_for_branch(LIR_Condition condition, LIR_Opr left, LIR_Opr right,
1.386 + CodeEmitInfo* info = NULL) {
1.387 + append(new LIR_Op2(lir_null_check_for_branch, condition, left, right, info));
1.388 + }
1.389 +
1.390 + void null_check_for_branch(LIR_Condition condition, LIR_Opr left, int right,
1.391 + CodeEmitInfo* info = NULL) {
1.392 + append(new LIR_Op2(lir_null_check_for_branch, condition, left, LIR_OprFact::intConst(right), info));
1.393 + }
1.394 +
1.395 + void null_check_for_branch(LIR_Condition condition, LIR_Opr base, int disp, int c,
1.396 + CodeEmitInfo* info) {
1.397 + append(new LIR_Op2(lir_null_check_for_branch, condition,
1.398 + LIR_OprFact::address(new LIR_Address(base, disp, T_INT)),
1.399 + LIR_OprFact::intConst(c),
1.400 + info, T_INT));
1.401 + }
1.402 +
1.403 + void null_check_branch(LIR_Condition condition, LIR_Opr reg, LIR_Address* addr,
1.404 + CodeEmitInfo* info) {
1.405 + append(new LIR_Op2(lir_null_check_for_branch, condition,
1.406 + reg,
1.407 + LIR_OprFact::address(addr),
1.408 + info));
1.409 + }
1.410 +
1.411 +#endif
1.412 +#ifndef MIPS64
1.413 void cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1.414 LIR_Opr t1, LIR_Opr t2, LIR_Opr result = LIR_OprFact::illegalOpr);
1.415 void cas_obj(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1.416 LIR_Opr t1, LIR_Opr t2, LIR_Opr result = LIR_OprFact::illegalOpr);
1.417 void cas_int(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1.418 LIR_Opr t1, LIR_Opr t2, LIR_Opr result = LIR_OprFact::illegalOpr);
1.419 +#else
1.420 + void cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, LIR_Opr t1, LIR_Opr t2, LIR_Opr result);
1.421 + void cas_obj(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, LIR_Opr t1, LIR_Opr t2, LIR_Opr result);
1.422 + void cas_int(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, LIR_Opr t1, LIR_Opr t2, LIR_Opr result);
1.423 +#endif
1.424
1.425 void abs (LIR_Opr from, LIR_Opr to, LIR_Opr tmp) { append(new LIR_Op2(lir_abs , from, tmp, to)); }
1.426 void sqrt(LIR_Opr from, LIR_Opr to, LIR_Opr tmp) { append(new LIR_Op2(lir_sqrt, from, tmp, to)); }
1.427 @@ -2220,21 +2520,39 @@
1.428 void volatile_store_mem_reg(LIR_Opr src, LIR_Address* address, CodeEmitInfo* info, LIR_PatchCode patch_code = lir_patch_none);
1.429 void volatile_store_unsafe_reg(LIR_Opr src, LIR_Opr base, LIR_Opr offset, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code);
1.430
1.431 +#ifdef MIPS64
1.432 + void frem(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info = NULL);
1.433 +#endif
1.434 +
1.435 void idiv(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info);
1.436 void idiv(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info);
1.437 void irem(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info);
1.438 void irem(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info);
1.439
1.440 +#ifndef MIPS64
1.441 void allocate_object(LIR_Opr dst, LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4, int header_size, int object_size, LIR_Opr klass, bool init_check, CodeStub* stub);
1.442 void allocate_array(LIR_Opr dst, LIR_Opr len, LIR_Opr t1,LIR_Opr t2, LIR_Opr t3,LIR_Opr t4, BasicType type, LIR_Opr klass, CodeStub* stub);
1.443 +#else
1.444 + void allocate_object(LIR_Opr dst, LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4, LIR_Opr t5, LIR_Opr t6,int header_size, int object_size, LIR_Opr klass, bool init_check, CodeStub* stub);
1.445 + void allocate_array(LIR_Opr dst, LIR_Opr len, LIR_Opr t1,LIR_Opr t2, LIR_Opr t3,LIR_Opr t4, LIR_Opr t5,BasicType type, LIR_Opr klass, CodeStub* stub);
1.446 +#endif
1.447
1.448 // jump is an unconditional branch
1.449 void jump(BlockBegin* block) {
1.450 +#ifndef MIPS64
1.451 append(new LIR_OpBranch(lir_cond_always, T_ILLEGAL, block));
1.452 +#else
1.453 + append(new LIR_OpBranch(lir_cond_always, LIR_OprFact::illegalOpr,LIR_OprFact::illegalOpr,T_ILLEGAL, block));
1.454 +#endif
1.455 }
1.456 void jump(CodeStub* stub) {
1.457 +#ifndef MIPS64
1.458 append(new LIR_OpBranch(lir_cond_always, T_ILLEGAL, stub));
1.459 +#else
1.460 + append(new LIR_OpBranch(lir_cond_always, LIR_OprFact::illegalOpr, LIR_OprFact::illegalOpr,T_ILLEGAL, stub));
1.461 +#endif
1.462 }
1.463 +#ifndef MIPS64
1.464 void branch(LIR_Condition cond, BasicType type, Label* lbl) { append(new LIR_OpBranch(cond, type, lbl)); }
1.465 void branch(LIR_Condition cond, BasicType type, BlockBegin* block) {
1.466 assert(type != T_FLOAT && type != T_DOUBLE, "no fp comparisons");
1.467 @@ -2248,6 +2566,25 @@
1.468 assert(type == T_FLOAT || type == T_DOUBLE, "fp comparisons only");
1.469 append(new LIR_OpBranch(cond, type, block, unordered));
1.470 }
1.471 +#else
1.472 + void branch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, Label* lbl) {
1.473 + append(new LIR_OpBranch(cond, left, right, lbl));
1.474 + }
1.475 +
1.476 + void branch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, BasicType type, BlockBegin* block) {
1.477 + append(new LIR_OpBranch(cond, left, right, type, block));
1.478 + }
1.479 +
1.480 + void branch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, BasicType type, CodeStub* stub) {
1.481 + append(new LIR_OpBranch(cond, left, right, type, stub));
1.482 + }
1.483 +
1.484 + void branch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, BasicType type,
1.485 + BlockBegin* block, BlockBegin* unordered) {
1.486 + append(new LIR_OpBranch(cond, left, right, type, block, unordered));
1.487 + }
1.488 +
1.489 +#endif
1.490
1.491 void shift_left(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp);
1.492 void shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp);
