1.1 --- a/src/cpu/sparc/vm/sparc.ad Thu Nov 07 11:47:11 2013 +0100
1.2 +++ b/src/cpu/sparc/vm/sparc.ad Thu Nov 14 19:24:59 2013 -0800
1.3 @@ -1034,6 +1034,11 @@
1.4 }
1.5 }
1.6
1.7 +bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
1.8 +void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1.9 + ShouldNotReachHere();
1.10 +}
1.11 +
1.12 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1.13 Compile* C = ra_->C;
1.14 Compile::ConstantTable& constant_table = C->constant_table();
1.15 @@ -1884,6 +1889,9 @@
1.16 return (VM_Version::is_T4() || VM_Version::is_sparc64()) ? ConditionalMoveLimit : 0;
1.17 }
1.18
1.19 +// Does the CPU require late expand (see block.cpp for description of late expand)?
1.20 +const bool Matcher::require_postalloc_expand = false;
1.21 +
1.22 // Should the Matcher clone shifts on addressing modes, expecting them to
1.23 // be subsumed into complex addressing expressions or compute them into
1.24 // registers? True for Intel but false for most RISCs
