1.1 --- a/src/cpu/x86/vm/vm_version_x86.hpp Sun Dec 23 17:08:22 2012 +0100
1.2 +++ b/src/cpu/x86/vm/vm_version_x86.hpp Thu Jan 03 15:09:55 2013 -0800
1.3 @@ -204,7 +204,8 @@
1.4 avx2 : 1,
1.5 : 2,
1.6 bmi2 : 1,
1.7 - : 23;
1.8 + erms : 1,
1.9 + : 22;
1.10 } bits;
1.11 };
1.12
1.13 @@ -247,7 +248,8 @@
1.14 CPU_TSCINV = (1 << 16),
1.15 CPU_AVX = (1 << 17),
1.16 CPU_AVX2 = (1 << 18),
1.17 - CPU_AES = (1 << 19)
1.18 + CPU_AES = (1 << 19),
1.19 + CPU_ERMS = (1 << 20) // enhanced 'rep movsb/stosb' instructions
1.20 } cpuFeatureFlags;
1.21
1.22 enum {
1.23 @@ -425,6 +427,8 @@
1.24 result |= CPU_TSCINV;
1.25 if (_cpuid_info.std_cpuid1_ecx.bits.aes != 0)
1.26 result |= CPU_AES;
1.27 + if (_cpuid_info.sef_cpuid7_ebx.bits.erms != 0)
1.28 + result |= CPU_ERMS;
1.29
1.30 // AMD features.
1.31 if (is_amd()) {
1.32 @@ -489,7 +493,7 @@
1.33 return (_cpuid_info.std_max_function >= 0xB) &&
1.34 // eax[4:0] | ebx[0:15] == 0 indicates invalid topology level.
1.35 // Some cpus have max cpuid >= 0xB but do not support processor topology.
1.36 - ((_cpuid_info.tpl_cpuidB0_eax & 0x1f | _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus) != 0);
1.37 + (((_cpuid_info.tpl_cpuidB0_eax & 0x1f) | _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus) != 0);
1.38 }
1.39
1.40 static uint cores_per_cpu() {
1.41 @@ -550,6 +554,7 @@
1.42 static bool supports_avx2() { return (_cpuFeatures & CPU_AVX2) != 0; }
1.43 static bool supports_tsc() { return (_cpuFeatures & CPU_TSC) != 0; }
1.44 static bool supports_aes() { return (_cpuFeatures & CPU_AES) != 0; }
1.45 + static bool supports_erms() { return (_cpuFeatures & CPU_ERMS) != 0; }
1.46
1.47 // Intel features
1.48 static bool is_intel_family_core() { return is_intel() &&
