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comparison: src/cpu/mips/vm/mips_64.ad

src/cpu/mips/vm/mips_64.ad

changeset 8862
fd13a567f179
parent 8861
2a33b32dd03c
child 8863
5376ce0dc552
equal deleted inserted replaced
8861:2a33b32dd03c 8862:fd13a567f179
652 } 652 }
653 653
654 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) { 654 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
655 int offs = offset - br_size + 4; 655 int offs = offset - br_size + 4;
656 // To be conservative on MIPS 656 // To be conservative on MIPS
657 return Assembler::is_simm16((offs + 4) >> 2) && Assembler::is_simm16((offs - 4) >> 2); 657 const int safety_zone = 3 * BytesPerInstWord;
658 return Assembler::is_simm16((offs<0 ? offs-safety_zone : offs+safety_zone) >> 2);
658 } 659 }
659 660
660 661
661 // No additional cost for CMOVL. 662 // No additional cost for CMOVL.
662 const int Matcher::long_cmove_cost() { return 0; } 663 const int Matcher::long_cmove_cost() { return 0; }
1560 1561
1561 if (consts_section->size()) { 1562 if (consts_section->size()) {
1562 // Materialize the constant table base. 1563 // Materialize the constant table base.
1563 address baseaddr = consts_section->start() + -(constant_table.table_base_offset()); 1564 address baseaddr = consts_section->start() + -(constant_table.table_base_offset());
1564 // RelocationHolder rspec = internal_word_Relocation::spec(baseaddr); 1565 // RelocationHolder rspec = internal_word_Relocation::spec(baseaddr);
1565 __ relocate(relocInfo::internal_pc_type); 1566 __ relocate(relocInfo::internal_word_type);
1566 __ patchable_set48(Rtoc, (long)baseaddr); 1567 __ patchable_set48(Rtoc, (long)baseaddr);
1567 } 1568 }
1568 } 1569 }
1569 1570
1570 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const { 1571 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
6696 6697
6697 ins_cost(300); 6698 ins_cost(300);
6698 format %{ "JMP $labl #@jmpDir_long" %} 6699 format %{ "JMP $labl #@jmpDir_long" %}
6699 6700
6700 ins_encode %{ 6701 ins_encode %{
6701 Label &L = *($labl$$label); 6702 Label* L = $labl$$label;
6702 if(&L) 6703 __ jmp_far(*L);
6703 __ b(L); 6704 %}
6704 else 6705
6705 __ b(int(0)); 6706 ins_pipe( pipe_jump );
6706 __ nop(); 6707 //ins_pc_relative(1);
6707 __ nop();
6708 %}
6709
6710 ins_pipe( pipe_jump );
6711 ins_pc_relative(1);
6712 %} 6708 %}
6713 6709
6714 // Jump Direct Conditional - Label defines a relative address from Jcc+1 6710 // Jump Direct Conditional - Label defines a relative address from Jcc+1
6715 instruct jmpLoopEnd_long(cmpOp cop, mRegI src1, mRegI src2, label labl) %{ 6711 instruct jmpLoopEnd_long(cmpOp cop, mRegI src1, mRegI src2, label labl) %{
6716 match(CountedLoopEnd cop (CmpI src1 src2)); 6712 match(CountedLoopEnd cop (CmpI src1 src2));
6719 ins_cost(300); 6715 ins_cost(300);
6720 format %{ "J$cop $src1, $src2, $labl\t# Loop end @ jmpLoopEnd_long" %} 6716 format %{ "J$cop $src1, $src2, $labl\t# Loop end @ jmpLoopEnd_long" %}
6721 ins_encode %{ 6717 ins_encode %{
6722 Register op1 = $src1$$Register; 6718 Register op1 = $src1$$Register;
6723 Register op2 = $src2$$Register; 6719 Register op2 = $src2$$Register;
6724 Label &L = *($labl$$label); 6720 Label* L = $labl$$label;
6725 int flag = $cop$$cmpcode; 6721 int flag = $cop$$cmpcode;
6726 6722
6727 switch(flag) { 6723 switch(flag) {
6728 case 0x01: //equal 6724 case 0x01: //equal
6729 if (&L) 6725 __ beq_long(op1, op2, *L);
6730 __ beq(op1, op2, L);
6731 else
6732 __ beq(op1, op2, (int)0);
6733 break; 6726 break;
6734 case 0x02: //not_equal 6727 case 0x02: //not_equal
6735 if (&L) 6728 __ bne_long(op1, op2, *L);
6736 __ bne(op1, op2, L);
6737 else
6738 __ bne(op1, op2, (int)0);
6739 break; 6729 break;
6740 case 0x03: //above 6730 case 0x03: //above
6741 __ slt(AT, op2, op1); 6731 __ slt(AT, op2, op1);
6742 if(&L) 6732 __ bne_long(AT, R0, *L);
6743 __ bne(AT, R0, L);
6744 else
6745 __ bne(AT, R0, (int)0);
6746 break; 6733 break;
6747 case 0x04: //above_equal 6734 case 0x04: //above_equal
6748 __ slt(AT, op1, op2); 6735 __ slt(AT, op1, op2);
6749 if(&L) 6736 __ beq_long(AT, R0, *L);
6750 __ beq(AT, R0, L);
6751 else
6752 __ beq(AT, R0, (int)0);
6753 break; 6737 break;
6754 case 0x05: //below 6738 case 0x05: //below
6755 __ slt(AT, op1, op2); 6739 __ slt(AT, op1, op2);
6756 if(&L) 6740 __ bne_long(AT, R0, *L);
6757 __ bne(AT, R0, L);
6758 else
6759 __ bne(AT, R0, (int)0);
6760 break; 6741 break;
6761 case 0x06: //below_equal 6742 case 0x06: //below_equal
6762 __ slt(AT, op2, op1); 6743 __ slt(AT, op2, op1);
6763 if(&L) 6744 __ beq_long(AT, R0, *L);
6764 __ beq(AT, R0, L);
6765 else
6766 __ beq(AT, R0, (int)0);
6767 break; 6745 break;
6768 default: 6746 default:
6769 Unimplemented(); 6747 Unimplemented();
6770 } 6748 }
6771 __ nop();
6772 __ nop();
6773 %} 6749 %}
6774 ins_pipe( pipe_jump ); 6750 ins_pipe( pipe_jump );
6775 ins_pc_relative(1); 6751 ins_pc_relative(1);
6776 %} 6752 %}
6777 6753
6782 ins_cost(300); 6758 ins_cost(300);
6783 format %{ "J$cop $src1, $src2, $labl\t# Loop end @ jmpLoopEnd_reg_immI_long" %} 6759 format %{ "J$cop $src1, $src2, $labl\t# Loop end @ jmpLoopEnd_reg_immI_long" %}
6784 ins_encode %{ 6760 ins_encode %{
6785 Register op1 = $src1$$Register; 6761 Register op1 = $src1$$Register;
6786 Register op2 = AT; 6762 Register op2 = AT;
6787 Label &L = *($labl$$label); 6763 Label* L = $labl$$label;
6788 int flag = $cop$$cmpcode; 6764 int flag = $cop$$cmpcode;
6789 6765
6790 __ move(op2, $src2$$constant); 6766 __ move(op2, $src2$$constant);
6791 6767
6792 switch(flag) { 6768 switch(flag) {
6793 case 0x01: //equal 6769 case 0x01: //equal
6794 if (&L) 6770 __ beq_long(op1, op2, *L);
6795 __ beq(op1, op2, L);
6796 else
6797 __ beq(op1, op2, (int)0);
6798 break; 6771 break;
6799 case 0x02: //not_equal 6772 case 0x02: //not_equal
6800 if (&L) 6773 __ bne_long(op1, op2, *L);
6801 __ bne(op1, op2, L);
6802 else
6803 __ bne(op1, op2, (int)0);
6804 break; 6774 break;
6805 case 0x03: //above 6775 case 0x03: //above
6806 __ slt(AT, op2, op1); 6776 __ slt(AT, op2, op1);
6807 if(&L) 6777 __ bne_long(AT, R0, *L);
6808 __ bne(AT, R0, L);
6809 else
6810 __ bne(AT, R0, (int)0);
6811 break; 6778 break;
6812 case 0x04: //above_equal 6779 case 0x04: //above_equal
6813 __ slt(AT, op1, op2); 6780 __ slt(AT, op1, op2);
6814 if(&L) 6781 __ beq_long(AT, R0, *L);
6815 __ beq(AT, R0, L);
6816 else
6817 __ beq(AT, R0, (int)0);
6818 break; 6782 break;
6819 case 0x05: //below 6783 case 0x05: //below
6820 __ slt(AT, op1, op2); 6784 __ slt(AT, op1, op2);
6821 if(&L) 6785 __ bne_long(AT, R0, *L);
6822 __ bne(AT, R0, L);
6823 else
6824 __ bne(AT, R0, (int)0);
6825 break; 6786 break;
6826 case 0x06: //below_equal 6787 case 0x06: //below_equal
6827 __ slt(AT, op2, op1); 6788 __ slt(AT, op2, op1);
6828 if(&L) 6789 __ beq_long(AT, R0, *L);
6829 __ beq(AT, R0, L);
6830 else
6831 __ beq(AT, R0, (int)0);
6832 break; 6790 break;
6833 default: 6791 default:
6834 Unimplemented(); 6792 Unimplemented();
6835 } 6793 }
6836 __ nop();
6837 __ nop();
6838 %} 6794 %}
6839 ins_pipe( pipe_jump ); 6795 ins_pipe( pipe_jump );
6840 ins_pc_relative(1); 6796 ins_pc_relative(1);
6841 %} 6797 %}
6842 6798
6848 6804
6849 ins_cost(300); 6805 ins_cost(300);
6850 format %{ "J$cop $labl #mips uses AT as eflag @jmpCon_flags_long" %} 6806 format %{ "J$cop $labl #mips uses AT as eflag @jmpCon_flags_long" %}
6851 6807
6852 ins_encode %{ 6808 ins_encode %{
6853 Label &L = *($labl$$label); 6809 Label* L = $labl$$label;
6854 switch($cop$$cmpcode) { 6810 switch($cop$$cmpcode) {
6855 case 0x01: //equal 6811 case 0x01: //equal
6856 if (&L) 6812 __ bne_long(AT, R0, *L);
6857 __ bne(AT, R0, L);
6858 else
6859 __ bne(AT, R0, (int)0);
6860 break; 6813 break;
6861 case 0x02: //not equal 6814 case 0x02: //not equal
6862 if (&L) 6815 __ beq_long(AT, R0, *L);
6863 __ beq(AT, R0, L);
6864 else
6865 __ beq(AT, R0, (int)0);
6866 break; 6816 break;
6867 default: 6817 default:
6868 Unimplemented(); 6818 Unimplemented();
6869 } 6819 }
6870 __ nop();
6871 __ nop();
6872 %} 6820 %}
6873 6821
6874 ins_pipe( pipe_jump ); 6822 ins_pipe( pipe_jump );
6875 ins_pc_relative(1); 6823 ins_pc_relative(1);
6876 %} 6824 %}
6884 format %{ "b$cmp $op1, R0, $labl #@branchConP_zero_long" %} 6832 format %{ "b$cmp $op1, R0, $labl #@branchConP_zero_long" %}
6885 6833
6886 ins_encode %{ 6834 ins_encode %{
6887 Register op1 = $op1$$Register; 6835 Register op1 = $op1$$Register;
6888 Register op2 = R0; 6836 Register op2 = R0;
6889 Label &L = *($labl$$label); 6837 Label* L = $labl$$label;
6890 int flag = $cmp$$cmpcode; 6838 int flag = $cmp$$cmpcode;
6891 6839
6892 switch(flag) { 6840 switch(flag) {
6893 case 0x01: //equal 6841 case 0x01: //equal
6894 if (&L) 6842 __ beq_long(op1, op2, *L);
6895 __ beq(op1, op2, L);
6896 else
6897 __ beq(op1, op2, (int)0);
6898 break; 6843 break;
6899 case 0x02: //not_equal 6844 case 0x02: //not_equal
6900 if (&L) 6845 __ bne_long(op1, op2, *L);
6901 __ bne(op1, op2, L);
6902 else
6903 __ bne(op1, op2, (int)0);
6904 break; 6846 break;
6905 default: 6847 default:
6906 Unimplemented(); 6848 Unimplemented();
6907 } 6849 }
6908 __ nop();
6909 __ nop();
6910 %} 6850 %}
6911 6851
6912 ins_pc_relative(1); 6852 ins_pc_relative(1);
6913 ins_pipe( pipe_alu_branch ); 6853 ins_pipe( pipe_alu_branch );
6914 %} 6854 %}
6922 format %{ "b$cmp $op1, R0, $labl #@branchConN2P_zero_long" %} 6862 format %{ "b$cmp $op1, R0, $labl #@branchConN2P_zero_long" %}
6923 6863
6924 ins_encode %{ 6864 ins_encode %{
6925 Register op1 = $op1$$Register; 6865 Register op1 = $op1$$Register;
6926 Register op2 = R0; 6866 Register op2 = R0;
6927 Label &L = *($labl$$label); 6867 Label* L = $labl$$label;
6928 int flag = $cmp$$cmpcode; 6868 int flag = $cmp$$cmpcode;
6929 6869
6930 switch(flag) 6870 switch(flag)
6931 { 6871 {
6932 case 0x01: //equal 6872 case 0x01: //equal
6933 if (&L) 6873 __ beq_long(op1, op2, *L);
6934 __ beq(op1, op2, L);
6935 else
6936 __ beq(op1, op2, (int)0);
6937 break; 6874 break;
6938 case 0x02: //not_equal 6875 case 0x02: //not_equal
6939 if (&L) 6876 __ bne_long(op1, op2, *L);
6940 __ bne(op1, op2, L);
6941 else
6942 __ bne(op1, op2, (int)0);
6943 break; 6877 break;
6944 default: 6878 default:
6945 Unimplemented(); 6879 Unimplemented();
6946 } 6880 }
6947 __ nop();
6948 __ nop();
6949 %} 6881 %}
6950 6882
6951 ins_pc_relative(1); 6883 ins_pc_relative(1);
6952 ins_pipe( pipe_alu_branch ); 6884 ins_pipe( pipe_alu_branch );
6953 %} 6885 %}
6962 format %{ "b$cmp $op1, $op2, $labl #@branchConP_long" %} 6894 format %{ "b$cmp $op1, $op2, $labl #@branchConP_long" %}
6963 6895
6964 ins_encode %{ 6896 ins_encode %{
6965 Register op1 = $op1$$Register; 6897 Register op1 = $op1$$Register;
6966 Register op2 = $op2$$Register; 6898 Register op2 = $op2$$Register;
6967 Label &L = *($labl$$label); 6899 Label* L = $labl$$label;
6968 int flag = $cmp$$cmpcode; 6900 int flag = $cmp$$cmpcode;
6969 6901
6970 switch(flag) { 6902 switch(flag) {
6971 case 0x01: //equal 6903 case 0x01: //equal
6972 if (&L) 6904 __ beq_long(op1, op2, *L);
6973 __ beq(op1, op2, L);
6974 else
6975 __ beq(op1, op2, (int)0);
6976 break; 6905 break;
6977 case 0x02: //not_equal 6906 case 0x02: //not_equal
6978 if (&L) 6907 __ bne_long(op1, op2, *L);
6979 __ bne(op1, op2, L);
6980 else
6981 __ bne(op1, op2, (int)0);
6982 break; 6908 break;
6983 case 0x03: //above 6909 case 0x03: //above
6984 __ sltu(AT, op2, op1); 6910 __ sltu(AT, op2, op1);
6985 if(&L) 6911 __ bne_long(R0, AT, *L);
6986 __ bne(R0, AT, L);
6987 else
6988 __ bne(R0, AT, (int)0);
6989 break; 6912 break;
6990 case 0x04: //above_equal 6913 case 0x04: //above_equal
6991 __ sltu(AT, op1, op2); 6914 __ sltu(AT, op1, op2);
6992 if(&L) 6915 __ beq_long(AT, R0, *L);
6993 __ beq(AT, R0, L);
6994 else
6995 __ beq(AT, R0, (int)0);
6996 break; 6916 break;
6997 case 0x05: //below 6917 case 0x05: //below
6998 __ sltu(AT, op1, op2); 6918 __ sltu(AT, op1, op2);
6999 if(&L) 6919 __ bne_long(R0, AT, *L);
7000 __ bne(R0, AT, L);
7001 else
7002 __ bne(R0, AT, (int)0);
7003 break; 6920 break;
7004 case 0x06: //below_equal 6921 case 0x06: //below_equal
7005 __ sltu(AT, op2, op1); 6922 __ sltu(AT, op2, op1);
7006 if(&L) 6923 __ beq_long(AT, R0, *L);
7007 __ beq(AT, R0, L);
7008 else
7009 __ beq(AT, R0, (int)0);
7010 break; 6924 break;
7011 default: 6925 default:
7012 Unimplemented(); 6926 Unimplemented();
7013 } 6927 }
7014 __ nop();
7015 __ nop();
7016 %} 6928 %}
7017 6929
7018 ins_pc_relative(1); 6930 ins_pc_relative(1);
7019 ins_pipe( pipe_alu_branch ); 6931 ins_pipe( pipe_alu_branch );
7020 %} 6932 %}
7027 format %{ "CMP $op1,0\t! compressed ptr\n\t" 6939 format %{ "CMP $op1,0\t! compressed ptr\n\t"
7028 "BP$cmp $labl @ cmpN_null_branch_long" %} 6940 "BP$cmp $labl @ cmpN_null_branch_long" %}
7029 ins_encode %{ 6941 ins_encode %{
7030 Register op1 = $op1$$Register; 6942 Register op1 = $op1$$Register;
7031 Register op2 = R0; 6943 Register op2 = R0;
7032 Label &L = *($labl$$label); 6944 Label* L = $labl$$label;
7033 int flag = $cmp$$cmpcode; 6945 int flag = $cmp$$cmpcode;
7034 6946
7035 switch(flag) { 6947 switch(flag) {
7036 case 0x01: //equal 6948 case 0x01: //equal
7037 if (&L) 6949 __ beq_long(op1, op2, *L);
7038 __ beq(op1, op2, L);
7039 else
7040 __ beq(op1, op2, (int)0);
7041 break; 6950 break;
7042 case 0x02: //not_equal 6951 case 0x02: //not_equal
7043 if (&L) 6952 __ bne_long(op1, op2, *L);
7044 __ bne(op1, op2, L);
7045 else
7046 __ bne(op1, op2, (int)0);
7047 break; 6953 break;
7048 default: 6954 default:
7049 Unimplemented(); 6955 Unimplemented();
7050 } 6956 }
7051 __ nop();
7052 __ nop();
7053 %} 6957 %}
7054 //TODO: pipe_branchP or create pipe_branchN LEE 6958 //TODO: pipe_branchP or create pipe_branchN LEE
7055 ins_pc_relative(1); 6959 ins_pc_relative(1);
7056 ins_pipe( pipe_alu_branch ); 6960 ins_pipe( pipe_alu_branch );
7057 %} 6961 %}
7064 format %{ "CMP $op1,$op2\t! compressed ptr\n\t" 6968 format %{ "CMP $op1,$op2\t! compressed ptr\n\t"
7065 "BP$cmp $labl @ cmpN_reg_branch_long" %} 6969 "BP$cmp $labl @ cmpN_reg_branch_long" %}
7066 ins_encode %{ 6970 ins_encode %{
7067 Register op1_reg = $op1$$Register; 6971 Register op1_reg = $op1$$Register;
7068 Register op2_reg = $op2$$Register; 6972 Register op2_reg = $op2$$Register;
7069 Label &L = *($labl$$label); 6973 Label* L = $labl$$label;
7070 int flag = $cmp$$cmpcode; 6974 int flag = $cmp$$cmpcode;
7071 6975
7072 switch(flag) { 6976 switch(flag) {
7073 case 0x01: //equal 6977 case 0x01: //equal
7074 if (&L) 6978 __ beq_long(op1_reg, op2_reg, *L);
7075 __ beq(op1_reg, op2_reg, L);
7076 else
7077 __ beq(op1_reg, op2_reg, (int)0);
7078 break; 6979 break;
7079 case 0x02: //not_equal 6980 case 0x02: //not_equal
7080 if (&L) 6981 __ bne_long(op1_reg, op2_reg, *L);
7081 __ bne(op1_reg, op2_reg, L);
7082 else
7083 __ bne(op1_reg, op2_reg, (int)0);
7084 break; 6982 break;
7085 case 0x03: //above 6983 case 0x03: //above
7086 __ sltu(AT, op2_reg, op1_reg); 6984 __ sltu(AT, op2_reg, op1_reg);
7087 if(&L) 6985 __ bne_long(R0, AT, *L);
7088 __ bne(R0, AT, L);
7089 else
7090 __ bne(R0, AT, (int)0);
7091 break; 6986 break;
7092 case 0x04: //above_equal 6987 case 0x04: //above_equal
7093 __ sltu(AT, op1_reg, op2_reg); 6988 __ sltu(AT, op1_reg, op2_reg);
7094 if(&L) 6989 __ beq_long(AT, R0, *L);
7095 __ beq(AT, R0, L);
7096 else
7097 __ beq(AT, R0, (int)0);
7098 break; 6990 break;
7099 case 0x05: //below 6991 case 0x05: //below
7100 __ sltu(AT, op1_reg, op2_reg); 6992 __ sltu(AT, op1_reg, op2_reg);
7101 if(&L) 6993 __ bne_long(R0, AT, *L);
7102 __ bne(R0, AT, L);
7103 else
7104 __ bne(R0, AT, (int)0);
7105 break; 6994 break;
7106 case 0x06: //below_equal 6995 case 0x06: //below_equal
7107 __ sltu(AT, op2_reg, op1_reg); 6996 __ sltu(AT, op2_reg, op1_reg);
7108 if(&L) 6997 __ beq_long(AT, R0, *L);
7109 __ beq(AT, R0, L);
7110 else
7111 __ beq(AT, R0, (int)0);
7112 break; 6998 break;
7113 default: 6999 default:
7114 Unimplemented(); 7000 Unimplemented();
7115 } 7001 }
7116 __ nop();
7117 __ nop();
7118 %} 7002 %}
7119 ins_pc_relative(1); 7003 ins_pc_relative(1);
7120 ins_pipe( pipe_alu_branch ); 7004 ins_pipe( pipe_alu_branch );
7121 %} 7005 %}
7122 7006
7126 format %{ "BR$cmp $src1, $src2, $labl #@branchConIU_reg_reg_long" %} 7010 format %{ "BR$cmp $src1, $src2, $labl #@branchConIU_reg_reg_long" %}
7127 7011
7128 ins_encode %{ 7012 ins_encode %{
7129 Register op1 = $src1$$Register; 7013 Register op1 = $src1$$Register;
7130 Register op2 = $src2$$Register; 7014 Register op2 = $src2$$Register;
7131 Label &L = *($labl$$label); 7015 Label* L = $labl$$label;
7132 int flag = $cmp$$cmpcode; 7016 int flag = $cmp$$cmpcode;
7133 7017
7134 switch(flag) { 7018 switch(flag) {
7135 case 0x01: //equal 7019 case 0x01: //equal
7136 if (&L) 7020 __ beq_long(op1, op2, *L);
7137 __ beq(op1, op2, L);
7138 else
7139 __ beq(op1, op2, (int)0);
7140 break; 7021 break;
7141 case 0x02: //not_equal 7022 case 0x02: //not_equal
7142 if (&L) 7023 __ bne_long(op1, op2, *L);
7143 __ bne(op1, op2, L);
7144 else
7145 __ bne(op1, op2, (int)0);
7146 break; 7024 break;
7147 case 0x03: //above 7025 case 0x03: //above
7148 __ sltu(AT, op2, op1); 7026 __ sltu(AT, op2, op1);
7149 if(&L) 7027 __ bne_long(AT, R0, *L);
7150 __ bne(AT, R0, L);
7151 else
7152 __ bne(AT, R0, (int)0);
7153 break; 7028 break;
7154 case 0x04: //above_equal 7029 case 0x04: //above_equal
7155 __ sltu(AT, op1, op2); 7030 __ sltu(AT, op1, op2);
7156 if(&L) 7031 __ beq_long(AT, R0, *L);
7157 __ beq(AT, R0, L);
7158 else
7159 __ beq(AT, R0, (int)0);
7160 break; 7032 break;
7161 case 0x05: //below 7033 case 0x05: //below
7162 __ sltu(AT, op1, op2); 7034 __ sltu(AT, op1, op2);
7163 if(&L) 7035 __ bne_long(AT, R0, *L);
7164 __ bne(AT, R0, L);
7165 else
7166 __ bne(AT, R0, (int)0);
7167 break; 7036 break;
7168 case 0x06: //below_equal 7037 case 0x06: //below_equal
7169 __ sltu(AT, op2, op1); 7038 __ sltu(AT, op2, op1);
7170 if(&L) 7039 __ beq_long(AT, R0, *L);
7171 __ beq(AT, R0, L);
7172 else
7173 __ beq(AT, R0, (int)0);
7174 break; 7040 break;
7175 default: 7041 default:
7176 Unimplemented(); 7042 Unimplemented();
7177 } 7043 }
7178 __ nop();
7179 __ nop();
7180 %} 7044 %}
7181 7045
7182 ins_pc_relative(1); 7046 ins_pc_relative(1);
7183 ins_pipe( pipe_alu_branch ); 7047 ins_pipe( pipe_alu_branch );
7184 %} 7048 %}
7190 format %{ "BR$cmp $src1, $src2, $labl #@branchConIU_reg_imm_long" %} 7054 format %{ "BR$cmp $src1, $src2, $labl #@branchConIU_reg_imm_long" %}
7191 7055
7192 ins_encode %{ 7056 ins_encode %{
7193 Register op1 = $src1$$Register; 7057 Register op1 = $src1$$Register;
7194 int val = $src2$$constant; 7058 int val = $src2$$constant;
7195 Label &L = *($labl$$label); 7059 Label* L = $labl$$label;
7196 int flag = $cmp$$cmpcode; 7060 int flag = $cmp$$cmpcode;
7197 7061
7198 __ move(AT, val); 7062 __ move(AT, val);
7199 switch(flag) { 7063 switch(flag) {
7200 case 0x01: //equal 7064 case 0x01: //equal
7201 if (&L) 7065 __ beq_long(op1, AT, *L);
7202 __ beq(op1, AT, L);
7203 else
7204 __ beq(op1, AT, (int)0);
7205 break; 7066 break;
7206 case 0x02: //not_equal 7067 case 0x02: //not_equal
7207 if (&L) 7068 __ bne_long(op1, AT, *L);
7208 __ bne(op1, AT, L);
7209 else
7210 __ bne(op1, AT, (int)0);
7211 break; 7069 break;
7212 case 0x03: //above 7070 case 0x03: //above
7213 __ sltu(AT, AT, op1); 7071 __ sltu(AT, AT, op1);
7214 if(&L) 7072 __ bne_long(R0, AT, *L);
7215 __ bne(R0, AT, L);
7216 else
7217 __ bne(R0, AT, (int)0);
7218 break; 7073 break;
7219 case 0x04: //above_equal 7074 case 0x04: //above_equal
7220 __ sltu(AT, op1, AT); 7075 __ sltu(AT, op1, AT);
7221 if(&L) 7076 __ beq_long(AT, R0, *L);
7222 __ beq(AT, R0, L);
7223 else
7224 __ beq(AT, R0, (int)0);
7225 break; 7077 break;
7226 case 0x05: //below 7078 case 0x05: //below
7227 __ sltu(AT, op1, AT); 7079 __ sltu(AT, op1, AT);
7228 if(&L) 7080 __ bne_long(R0, AT, *L);
7229 __ bne(R0, AT, L);
7230 else
7231 __ bne(R0, AT, (int)0);
7232 break; 7081 break;
7233 case 0x06: //below_equal 7082 case 0x06: //below_equal
7234 __ sltu(AT, AT, op1); 7083 __ sltu(AT, AT, op1);
7235 if(&L) 7084 __ beq_long(AT, R0, *L);
7236 __ beq(AT, R0, L);
7237 else
7238 __ beq(AT, R0, (int)0);
7239 break; 7085 break;
7240 default: 7086 default:
7241 Unimplemented(); 7087 Unimplemented();
7242 } 7088 }
7243 __ nop();
7244 __ nop();
7245 %} 7089 %}
7246 7090
7247 ins_pc_relative(1); 7091 ins_pc_relative(1);
7248 ins_pipe( pipe_alu_branch ); 7092 ins_pipe( pipe_alu_branch );
7249 %} 7093 %}
7254 format %{ "BR$cmp $src1, $src2, $labl #@branchConI_reg_reg_long" %} 7098 format %{ "BR$cmp $src1, $src2, $labl #@branchConI_reg_reg_long" %}
7255 7099
7256 ins_encode %{ 7100 ins_encode %{
7257 Register op1 = $src1$$Register; 7101 Register op1 = $src1$$Register;
7258 Register op2 = $src2$$Register; 7102 Register op2 = $src2$$Register;
7259 Label &L = *($labl$$label); 7103 Label* L = $labl$$label;
7260 int flag = $cmp$$cmpcode; 7104 int flag = $cmp$$cmpcode;
7261 7105
7262 switch(flag) { 7106 switch(flag) {
7263 case 0x01: //equal 7107 case 0x01: //equal
7264 if (&L) 7108 __ beq_long(op1, op2, *L);
7265 __ beq(op1, op2, L);
7266 else
7267 __ beq(op1, op2, (int)0);
7268 break; 7109 break;
7269 case 0x02: //not_equal 7110 case 0x02: //not_equal
7270 if (&L) 7111 __ bne_long(op1, op2, *L);
7271 __ bne(op1, op2, L);
7272 else
7273 __ bne(op1, op2, (int)0);
7274 break; 7112 break;
7275 case 0x03: //above 7113 case 0x03: //above
7276 __ slt(AT, op2, op1); 7114 __ slt(AT, op2, op1);
7277 if(&L) 7115 __ bne_long(R0, AT, *L);
7278 __ bne(R0, AT, L);
7279 else
7280 __ bne(R0, AT, (int)0);
7281 break; 7116 break;
7282 case 0x04: //above_equal 7117 case 0x04: //above_equal
7283 __ slt(AT, op1, op2); 7118 __ slt(AT, op1, op2);
7284 if(&L) 7119 __ beq_long(AT, R0, *L);
7285 __ beq(AT, R0, L);
7286 else
7287 __ beq(AT, R0, (int)0);
7288 break; 7120 break;
7289 case 0x05: //below 7121 case 0x05: //below
7290 __ slt(AT, op1, op2); 7122 __ slt(AT, op1, op2);
7291 if(&L) 7123 __ bne_long(R0, AT, *L);
7292 __ bne(R0, AT, L);
7293 else
7294 __ bne(R0, AT, (int)0);
7295 break; 7124 break;
7296 case 0x06: //below_equal 7125 case 0x06: //below_equal
7297 __ slt(AT, op2, op1); 7126 __ slt(AT, op2, op1);
7298 if(&L) 7127 __ beq_long(AT, R0, *L);
7299 __ beq(AT, R0, L); 7128 break;
7300 else
7301 __ beq(AT, R0, (int)0);
7302 break;
7303 default: 7129 default:
7304 Unimplemented(); 7130 Unimplemented();
7305 } 7131 }
7306 __ nop();
7307 __ nop();
7308 %} 7132 %}
7309 7133
7310 ins_pc_relative(1); 7134 ins_pc_relative(1);
7311 ins_pipe( pipe_alu_branch ); 7135 ins_pipe( pipe_alu_branch );
7312 %} 7136 %}
7317 ins_cost(170); 7141 ins_cost(170);
7318 format %{ "BR$cmp $src1, $src2, $labl #@branchConI_reg_imm0_long" %} 7142 format %{ "BR$cmp $src1, $src2, $labl #@branchConI_reg_imm0_long" %}
7319 7143
7320 ins_encode %{ 7144 ins_encode %{
7321 Register op1 = $src1$$Register; 7145 Register op1 = $src1$$Register;
7322 Label &L = *($labl$$label); 7146 Label* L = $labl$$label;
7323 int flag = $cmp$$cmpcode; 7147 int flag = $cmp$$cmpcode;
7324 7148
7325 switch(flag) { 7149 switch(flag) {
7326 case 0x01: //equal 7150 case 0x01: //equal
7327 if (&L) 7151 __ beq_long(op1, R0, *L);
7328 __ beq(op1, R0, L);
7329 else
7330 __ beq(op1, R0, (int)0);
7331 break; 7152 break;
7332 case 0x02: //not_equal 7153 case 0x02: //not_equal
7333 if (&L) 7154 __ bne_long(op1, R0, *L);
7334 __ bne(op1, R0, L);
7335 else
7336 __ bne(op1, R0, (int)0);
7337 break; 7155 break;
7338 case 0x03: //greater 7156 case 0x03: //greater
7339 if(&L) 7157 __ slt(AT, R0, op1);
7340 __ bgtz(op1, L); 7158 __ bne_long(R0, AT, *L);
7341 else
7342 __ bgtz(op1, (int)0);
7343 break; 7159 break;
7344 case 0x04: //greater_equal 7160 case 0x04: //greater_equal
7345 if(&L) 7161 __ slt(AT, op1, R0);
7346 __ bgez(op1, L); 7162 __ beq_long(AT, R0, *L);
7347 else
7348 __ bgez(op1, (int)0);
7349 break; 7163 break;
7350 case 0x05: //less 7164 case 0x05: //less
7351 if(&L) 7165 __ slt(AT, op1, R0);
7352 __ bltz(op1, L); 7166 __ bne_long(R0, AT, *L);
7353 else
7354 __ bltz(op1, (int)0);
7355 break; 7167 break;
7356 case 0x06: //less_equal 7168 case 0x06: //less_equal
7357 if(&L) 7169 __ slt(AT, R0, op1);
7358 __ blez(op1, L); 7170 __ beq_long(AT, R0, *L);
7359 else 7171 break;
7360 __ blez(op1, (int)0);
7361 break;
7362 default: 7172 default:
7363 Unimplemented(); 7173 Unimplemented();
7364 } 7174 }
7365 __ nop();
7366 __ nop();
7367 %} 7175 %}
7368 7176
7369 ins_pc_relative(1); 7177 ins_pc_relative(1);
7370 ins_pipe( pipe_alu_branch ); 7178 ins_pipe( pipe_alu_branch );
7371 %} 7179 %}
7372
7373 7180
7374 instruct branchConI_reg_imm_long(cmpOp cmp, mRegI src1, immI src2, label labl) %{ 7181 instruct branchConI_reg_imm_long(cmpOp cmp, mRegI src1, immI src2, label labl) %{
7375 match( If cmp (CmpI src1 src2) ); 7182 match( If cmp (CmpI src1 src2) );
7376 effect(USE labl); 7183 effect(USE labl);
7377 ins_cost(200); 7184 ins_cost(200);
7378 format %{ "BR$cmp $src1, $src2, $labl #@branchConI_reg_imm_long" %} 7185 format %{ "BR$cmp $src1, $src2, $labl #@branchConI_reg_imm_long" %}
7379 7186
7380 ins_encode %{ 7187 ins_encode %{
7381 Register op1 = $src1$$Register; 7188 Register op1 = $src1$$Register;
7382 int val = $src2$$constant; 7189 int val = $src2$$constant;
7383 Label &L = *($labl$$label); 7190 Label* L = $labl$$label;
7384 int flag = $cmp$$cmpcode; 7191 int flag = $cmp$$cmpcode;
7385 7192
7386 __ move(AT, val); 7193 __ move(AT, val);
7387 switch(flag) { 7194 switch(flag) {
7388 case 0x01: //equal 7195 case 0x01: //equal
7389 if (&L) 7196 __ beq_long(op1, AT, *L);
7390 __ beq(op1, AT, L);
7391 else
7392 __ beq(op1, AT, (int)0);
7393 break; 7197 break;
7394 case 0x02: //not_equal 7198 case 0x02: //not_equal
7395 if (&L) 7199 __ bne_long(op1, AT, *L);
7396 __ bne(op1, AT, L);
7397 else
7398 __ bne(op1, AT, (int)0);
7399 break; 7200 break;
7400 case 0x03: //greater 7201 case 0x03: //greater
7401 __ slt(AT, AT, op1); 7202 __ slt(AT, AT, op1);
7402 if(&L) 7203 __ bne_long(R0, AT, *L);
7403 __ bne(R0, AT, L);
7404 else
7405 __ bne(R0, AT, (int)0);
7406 break; 7204 break;
7407 case 0x04: //greater_equal 7205 case 0x04: //greater_equal
7408 __ slt(AT, op1, AT); 7206 __ slt(AT, op1, AT);
7409 if(&L) 7207 __ beq_long(AT, R0, *L);
7410 __ beq(AT, R0, L);
7411 else
7412 __ beq(AT, R0, (int)0);
7413 break; 7208 break;
7414 case 0x05: //less 7209 case 0x05: //less
7415 __ slt(AT, op1, AT); 7210 __ slt(AT, op1, AT);
7416 if(&L) 7211 __ bne_long(R0, AT, *L);
7417 __ bne(R0, AT, L);
7418 else
7419 __ bne(R0, AT, (int)0);
7420 break; 7212 break;
7421 case 0x06: //less_equal 7213 case 0x06: //less_equal
7422 __ slt(AT, AT, op1); 7214 __ slt(AT, AT, op1);
7423 if(&L) 7215 __ beq_long(AT, R0, *L);
7424 __ beq(AT, R0, L);
7425 else
7426 __ beq(AT, R0, (int)0);
7427 break; 7216 break;
7428 default: 7217 default:
7429 Unimplemented(); 7218 Unimplemented();
7430 } 7219 }
7431 __ nop();
7432 __ nop();
7433 %} 7220 %}
7434 7221
7435 ins_pc_relative(1); 7222 ins_pc_relative(1);
7436 ins_pipe( pipe_alu_branch ); 7223 ins_pipe( pipe_alu_branch );
7437 %} 7224 %}
7441 effect(USE labl); 7228 effect(USE labl);
7442 format %{ "BR$cmp $src1, zero, $labl #@branchConIU_reg_imm0_long" %} 7229 format %{ "BR$cmp $src1, zero, $labl #@branchConIU_reg_imm0_long" %}
7443 7230
7444 ins_encode %{ 7231 ins_encode %{
7445 Register op1 = $src1$$Register; 7232 Register op1 = $src1$$Register;
7446 Label &L = *($labl$$label); 7233 Label* L = $labl$$label;
7447 int flag = $cmp$$cmpcode; 7234 int flag = $cmp$$cmpcode;
7448 7235
7449 switch(flag) { 7236 switch(flag) {
7450 case 0x01: //equal 7237 case 0x01: //equal
7451 if (&L) 7238 __ beq_long(op1, R0, *L);
7452 __ beq(op1, R0, L);
7453 else
7454 __ beq(op1, R0, (int)0);
7455 break; 7239 break;
7456 case 0x02: //not_equal 7240 case 0x02: //not_equal
7457 if (&L) 7241 __ bne_long(op1, R0, *L);
7458 __ bne(op1, R0, L);
7459 else
7460 __ bne(op1, R0, (int)0);
7461 break; 7242 break;
7462 case 0x03: //above 7243 case 0x03: //above
7463 if(&L) 7244 __ bne_long(R0, op1, *L);
7464 __ bne(R0, op1, L);
7465 else
7466 __ bne(R0, op1, (int)0);
7467 break; 7245 break;
7468 case 0x04: //above_equal 7246 case 0x04: //above_equal
7469 if(&L) 7247 __ beq_long(R0, R0, *L);
7470 __ beq(R0, R0, L);
7471 else
7472 __ beq(R0, R0, (int)0);
7473 break; 7248 break;
7474 case 0x05: //below 7249 case 0x05: //below
7475 return; 7250 return;
7476 break; 7251 break;
7477 case 0x06: //below_equal 7252 case 0x06: //below_equal
7478 if(&L) 7253 __ beq_long(op1, R0, *L);
7479 __ beq(op1, R0, L);
7480 else
7481 __ beq(op1, R0, (int)0);
7482 break; 7254 break;
7483 default: 7255 default:
7484 Unimplemented(); 7256 Unimplemented();
7485 } 7257 }
7486 __ nop(); 7258 %}
7487 __ nop();
7488 %}
7489 7259
7490 ins_pc_relative(1); 7260 ins_pc_relative(1);
7491 ins_pipe( pipe_alu_branch ); 7261 ins_pipe( pipe_alu_branch );
7492 %} 7262 %}
7493 7263
7499 format %{ "BR$cmp $src1, $src2, $labl #@branchConIU_reg_immI16_long" %} 7269 format %{ "BR$cmp $src1, $src2, $labl #@branchConIU_reg_immI16_long" %}
7500 7270
7501 ins_encode %{ 7271 ins_encode %{
7502 Register op1 = $src1$$Register; 7272 Register op1 = $src1$$Register;
7503 int val = $src2$$constant; 7273 int val = $src2$$constant;
7504 Label &L = *($labl$$label); 7274 Label* L = $labl$$label;
7505 int flag = $cmp$$cmpcode; 7275 int flag = $cmp$$cmpcode;
7506 7276
7507 switch(flag) { 7277 switch(flag) {
7508 case 0x01: //equal 7278 case 0x01: //equal
7509 __ move(AT, val); 7279 __ move(AT, val);
7510 if (&L) 7280 __ beq_long(op1, AT, *L);
7511 __ beq(op1, AT, L);
7512 else
7513 __ beq(op1, AT, (int)0);
7514 break; 7281 break;
7515 case 0x02: //not_equal 7282 case 0x02: //not_equal
7516 __ move(AT, val); 7283 __ move(AT, val);
7517 if (&L) 7284 __ bne_long(op1, AT, *L);
7518 __ bne(op1, AT, L);
7519 else
7520 __ bne(op1, AT, (int)0);
7521 break; 7285 break;
7522 case 0x03: //above 7286 case 0x03: //above
7523 __ move(AT, val); 7287 __ move(AT, val);
7524 __ sltu(AT, AT, op1); 7288 __ sltu(AT, AT, op1);
7525 if(&L) 7289 __ bne_long(R0, AT, *L);
7526 __ bne(R0, AT, L);
7527 else
7528 __ bne(R0, AT, (int)0);
7529 break; 7290 break;
7530 case 0x04: //above_equal 7291 case 0x04: //above_equal
7531 __ sltiu(AT, op1, val); 7292 __ sltiu(AT, op1, val);
7532 if(&L) 7293 __ beq_long(AT, R0, *L);
7533 __ beq(AT, R0, L);
7534 else
7535 __ beq(AT, R0, (int)0);
7536 break; 7294 break;
7537 case 0x05: //below 7295 case 0x05: //below
7538 __ sltiu(AT, op1, val); 7296 __ sltiu(AT, op1, val);
7539 if(&L) 7297 __ bne_long(R0, AT, *L);
7540 __ bne(R0, AT, L);
7541 else
7542 __ bne(R0, AT, (int)0);
7543 break; 7298 break;
7544 case 0x06: //below_equal 7299 case 0x06: //below_equal
7545 __ move(AT, val); 7300 __ move(AT, val);
7546 __ sltu(AT, AT, op1); 7301 __ sltu(AT, AT, op1);
7547 if(&L) 7302 __ beq_long(AT, R0, *L);
7548 __ beq(AT, R0, L);
7549 else
7550 __ beq(AT, R0, (int)0);
7551 break; 7303 break;
7552 default: 7304 default:
7553 Unimplemented(); 7305 Unimplemented();
7554 } 7306 }
7555 __ nop();
7556 __ nop();
7557 %} 7307 %}
7558 7308
7559 ins_pc_relative(1); 7309 ins_pc_relative(1);
7560 ins_pipe( pipe_alu_branch ); 7310 ins_pipe( pipe_alu_branch );
7561 %} 7311 %}
7569 7319
7570 ins_encode %{ 7320 ins_encode %{
7571 Register opr1_reg = as_Register($src1$$reg); 7321 Register opr1_reg = as_Register($src1$$reg);
7572 Register opr2_reg = as_Register($src2$$reg); 7322 Register opr2_reg = as_Register($src2$$reg);
7573 7323
7574 Label &target = *($labl$$label); 7324 Label* target = $labl$$label;
7575 int flag = $cmp$$cmpcode; 7325 int flag = $cmp$$cmpcode;
7576 7326
7577 switch(flag) { 7327 switch(flag) {
7578 case 0x01: //equal 7328 case 0x01: //equal
7579 if (&target) 7329 __ beq_long(opr1_reg, opr2_reg, *target);
7580 __ beq(opr1_reg, opr2_reg, target);
7581 else
7582 __ beq(opr1_reg, opr2_reg, (int)0);
7583 __ delayed()->nop();
7584 break; 7330 break;
7585 7331
7586 case 0x02: //not_equal 7332 case 0x02: //not_equal
7587 if(&target) 7333 __ bne_long(opr1_reg, opr2_reg, *target);
7588 __ bne(opr1_reg, opr2_reg, target);
7589 else
7590 __ bne(opr1_reg, opr2_reg, (int)0);
7591 __ delayed()->nop();
7592 break; 7334 break;
7593 7335
7594 case 0x03: //greater 7336 case 0x03: //greater
7595 __ slt(AT, opr2_reg, opr1_reg); 7337 __ slt(AT, opr2_reg, opr1_reg);
7596 if(&target) 7338 __ bne_long(AT, R0, *target);
7597 __ bne(AT, R0, target);
7598 else
7599 __ bne(AT, R0, (int)0);
7600 __ delayed()->nop();
7601 break; 7339 break;
7602 7340
7603 case 0x04: //greater_equal 7341 case 0x04: //greater_equal
7604 __ slt(AT, opr1_reg, opr2_reg); 7342 __ slt(AT, opr1_reg, opr2_reg);
7605 if(&target) 7343 __ beq_long(AT, R0, *target);
7606 __ beq(AT, R0, target);
7607 else
7608 __ beq(AT, R0, (int)0);
7609 __ delayed()->nop();
7610
7611 break; 7344 break;
7612 7345
7613 case 0x05: //less 7346 case 0x05: //less
7614 __ slt(AT, opr1_reg, opr2_reg); 7347 __ slt(AT, opr1_reg, opr2_reg);
7615 if(&target) 7348 __ bne_long(AT, R0, *target);
7616 __ bne(AT, R0, target);
7617 else
7618 __ bne(AT, R0, (int)0);
7619 __ delayed()->nop();
7620
7621 break; 7349 break;
7622 7350
7623 case 0x06: //less_equal 7351 case 0x06: //less_equal
7624 __ slt(AT, opr2_reg, opr1_reg); 7352 __ slt(AT, opr2_reg, opr1_reg);
7625 7353 __ beq_long(AT, R0, *target);
7626 if(&target)
7627 __ beq(AT, R0, target);
7628 else
7629 __ beq(AT, R0, (int)0);
7630 __ delayed()->nop();
7631
7632 break; 7354 break;
7633 7355
7634 default: 7356 default:
7635 Unimplemented(); 7357 Unimplemented();
7636 } 7358 }
7637 __ nop();
7638 %} 7359 %}
7639 7360
7640 7361
7641 ins_pc_relative(1); 7362 ins_pc_relative(1);
7642 ins_pipe( pipe_alu_branch ); 7363 ins_pipe( pipe_alu_branch );
7643 %} 7364 %}
7644
7645 7365
7646 instruct branchConL_regL_immL0_long(cmpOp cmp, mRegL src1, immL0 zero, label labl) %{ 7366 instruct branchConL_regL_immL0_long(cmpOp cmp, mRegL src1, immL0 zero, label labl) %{
7647 match( If cmp (CmpL src1 zero) ); 7367 match( If cmp (CmpL src1 zero) );
7648 effect(USE labl); 7368 effect(USE labl);
7649 format %{ "BR$cmp $src1, zero, $labl #@branchConL_regL_immL0_long" %} 7369 format %{ "BR$cmp $src1, zero, $labl #@branchConL_regL_immL0_long" %}
7650 ins_cost(150); 7370 ins_cost(150);
7651 7371
7652 ins_encode %{ 7372 ins_encode %{
7653 Register opr1_reg = as_Register($src1$$reg); 7373 Register opr1_reg = as_Register($src1$$reg);
7654 Label &target = *($labl$$label); 7374 Register opr2_reg = R0;
7375
7376 Label* target = $labl$$label;
7655 int flag = $cmp$$cmpcode; 7377 int flag = $cmp$$cmpcode;
7656 7378
7657 switch(flag) { 7379 switch(flag) {
7658 case 0x01: //equal 7380 case 0x01: //equal
7659 if (&target) 7381 __ beq_long(opr1_reg, opr2_reg, *target);
7660 __ beq(opr1_reg, R0, target);
7661 else
7662 __ beq(opr1_reg, R0, int(0));
7663 break; 7382 break;
7664 7383
7665 case 0x02: //not_equal 7384 case 0x02: //not_equal
7666 if(&target) 7385 __ bne_long(opr1_reg, opr2_reg, *target);
7667 __ bne(opr1_reg, R0, target);
7668 else
7669 __ bne(opr1_reg, R0, (int)0);
7670 break; 7386 break;
7671 7387
7672 case 0x03: //greater 7388 case 0x03: //greater
7673 if(&target) 7389 __ slt(AT, opr2_reg, opr1_reg);
7674 __ bgtz(opr1_reg, target); 7390 __ bne_long(AT, R0, *target);
7675 else 7391 break;
7676 __ bgtz(opr1_reg, (int)0);
7677 break;
7678 7392
7679 case 0x04: //greater_equal 7393 case 0x04: //greater_equal
7680 if(&target) 7394 __ slt(AT, opr1_reg, opr2_reg);
7681 __ bgez(opr1_reg, target); 7395 __ beq_long(AT, R0, *target);
7682 else
7683 __ bgez(opr1_reg, (int)0);
7684 break; 7396 break;
7685 7397
7686 case 0x05: //less 7398 case 0x05: //less
7687 __ slt(AT, opr1_reg, R0); 7399 __ slt(AT, opr1_reg, opr2_reg);
7688 if(&target) 7400 __ bne_long(AT, R0, *target);
7689 __ bne(AT, R0, target);
7690 else
7691 __ bne(AT, R0, (int)0);
7692 break; 7401 break;
7693 7402
7694 case 0x06: //less_equal 7403 case 0x06: //less_equal
7695 if (&target) 7404 __ slt(AT, opr2_reg, opr1_reg);
7696 __ blez(opr1_reg, target); 7405 __ beq_long(AT, R0, *target);
7697 else
7698 __ blez(opr1_reg, int(0));
7699 break; 7406 break;
7700 7407
7701 default: 7408 default:
7702 Unimplemented(); 7409 Unimplemented();
7703 } 7410 }
7704 __ delayed()->nop();
7705 __ nop();
7706 %} 7411 %}
7707 7412
7708 7413
7709 ins_pc_relative(1); 7414 ins_pc_relative(1);
7710 ins_pipe( pipe_alu_branch ); 7415 ins_pipe( pipe_alu_branch );
7718 7423
7719 ins_encode %{ 7424 ins_encode %{
7720 Register opr1_reg = as_Register($src1$$reg); 7425 Register opr1_reg = as_Register($src1$$reg);
7721 Register opr2_reg = AT; 7426 Register opr2_reg = AT;
7722 7427
7723 Label &target = *($labl$$label); 7428 Label* target = $labl$$label;
7724 int flag = $cmp$$cmpcode; 7429 int flag = $cmp$$cmpcode;
7725 7430
7726 __ set64(opr2_reg, $src2$$constant); 7431 __ set64(opr2_reg, $src2$$constant);
7727 7432
7728 switch(flag) { 7433 switch(flag) {
7729 case 0x01: //equal 7434 case 0x01: //equal
7730 if (&target) 7435 __ beq_long(opr1_reg, opr2_reg, *target);
7731 __ beq(opr1_reg, opr2_reg, target);
7732 else
7733 __ beq(opr1_reg, opr2_reg, (int)0);
7734 break; 7436 break;
7735 7437
7736 case 0x02: //not_equal 7438 case 0x02: //not_equal
7737 if(&target) 7439 __ bne_long(opr1_reg, opr2_reg, *target);
7738 __ bne(opr1_reg, opr2_reg, target);
7739 else
7740 __ bne(opr1_reg, opr2_reg, (int)0);
7741 break; 7440 break;
7742 7441
7743 case 0x03: //greater 7442 case 0x03: //greater
7744 __ slt(AT, opr2_reg, opr1_reg); 7443 __ slt(AT, opr2_reg, opr1_reg);
7745 if(&target) 7444 __ bne_long(AT, R0, *target);
7746 __ bne(AT, R0, target);
7747 else
7748 __ bne(AT, R0, (int)0);
7749 break; 7445 break;
7750 7446
7751 case 0x04: //greater_equal 7447 case 0x04: //greater_equal
7752 __ slt(AT, opr1_reg, opr2_reg); 7448 __ slt(AT, opr1_reg, opr2_reg);
7753 if(&target) 7449 __ beq_long(AT, R0, *target);
7754 __ beq(AT, R0, target);
7755 else
7756 __ beq(AT, R0, (int)0);
7757 break; 7450 break;
7758 7451
7759 case 0x05: //less 7452 case 0x05: //less
7760 __ slt(AT, opr1_reg, opr2_reg); 7453 __ slt(AT, opr1_reg, opr2_reg);
7761 if(&target) 7454 __ bne_long(AT, R0, *target);
7762 __ bne(AT, R0, target);
7763 else
7764 __ bne(AT, R0, (int)0);
7765 break; 7455 break;
7766 7456
7767 case 0x06: //less_equal 7457 case 0x06: //less_equal
7768 __ slt(AT, opr2_reg, opr1_reg); 7458 __ slt(AT, opr2_reg, opr1_reg);
7769 if(&target) 7459 __ beq_long(AT, R0, *target);
7770 __ beq(AT, R0, target);
7771 else
7772 __ beq(AT, R0, (int)0);
7773 break; 7460 break;
7774 7461
7775 default: 7462 default:
7776 Unimplemented(); 7463 Unimplemented();
7777 } 7464 }
7778 __ nop();
7779 __ nop();
7780 %} 7465 %}
7781 7466
7782 7467
7783 ins_pc_relative(1); 7468 ins_pc_relative(1);
7784 ins_pipe( pipe_alu_branch ); 7469 ins_pipe( pipe_alu_branch );
7792 format %{ "BR$cmp $src1, $src2, $labl #@branchConF_reg_reg_long" %} 7477 format %{ "BR$cmp $src1, $src2, $labl #@branchConF_reg_reg_long" %}
7793 7478
7794 ins_encode %{ 7479 ins_encode %{
7795 FloatRegister reg_op1 = $src1$$FloatRegister; 7480 FloatRegister reg_op1 = $src1$$FloatRegister;
7796 FloatRegister reg_op2 = $src2$$FloatRegister; 7481 FloatRegister reg_op2 = $src2$$FloatRegister;
7797 Label &L = *($labl$$label); 7482 Label* L = $labl$$label;
7798 int flag = $cmp$$cmpcode; 7483 int flag = $cmp$$cmpcode;
7799 7484
7800 switch(flag) { 7485 switch(flag) {
7801 case 0x01: //equal 7486 case 0x01: //equal
7802 __ c_eq_s(reg_op1, reg_op2); 7487 __ c_eq_s(reg_op1, reg_op2);
7803 if (&L) 7488 __ bc1t_long(*L);
7804 __ bc1t(L);
7805 else
7806 __ bc1t((int)0);
7807 break; 7489 break;
7808 case 0x02: //not_equal 7490 case 0x02: //not_equal
7809 __ c_eq_s(reg_op1, reg_op2); 7491 __ c_eq_s(reg_op1, reg_op2);
7810 if (&L) 7492 __ bc1f_long(*L);
7811 __ bc1f(L);
7812 else
7813 __ bc1f((int)0);
7814 break; 7493 break;
7815 case 0x03: //greater 7494 case 0x03: //greater
7816 __ c_ule_s(reg_op1, reg_op2); 7495 __ c_ule_s(reg_op1, reg_op2);
7817 if(&L) 7496 __ bc1f_long(*L);
7818 __ bc1f(L);
7819 else
7820 __ bc1f((int)0);
7821 break; 7497 break;
7822 case 0x04: //greater_equal 7498 case 0x04: //greater_equal
7823 __ c_ult_s(reg_op1, reg_op2); 7499 __ c_ult_s(reg_op1, reg_op2);
7824 if(&L) 7500 __ bc1f_long(*L);
7825 __ bc1f(L);
7826 else
7827 __ bc1f((int)0);
7828 break; 7501 break;
7829 case 0x05: //less 7502 case 0x05: //less
7830 __ c_ult_s(reg_op1, reg_op2); 7503 __ c_ult_s(reg_op1, reg_op2);
7831 if(&L) 7504 __ bc1t_long(*L);
7832 __ bc1t(L);
7833 else
7834 __ bc1t((int)0);
7835 break; 7505 break;
7836 case 0x06: //less_equal 7506 case 0x06: //less_equal
7837 __ c_ule_s(reg_op1, reg_op2); 7507 __ c_ule_s(reg_op1, reg_op2);
7838 if(&L) 7508 __ bc1t_long(*L);
7839 __ bc1t(L);
7840 else
7841 __ bc1t((int)0);
7842 break; 7509 break;
7843 default: 7510 default:
7844 Unimplemented(); 7511 Unimplemented();
7845 } 7512 }
7846 __ nop();
7847 __ nop();
7848 %} 7513 %}
7849 7514
7850 ins_pc_relative(1); 7515 ins_pc_relative(1);
7851 ins_pipe(pipe_slow); 7516 ins_pipe(pipe_slow);
7852 %} 7517 %}
7857 format %{ "BR$cmp $src1, $src2, $labl #@branchConD_reg_reg_long" %} 7522 format %{ "BR$cmp $src1, $src2, $labl #@branchConD_reg_reg_long" %}
7858 7523
7859 ins_encode %{ 7524 ins_encode %{
7860 FloatRegister reg_op1 = $src1$$FloatRegister; 7525 FloatRegister reg_op1 = $src1$$FloatRegister;
7861 FloatRegister reg_op2 = $src2$$FloatRegister; 7526 FloatRegister reg_op2 = $src2$$FloatRegister;
7862 Label &L = *($labl$$label); 7527 Label* L = $labl$$label;
7863 int flag = $cmp$$cmpcode; 7528 int flag = $cmp$$cmpcode;
7864 7529
7865 switch(flag) { 7530 switch(flag) {
7866 case 0x01: //equal 7531 case 0x01: //equal
7867 __ c_eq_d(reg_op1, reg_op2); 7532 __ c_eq_d(reg_op1, reg_op2);
7868 if (&L) 7533 __ bc1t_long(*L);
7869 __ bc1t(L);
7870 else
7871 __ bc1t((int)0);
7872 break; 7534 break;
7873 case 0x02: //not_equal 7535 case 0x02: //not_equal
7874 //2016/4/19 aoqi: c_ueq_d cannot distinguish NaN from equal. Double.isNaN(Double) is implemented by 'f != f', so the use of c_ueq_d causes bugs. 7536 //2016/4/19 aoqi: c_ueq_d cannot distinguish NaN from equal. Double.isNaN(Double) is implemented by 'f != f', so the use of c_ueq_d causes bugs.
7875 __ c_eq_d(reg_op1, reg_op2); 7537 __ c_eq_d(reg_op1, reg_op2);
7876 if (&L) 7538 __ bc1f_long(*L);
7877 __ bc1f(L);
7878 else
7879 __ bc1f((int)0);
7880 break; 7539 break;
7881 case 0x03: //greater 7540 case 0x03: //greater
7882 __ c_ule_d(reg_op1, reg_op2); 7541 __ c_ule_d(reg_op1, reg_op2);
7883 if(&L) 7542 __ bc1f_long(*L);
7884 __ bc1f(L);
7885 else
7886 __ bc1f((int)0);
7887 break; 7543 break;
7888 case 0x04: //greater_equal 7544 case 0x04: //greater_equal
7889 __ c_ult_d(reg_op1, reg_op2); 7545 __ c_ult_d(reg_op1, reg_op2);
7890 if(&L) 7546 __ bc1f_long(*L);
7891 __ bc1f(L);
7892 else
7893 __ bc1f((int)0);
7894 break; 7547 break;
7895 case 0x05: //less 7548 case 0x05: //less
7896 __ c_ult_d(reg_op1, reg_op2); 7549 __ c_ult_d(reg_op1, reg_op2);
7897 if(&L) 7550 __ bc1t_long(*L);
7898 __ bc1t(L);
7899 else
7900 __ bc1t((int)0);
7901 break; 7551 break;
7902 case 0x06: //less_equal 7552 case 0x06: //less_equal
7903 __ c_ule_d(reg_op1, reg_op2); 7553 __ c_ule_d(reg_op1, reg_op2);
7904 if(&L) 7554 __ bc1t_long(*L);
7905 __ bc1t(L);
7906 else
7907 __ bc1t((int)0);
7908 break; 7555 break;
7909 default: 7556 default:
7910 Unimplemented(); 7557 Unimplemented();
7911 } 7558 }
7912 __ nop();
7913 __ nop();
7914 %} 7559 %}
7915 7560
7916 ins_pc_relative(1); 7561 ins_pc_relative(1);
7917 ins_pipe(pipe_slow); 7562 ins_pipe(pipe_slow);
7918 %} 7563 %}
7932 ins_encode %{ 7577 ins_encode %{
7933 Label &L = *($labl$$label); 7578 Label &L = *($labl$$label);
7934 if(&L) 7579 if(&L)
7935 __ b(L); 7580 __ b(L);
7936 else 7581 else
7937 __ b(int(0)); 7582 __ b(int(0));
7938 __ nop(); 7583 __ nop();
7939 %} 7584 %}
7940 7585
7941 ins_pipe( pipe_jump ); 7586 ins_pipe( pipe_jump );
7942 ins_pc_relative(1); 7587 ins_pc_relative(1);

Mercurial Repository: jdk8-mips64-public/hotspot

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