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1 /* |
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2 * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. |
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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4 * |
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5 * This code is free software; you can redistribute it and/or modify it |
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6 * under the terms of the GNU General Public License version 2 only, as |
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7 * published by the Free Software Foundation. |
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8 * |
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9 * This code is distributed in the hope that it will be useful, but WITHOUT |
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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12 * version 2 for more details (a copy is included in the LICENSE file that |
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13 * accompanied this code). |
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14 * |
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15 * You should have received a copy of the GNU General Public License version |
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16 * 2 along with this work; if not, write to the Free Software Foundation, |
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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18 * |
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
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22 * |
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23 */ |
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24 |
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25 #include "precompiled.hpp" |
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26 #include "asm/macroAssembler.hpp" |
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27 #include "asm/macroAssembler.inline.hpp" |
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28 #include "memory/resourceArea.hpp" |
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29 #include "runtime/java.hpp" |
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30 #include "runtime/stubCodeGenerator.hpp" |
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31 #include "vm_version_x86.hpp" |
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32 #ifdef TARGET_OS_FAMILY_linux |
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33 # include "os_linux.inline.hpp" |
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34 #endif |
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35 #ifdef TARGET_OS_FAMILY_solaris |
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36 # include "os_solaris.inline.hpp" |
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37 #endif |
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38 #ifdef TARGET_OS_FAMILY_windows |
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39 # include "os_windows.inline.hpp" |
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40 #endif |
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41 #ifdef TARGET_OS_FAMILY_bsd |
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42 # include "os_bsd.inline.hpp" |
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43 #endif |
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44 |
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45 |
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46 int VM_Version::_cpu; |
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47 int VM_Version::_model; |
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48 int VM_Version::_stepping; |
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49 int VM_Version::_cpuFeatures; |
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50 const char* VM_Version::_features_str = ""; |
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51 VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, }; |
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52 |
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53 // Address of instruction which causes SEGV |
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54 address VM_Version::_cpuinfo_segv_addr = 0; |
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55 // Address of instruction after the one which causes SEGV |
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56 address VM_Version::_cpuinfo_cont_addr = 0; |
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57 |
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58 static BufferBlob* stub_blob; |
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59 static const int stub_size = 600; |
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60 |
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61 extern "C" { |
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62 typedef void (*get_cpu_info_stub_t)(void*); |
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63 } |
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64 static get_cpu_info_stub_t get_cpu_info_stub = NULL; |
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65 |
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66 |
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67 class VM_Version_StubGenerator: public StubCodeGenerator { |
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68 public: |
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69 |
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70 VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {} |
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71 |
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72 address generate_get_cpu_info() { |
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73 // Flags to test CPU type. |
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74 const uint32_t HS_EFL_AC = 0x40000; |
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75 const uint32_t HS_EFL_ID = 0x200000; |
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76 // Values for when we don't have a CPUID instruction. |
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77 const int CPU_FAMILY_SHIFT = 8; |
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78 const uint32_t CPU_FAMILY_386 = (3 << CPU_FAMILY_SHIFT); |
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79 const uint32_t CPU_FAMILY_486 = (4 << CPU_FAMILY_SHIFT); |
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80 |
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81 Label detect_486, cpu486, detect_586, std_cpuid1, std_cpuid4; |
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82 Label sef_cpuid, ext_cpuid, ext_cpuid1, ext_cpuid5, ext_cpuid7, done; |
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83 |
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84 StubCodeMark mark(this, "VM_Version", "get_cpu_info_stub"); |
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85 # define __ _masm-> |
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86 |
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87 address start = __ pc(); |
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88 |
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89 // |
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90 // void get_cpu_info(VM_Version::CpuidInfo* cpuid_info); |
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91 // |
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92 // LP64: rcx and rdx are first and second argument registers on windows |
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93 |
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94 __ push(rbp); |
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95 #ifdef _LP64 |
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96 __ mov(rbp, c_rarg0); // cpuid_info address |
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97 #else |
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98 __ movptr(rbp, Address(rsp, 8)); // cpuid_info address |
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99 #endif |
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100 __ push(rbx); |
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101 __ push(rsi); |
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102 __ pushf(); // preserve rbx, and flags |
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103 __ pop(rax); |
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104 __ push(rax); |
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105 __ mov(rcx, rax); |
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106 // |
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107 // if we are unable to change the AC flag, we have a 386 |
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108 // |
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109 __ xorl(rax, HS_EFL_AC); |
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110 __ push(rax); |
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111 __ popf(); |
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112 __ pushf(); |
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113 __ pop(rax); |
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114 __ cmpptr(rax, rcx); |
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115 __ jccb(Assembler::notEqual, detect_486); |
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116 |
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117 __ movl(rax, CPU_FAMILY_386); |
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118 __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax); |
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119 __ jmp(done); |
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120 |
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121 // |
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122 // If we are unable to change the ID flag, we have a 486 which does |
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123 // not support the "cpuid" instruction. |
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124 // |
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125 __ bind(detect_486); |
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126 __ mov(rax, rcx); |
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127 __ xorl(rax, HS_EFL_ID); |
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128 __ push(rax); |
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129 __ popf(); |
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130 __ pushf(); |
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131 __ pop(rax); |
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132 __ cmpptr(rcx, rax); |
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133 __ jccb(Assembler::notEqual, detect_586); |
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134 |
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135 __ bind(cpu486); |
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136 __ movl(rax, CPU_FAMILY_486); |
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137 __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax); |
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138 __ jmp(done); |
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139 |
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140 // |
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141 // At this point, we have a chip which supports the "cpuid" instruction |
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142 // |
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143 __ bind(detect_586); |
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144 __ xorl(rax, rax); |
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145 __ cpuid(); |
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146 __ orl(rax, rax); |
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147 __ jcc(Assembler::equal, cpu486); // if cpuid doesn't support an input |
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148 // value of at least 1, we give up and |
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149 // assume a 486 |
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150 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); |
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151 __ movl(Address(rsi, 0), rax); |
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152 __ movl(Address(rsi, 4), rbx); |
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153 __ movl(Address(rsi, 8), rcx); |
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154 __ movl(Address(rsi,12), rdx); |
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155 |
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156 __ cmpl(rax, 0xa); // Is cpuid(0xB) supported? |
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157 __ jccb(Assembler::belowEqual, std_cpuid4); |
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158 |
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159 // |
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160 // cpuid(0xB) Processor Topology |
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161 // |
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162 __ movl(rax, 0xb); |
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163 __ xorl(rcx, rcx); // Threads level |
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164 __ cpuid(); |
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165 |
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166 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB0_offset()))); |
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167 __ movl(Address(rsi, 0), rax); |
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168 __ movl(Address(rsi, 4), rbx); |
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169 __ movl(Address(rsi, 8), rcx); |
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170 __ movl(Address(rsi,12), rdx); |
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171 |
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172 __ movl(rax, 0xb); |
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173 __ movl(rcx, 1); // Cores level |
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174 __ cpuid(); |
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175 __ push(rax); |
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176 __ andl(rax, 0x1f); // Determine if valid topology level |
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177 __ orl(rax, rbx); // eax[4:0] | ebx[0:15] == 0 indicates invalid level |
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178 __ andl(rax, 0xffff); |
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179 __ pop(rax); |
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180 __ jccb(Assembler::equal, std_cpuid4); |
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181 |
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182 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB1_offset()))); |
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183 __ movl(Address(rsi, 0), rax); |
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184 __ movl(Address(rsi, 4), rbx); |
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185 __ movl(Address(rsi, 8), rcx); |
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186 __ movl(Address(rsi,12), rdx); |
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187 |
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188 __ movl(rax, 0xb); |
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189 __ movl(rcx, 2); // Packages level |
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190 __ cpuid(); |
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191 __ push(rax); |
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192 __ andl(rax, 0x1f); // Determine if valid topology level |
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193 __ orl(rax, rbx); // eax[4:0] | ebx[0:15] == 0 indicates invalid level |
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194 __ andl(rax, 0xffff); |
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195 __ pop(rax); |
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196 __ jccb(Assembler::equal, std_cpuid4); |
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197 |
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198 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB2_offset()))); |
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199 __ movl(Address(rsi, 0), rax); |
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200 __ movl(Address(rsi, 4), rbx); |
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201 __ movl(Address(rsi, 8), rcx); |
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202 __ movl(Address(rsi,12), rdx); |
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203 |
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204 // |
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205 // cpuid(0x4) Deterministic cache params |
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206 // |
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207 __ bind(std_cpuid4); |
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208 __ movl(rax, 4); |
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209 __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x4) supported? |
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210 __ jccb(Assembler::greater, std_cpuid1); |
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211 |
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212 __ xorl(rcx, rcx); // L1 cache |
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213 __ cpuid(); |
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214 __ push(rax); |
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215 __ andl(rax, 0x1f); // Determine if valid cache parameters used |
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216 __ orl(rax, rax); // eax[4:0] == 0 indicates invalid cache |
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217 __ pop(rax); |
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218 __ jccb(Assembler::equal, std_cpuid1); |
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219 |
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220 __ lea(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset()))); |
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221 __ movl(Address(rsi, 0), rax); |
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222 __ movl(Address(rsi, 4), rbx); |
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223 __ movl(Address(rsi, 8), rcx); |
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224 __ movl(Address(rsi,12), rdx); |
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225 |
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226 // |
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227 // Standard cpuid(0x1) |
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228 // |
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229 __ bind(std_cpuid1); |
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230 __ movl(rax, 1); |
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231 __ cpuid(); |
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232 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset()))); |
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233 __ movl(Address(rsi, 0), rax); |
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234 __ movl(Address(rsi, 4), rbx); |
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235 __ movl(Address(rsi, 8), rcx); |
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236 __ movl(Address(rsi,12), rdx); |
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237 |
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238 // |
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239 // Check if OS has enabled XGETBV instruction to access XCR0 |
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240 // (OSXSAVE feature flag) and CPU supports AVX |
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241 // |
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242 __ andl(rcx, 0x18000000); // cpuid1 bits osxsave | avx |
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243 __ cmpl(rcx, 0x18000000); |
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244 __ jccb(Assembler::notEqual, sef_cpuid); // jump if AVX is not supported |
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245 |
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246 // |
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247 // XCR0, XFEATURE_ENABLED_MASK register |
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248 // |
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249 __ xorl(rcx, rcx); // zero for XCR0 register |
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250 __ xgetbv(); |
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251 __ lea(rsi, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); |
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252 __ movl(Address(rsi, 0), rax); |
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253 __ movl(Address(rsi, 4), rdx); |
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254 |
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255 __ andl(rax, 0x6); // xcr0 bits sse | ymm |
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256 __ cmpl(rax, 0x6); |
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257 __ jccb(Assembler::notEqual, sef_cpuid); // jump if AVX is not supported |
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258 |
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259 // |
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260 // Some OSs have a bug when upper 128bits of YMM |
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261 // registers are not restored after a signal processing. |
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262 // Generate SEGV here (reference through NULL) |
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263 // and check upper YMM bits after it. |
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264 // |
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265 VM_Version::set_avx_cpuFeatures(); // Enable temporary to pass asserts |
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266 intx saved_useavx = UseAVX; |
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267 intx saved_usesse = UseSSE; |
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268 UseAVX = 1; |
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269 UseSSE = 2; |
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270 |
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271 // load value into all 32 bytes of ymm7 register |
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272 __ movl(rcx, VM_Version::ymm_test_value()); |
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273 |
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274 __ movdl(xmm0, rcx); |
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275 __ pshufd(xmm0, xmm0, 0x00); |
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276 __ vinsertf128h(xmm0, xmm0, xmm0); |
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277 __ vmovdqu(xmm7, xmm0); |
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278 #ifdef _LP64 |
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279 __ vmovdqu(xmm8, xmm0); |
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280 __ vmovdqu(xmm15, xmm0); |
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281 #endif |
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282 |
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283 __ xorl(rsi, rsi); |
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284 VM_Version::set_cpuinfo_segv_addr( __ pc() ); |
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285 // Generate SEGV |
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286 __ movl(rax, Address(rsi, 0)); |
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287 |
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288 VM_Version::set_cpuinfo_cont_addr( __ pc() ); |
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289 // Returns here after signal. Save xmm0 to check it later. |
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290 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ymm_save_offset()))); |
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291 __ vmovdqu(Address(rsi, 0), xmm0); |
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292 __ vmovdqu(Address(rsi, 32), xmm7); |
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293 #ifdef _LP64 |
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294 __ vmovdqu(Address(rsi, 64), xmm8); |
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295 __ vmovdqu(Address(rsi, 96), xmm15); |
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296 #endif |
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297 |
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298 VM_Version::clean_cpuFeatures(); |
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299 UseAVX = saved_useavx; |
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300 UseSSE = saved_usesse; |
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301 |
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302 // |
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303 // cpuid(0x7) Structured Extended Features |
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304 // |
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305 __ bind(sef_cpuid); |
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306 __ movl(rax, 7); |
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307 __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x7) supported? |
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308 __ jccb(Assembler::greater, ext_cpuid); |
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309 |
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310 __ xorl(rcx, rcx); |
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311 __ cpuid(); |
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312 __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset()))); |
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313 __ movl(Address(rsi, 0), rax); |
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314 __ movl(Address(rsi, 4), rbx); |
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315 |
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316 // |
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317 // Extended cpuid(0x80000000) |
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318 // |
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319 __ bind(ext_cpuid); |
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320 __ movl(rax, 0x80000000); |
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321 __ cpuid(); |
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322 __ cmpl(rax, 0x80000000); // Is cpuid(0x80000001) supported? |
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323 __ jcc(Assembler::belowEqual, done); |
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324 __ cmpl(rax, 0x80000004); // Is cpuid(0x80000005) supported? |
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325 __ jccb(Assembler::belowEqual, ext_cpuid1); |
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326 __ cmpl(rax, 0x80000006); // Is cpuid(0x80000007) supported? |
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327 __ jccb(Assembler::belowEqual, ext_cpuid5); |
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328 __ cmpl(rax, 0x80000007); // Is cpuid(0x80000008) supported? |
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329 __ jccb(Assembler::belowEqual, ext_cpuid7); |
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330 // |
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331 // Extended cpuid(0x80000008) |
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332 // |
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333 __ movl(rax, 0x80000008); |
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334 __ cpuid(); |
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335 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset()))); |
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336 __ movl(Address(rsi, 0), rax); |
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337 __ movl(Address(rsi, 4), rbx); |
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338 __ movl(Address(rsi, 8), rcx); |
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339 __ movl(Address(rsi,12), rdx); |
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340 |
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341 // |
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342 // Extended cpuid(0x80000007) |
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343 // |
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344 __ bind(ext_cpuid7); |
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345 __ movl(rax, 0x80000007); |
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346 __ cpuid(); |
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347 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid7_offset()))); |
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348 __ movl(Address(rsi, 0), rax); |
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349 __ movl(Address(rsi, 4), rbx); |
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350 __ movl(Address(rsi, 8), rcx); |
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351 __ movl(Address(rsi,12), rdx); |
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352 |
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353 // |
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354 // Extended cpuid(0x80000005) |
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355 // |
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356 __ bind(ext_cpuid5); |
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357 __ movl(rax, 0x80000005); |
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358 __ cpuid(); |
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359 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset()))); |
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360 __ movl(Address(rsi, 0), rax); |
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361 __ movl(Address(rsi, 4), rbx); |
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362 __ movl(Address(rsi, 8), rcx); |
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363 __ movl(Address(rsi,12), rdx); |
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364 |
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365 // |
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366 // Extended cpuid(0x80000001) |
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367 // |
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368 __ bind(ext_cpuid1); |
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369 __ movl(rax, 0x80000001); |
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370 __ cpuid(); |
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371 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset()))); |
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372 __ movl(Address(rsi, 0), rax); |
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373 __ movl(Address(rsi, 4), rbx); |
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374 __ movl(Address(rsi, 8), rcx); |
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375 __ movl(Address(rsi,12), rdx); |
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376 |
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377 // |
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378 // return |
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379 // |
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380 __ bind(done); |
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381 __ popf(); |
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382 __ pop(rsi); |
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383 __ pop(rbx); |
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384 __ pop(rbp); |
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385 __ ret(0); |
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386 |
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387 # undef __ |
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388 |
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389 return start; |
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390 }; |
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391 }; |
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392 |
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393 |
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394 void VM_Version::get_cpu_info_wrapper() { |
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395 get_cpu_info_stub(&_cpuid_info); |
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396 } |
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397 |
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398 #ifndef CALL_TEST_FUNC_WITH_WRAPPER_IF_NEEDED |
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399 #define CALL_TEST_FUNC_WITH_WRAPPER_IF_NEEDED(f) f() |
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400 #endif |
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401 |
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402 void VM_Version::get_processor_features() { |
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403 |
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404 _cpu = 4; // 486 by default |
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405 _model = 0; |
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406 _stepping = 0; |
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407 _cpuFeatures = 0; |
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408 _logical_processors_per_package = 1; |
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409 |
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410 if (!Use486InstrsOnly) { |
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411 // Get raw processor info |
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412 |
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413 // Some platforms (like Win*) need a wrapper around here |
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414 // in order to properly handle SEGV for YMM registers test. |
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415 CALL_TEST_FUNC_WITH_WRAPPER_IF_NEEDED(get_cpu_info_wrapper); |
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416 |
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417 assert_is_initialized(); |
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418 _cpu = extended_cpu_family(); |
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419 _model = extended_cpu_model(); |
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420 _stepping = cpu_stepping(); |
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421 |
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422 if (cpu_family() > 4) { // it supports CPUID |
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423 _cpuFeatures = feature_flags(); |
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424 // Logical processors are only available on P4s and above, |
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425 // and only if hyperthreading is available. |
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426 _logical_processors_per_package = logical_processor_count(); |
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427 } |
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428 } |
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429 |
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430 _supports_cx8 = supports_cmpxchg8(); |
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431 // xchg and xadd instructions |
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432 _supports_atomic_getset4 = true; |
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433 _supports_atomic_getadd4 = true; |
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434 LP64_ONLY(_supports_atomic_getset8 = true); |
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435 LP64_ONLY(_supports_atomic_getadd8 = true); |
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436 |
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437 #ifdef _LP64 |
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438 // OS should support SSE for x64 and hardware should support at least SSE2. |
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439 if (!VM_Version::supports_sse2()) { |
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440 vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported"); |
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441 } |
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442 // in 64 bit the use of SSE2 is the minimum |
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443 if (UseSSE < 2) UseSSE = 2; |
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444 #endif |
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445 |
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446 #ifdef AMD64 |
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447 // flush_icache_stub have to be generated first. |
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448 // That is why Icache line size is hard coded in ICache class, |
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449 // see icache_x86.hpp. It is also the reason why we can't use |
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450 // clflush instruction in 32-bit VM since it could be running |
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451 // on CPU which does not support it. |
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452 // |
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453 // The only thing we can do is to verify that flushed |
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454 // ICache::line_size has correct value. |
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455 guarantee(_cpuid_info.std_cpuid1_edx.bits.clflush != 0, "clflush is not supported"); |
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456 // clflush_size is size in quadwords (8 bytes). |
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457 guarantee(_cpuid_info.std_cpuid1_ebx.bits.clflush_size == 8, "such clflush size is not supported"); |
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458 #endif |
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459 |
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460 // If the OS doesn't support SSE, we can't use this feature even if the HW does |
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461 if (!os::supports_sse()) |
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462 _cpuFeatures &= ~(CPU_SSE|CPU_SSE2|CPU_SSE3|CPU_SSSE3|CPU_SSE4A|CPU_SSE4_1|CPU_SSE4_2); |
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463 |
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464 if (UseSSE < 4) { |
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465 _cpuFeatures &= ~CPU_SSE4_1; |
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466 _cpuFeatures &= ~CPU_SSE4_2; |
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467 } |
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468 |
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469 if (UseSSE < 3) { |
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470 _cpuFeatures &= ~CPU_SSE3; |
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471 _cpuFeatures &= ~CPU_SSSE3; |
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472 _cpuFeatures &= ~CPU_SSE4A; |
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473 } |
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474 |
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475 if (UseSSE < 2) |
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476 _cpuFeatures &= ~CPU_SSE2; |
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477 |
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478 if (UseSSE < 1) |
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479 _cpuFeatures &= ~CPU_SSE; |
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480 |
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481 if (UseAVX < 2) |
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482 _cpuFeatures &= ~CPU_AVX2; |
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483 |
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484 if (UseAVX < 1) |
|
485 _cpuFeatures &= ~CPU_AVX; |
|
486 |
|
487 if (!UseAES && !FLAG_IS_DEFAULT(UseAES)) |
|
488 _cpuFeatures &= ~CPU_AES; |
|
489 |
|
490 if (logical_processors_per_package() == 1) { |
|
491 // HT processor could be installed on a system which doesn't support HT. |
|
492 _cpuFeatures &= ~CPU_HT; |
|
493 } |
|
494 |
|
495 char buf[256]; |
|
496 jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", |
|
497 cores_per_cpu(), threads_per_core(), |
|
498 cpu_family(), _model, _stepping, |
|
499 (supports_cmov() ? ", cmov" : ""), |
|
500 (supports_cmpxchg8() ? ", cx8" : ""), |
|
501 (supports_fxsr() ? ", fxsr" : ""), |
|
502 (supports_mmx() ? ", mmx" : ""), |
|
503 (supports_sse() ? ", sse" : ""), |
|
504 (supports_sse2() ? ", sse2" : ""), |
|
505 (supports_sse3() ? ", sse3" : ""), |
|
506 (supports_ssse3()? ", ssse3": ""), |
|
507 (supports_sse4_1() ? ", sse4.1" : ""), |
|
508 (supports_sse4_2() ? ", sse4.2" : ""), |
|
509 (supports_popcnt() ? ", popcnt" : ""), |
|
510 (supports_avx() ? ", avx" : ""), |
|
511 (supports_avx2() ? ", avx2" : ""), |
|
512 (supports_aes() ? ", aes" : ""), |
|
513 (supports_clmul() ? ", clmul" : ""), |
|
514 (supports_erms() ? ", erms" : ""), |
|
515 (supports_rtm() ? ", rtm" : ""), |
|
516 (supports_mmx_ext() ? ", mmxext" : ""), |
|
517 (supports_3dnow_prefetch() ? ", 3dnowpref" : ""), |
|
518 (supports_lzcnt() ? ", lzcnt": ""), |
|
519 (supports_sse4a() ? ", sse4a": ""), |
|
520 (supports_ht() ? ", ht": ""), |
|
521 (supports_tsc() ? ", tsc": ""), |
|
522 (supports_tscinv_bit() ? ", tscinvbit": ""), |
|
523 (supports_tscinv() ? ", tscinv": ""), |
|
524 (supports_bmi1() ? ", bmi1" : ""), |
|
525 (supports_bmi2() ? ", bmi2" : "")); |
|
526 _features_str = strdup(buf); |
|
527 |
|
528 // UseSSE is set to the smaller of what hardware supports and what |
|
529 // the command line requires. I.e., you cannot set UseSSE to 2 on |
|
530 // older Pentiums which do not support it. |
|
531 if (UseSSE > 4) UseSSE=4; |
|
532 if (UseSSE < 0) UseSSE=0; |
|
533 if (!supports_sse4_1()) // Drop to 3 if no SSE4 support |
|
534 UseSSE = MIN2((intx)3,UseSSE); |
|
535 if (!supports_sse3()) // Drop to 2 if no SSE3 support |
|
536 UseSSE = MIN2((intx)2,UseSSE); |
|
537 if (!supports_sse2()) // Drop to 1 if no SSE2 support |
|
538 UseSSE = MIN2((intx)1,UseSSE); |
|
539 if (!supports_sse ()) // Drop to 0 if no SSE support |
|
540 UseSSE = 0; |
|
541 |
|
542 if (UseAVX > 2) UseAVX=2; |
|
543 if (UseAVX < 0) UseAVX=0; |
|
544 if (!supports_avx2()) // Drop to 1 if no AVX2 support |
|
545 UseAVX = MIN2((intx)1,UseAVX); |
|
546 if (!supports_avx ()) // Drop to 0 if no AVX support |
|
547 UseAVX = 0; |
|
548 |
|
549 // Use AES instructions if available. |
|
550 if (supports_aes()) { |
|
551 if (FLAG_IS_DEFAULT(UseAES)) { |
|
552 UseAES = true; |
|
553 } |
|
554 } else if (UseAES) { |
|
555 if (!FLAG_IS_DEFAULT(UseAES)) |
|
556 warning("AES instructions are not available on this CPU"); |
|
557 FLAG_SET_DEFAULT(UseAES, false); |
|
558 } |
|
559 |
|
560 // Use CLMUL instructions if available. |
|
561 if (supports_clmul()) { |
|
562 if (FLAG_IS_DEFAULT(UseCLMUL)) { |
|
563 UseCLMUL = true; |
|
564 } |
|
565 } else if (UseCLMUL) { |
|
566 if (!FLAG_IS_DEFAULT(UseCLMUL)) |
|
567 warning("CLMUL instructions not available on this CPU (AVX may also be required)"); |
|
568 FLAG_SET_DEFAULT(UseCLMUL, false); |
|
569 } |
|
570 |
|
571 if (UseCLMUL && (UseAVX > 0) && (UseSSE > 2)) { |
|
572 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) { |
|
573 UseCRC32Intrinsics = true; |
|
574 } |
|
575 } else if (UseCRC32Intrinsics) { |
|
576 if (!FLAG_IS_DEFAULT(UseCRC32Intrinsics)) |
|
577 warning("CRC32 Intrinsics requires AVX and CLMUL instructions (not available on this CPU)"); |
|
578 FLAG_SET_DEFAULT(UseCRC32Intrinsics, false); |
|
579 } |
|
580 |
|
581 // The AES intrinsic stubs require AES instruction support (of course) |
|
582 // but also require sse3 mode for instructions it use. |
|
583 if (UseAES && (UseSSE > 2)) { |
|
584 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) { |
|
585 UseAESIntrinsics = true; |
|
586 } |
|
587 } else if (UseAESIntrinsics) { |
|
588 if (!FLAG_IS_DEFAULT(UseAESIntrinsics)) |
|
589 warning("AES intrinsics are not available on this CPU"); |
|
590 FLAG_SET_DEFAULT(UseAESIntrinsics, false); |
|
591 } |
|
592 |
|
593 // Adjust RTM (Restricted Transactional Memory) flags |
|
594 if (!supports_rtm() && UseRTMLocking) { |
|
595 // Can't continue because UseRTMLocking affects UseBiasedLocking flag |
|
596 // setting during arguments processing. See use_biased_locking(). |
|
597 // VM_Version_init() is executed after UseBiasedLocking is used |
|
598 // in Thread::allocate(). |
|
599 vm_exit_during_initialization("RTM instructions are not available on this CPU"); |
|
600 } |
|
601 |
|
602 #if INCLUDE_RTM_OPT |
|
603 if (UseRTMLocking) { |
|
604 if (!FLAG_IS_CMDLINE(UseRTMLocking)) { |
|
605 // RTM locking should be used only for applications with |
|
606 // high lock contention. For now we do not use it by default. |
|
607 vm_exit_during_initialization("UseRTMLocking flag should be only set on command line"); |
|
608 } |
|
609 if (!is_power_of_2(RTMTotalCountIncrRate)) { |
|
610 warning("RTMTotalCountIncrRate must be a power of 2, resetting it to 64"); |
|
611 FLAG_SET_DEFAULT(RTMTotalCountIncrRate, 64); |
|
612 } |
|
613 if (RTMAbortRatio < 0 || RTMAbortRatio > 100) { |
|
614 warning("RTMAbortRatio must be in the range 0 to 100, resetting it to 50"); |
|
615 FLAG_SET_DEFAULT(RTMAbortRatio, 50); |
|
616 } |
|
617 } else { // !UseRTMLocking |
|
618 if (UseRTMForStackLocks) { |
|
619 if (!FLAG_IS_DEFAULT(UseRTMForStackLocks)) { |
|
620 warning("UseRTMForStackLocks flag should be off when UseRTMLocking flag is off"); |
|
621 } |
|
622 FLAG_SET_DEFAULT(UseRTMForStackLocks, false); |
|
623 } |
|
624 if (UseRTMDeopt) { |
|
625 FLAG_SET_DEFAULT(UseRTMDeopt, false); |
|
626 } |
|
627 if (PrintPreciseRTMLockingStatistics) { |
|
628 FLAG_SET_DEFAULT(PrintPreciseRTMLockingStatistics, false); |
|
629 } |
|
630 } |
|
631 #else |
|
632 if (UseRTMLocking) { |
|
633 // Only C2 does RTM locking optimization. |
|
634 // Can't continue because UseRTMLocking affects UseBiasedLocking flag |
|
635 // setting during arguments processing. See use_biased_locking(). |
|
636 vm_exit_during_initialization("RTM locking optimization is not supported in this VM"); |
|
637 } |
|
638 #endif |
|
639 |
|
640 #ifdef COMPILER2 |
|
641 if (UseFPUForSpilling) { |
|
642 if (UseSSE < 2) { |
|
643 // Only supported with SSE2+ |
|
644 FLAG_SET_DEFAULT(UseFPUForSpilling, false); |
|
645 } |
|
646 } |
|
647 if (MaxVectorSize > 0) { |
|
648 if (!is_power_of_2(MaxVectorSize)) { |
|
649 warning("MaxVectorSize must be a power of 2"); |
|
650 FLAG_SET_DEFAULT(MaxVectorSize, 32); |
|
651 } |
|
652 if (MaxVectorSize > 32) { |
|
653 FLAG_SET_DEFAULT(MaxVectorSize, 32); |
|
654 } |
|
655 if (MaxVectorSize > 16 && (UseAVX == 0 || !os_supports_avx_vectors())) { |
|
656 // 32 bytes vectors (in YMM) are only supported with AVX+ |
|
657 FLAG_SET_DEFAULT(MaxVectorSize, 16); |
|
658 } |
|
659 if (UseSSE < 2) { |
|
660 // Vectors (in XMM) are only supported with SSE2+ |
|
661 FLAG_SET_DEFAULT(MaxVectorSize, 0); |
|
662 } |
|
663 #ifdef ASSERT |
|
664 if (supports_avx() && PrintMiscellaneous && Verbose && TraceNewVectors) { |
|
665 tty->print_cr("State of YMM registers after signal handle:"); |
|
666 int nreg = 2 LP64_ONLY(+2); |
|
667 const char* ymm_name[4] = {"0", "7", "8", "15"}; |
|
668 for (int i = 0; i < nreg; i++) { |
|
669 tty->print("YMM%s:", ymm_name[i]); |
|
670 for (int j = 7; j >=0; j--) { |
|
671 tty->print(" %x", _cpuid_info.ymm_save[i*8 + j]); |
|
672 } |
|
673 tty->cr(); |
|
674 } |
|
675 } |
|
676 #endif |
|
677 } |
|
678 #endif |
|
679 |
|
680 // On new cpus instructions which update whole XMM register should be used |
|
681 // to prevent partial register stall due to dependencies on high half. |
|
682 // |
|
683 // UseXmmLoadAndClearUpper == true --> movsd(xmm, mem) |
|
684 // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem) |
|
685 // UseXmmRegToRegMoveAll == true --> movaps(xmm, xmm), movapd(xmm, xmm). |
|
686 // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm), movsd(xmm, xmm). |
|
687 |
|
688 if( is_amd() ) { // AMD cpus specific settings |
|
689 if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) { |
|
690 // Use it on new AMD cpus starting from Opteron. |
|
691 UseAddressNop = true; |
|
692 } |
|
693 if( supports_sse2() && FLAG_IS_DEFAULT(UseNewLongLShift) ) { |
|
694 // Use it on new AMD cpus starting from Opteron. |
|
695 UseNewLongLShift = true; |
|
696 } |
|
697 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) { |
|
698 if( supports_sse4a() ) { |
|
699 UseXmmLoadAndClearUpper = true; // use movsd only on '10h' Opteron |
|
700 } else { |
|
701 UseXmmLoadAndClearUpper = false; |
|
702 } |
|
703 } |
|
704 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) { |
|
705 if( supports_sse4a() ) { |
|
706 UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h' |
|
707 } else { |
|
708 UseXmmRegToRegMoveAll = false; |
|
709 } |
|
710 } |
|
711 if( FLAG_IS_DEFAULT(UseXmmI2F) ) { |
|
712 if( supports_sse4a() ) { |
|
713 UseXmmI2F = true; |
|
714 } else { |
|
715 UseXmmI2F = false; |
|
716 } |
|
717 } |
|
718 if( FLAG_IS_DEFAULT(UseXmmI2D) ) { |
|
719 if( supports_sse4a() ) { |
|
720 UseXmmI2D = true; |
|
721 } else { |
|
722 UseXmmI2D = false; |
|
723 } |
|
724 } |
|
725 if( FLAG_IS_DEFAULT(UseSSE42Intrinsics) ) { |
|
726 if( supports_sse4_2() && UseSSE >= 4 ) { |
|
727 UseSSE42Intrinsics = true; |
|
728 } |
|
729 } |
|
730 |
|
731 // some defaults for AMD family 15h |
|
732 if ( cpu_family() == 0x15 ) { |
|
733 // On family 15h processors default is no sw prefetch |
|
734 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) { |
|
735 AllocatePrefetchStyle = 0; |
|
736 } |
|
737 // Also, if some other prefetch style is specified, default instruction type is PREFETCHW |
|
738 if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) { |
|
739 AllocatePrefetchInstr = 3; |
|
740 } |
|
741 // On family 15h processors use XMM and UnalignedLoadStores for Array Copy |
|
742 if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) { |
|
743 UseXMMForArrayCopy = true; |
|
744 } |
|
745 if (supports_sse2() && FLAG_IS_DEFAULT(UseUnalignedLoadStores)) { |
|
746 UseUnalignedLoadStores = true; |
|
747 } |
|
748 } |
|
749 |
|
750 #ifdef COMPILER2 |
|
751 if (MaxVectorSize > 16) { |
|
752 // Limit vectors size to 16 bytes on current AMD cpus. |
|
753 FLAG_SET_DEFAULT(MaxVectorSize, 16); |
|
754 } |
|
755 #endif // COMPILER2 |
|
756 } |
|
757 |
|
758 if( is_intel() ) { // Intel cpus specific settings |
|
759 if( FLAG_IS_DEFAULT(UseStoreImmI16) ) { |
|
760 UseStoreImmI16 = false; // don't use it on Intel cpus |
|
761 } |
|
762 if( cpu_family() == 6 || cpu_family() == 15 ) { |
|
763 if( FLAG_IS_DEFAULT(UseAddressNop) ) { |
|
764 // Use it on all Intel cpus starting from PentiumPro |
|
765 UseAddressNop = true; |
|
766 } |
|
767 } |
|
768 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) { |
|
769 UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus |
|
770 } |
|
771 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) { |
|
772 if( supports_sse3() ) { |
|
773 UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus |
|
774 } else { |
|
775 UseXmmRegToRegMoveAll = false; |
|
776 } |
|
777 } |
|
778 if( cpu_family() == 6 && supports_sse3() ) { // New Intel cpus |
|
779 #ifdef COMPILER2 |
|
780 if( FLAG_IS_DEFAULT(MaxLoopPad) ) { |
|
781 // For new Intel cpus do the next optimization: |
|
782 // don't align the beginning of a loop if there are enough instructions |
|
783 // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp) |
|
784 // in current fetch line (OptoLoopAlignment) or the padding |
|
785 // is big (> MaxLoopPad). |
|
786 // Set MaxLoopPad to 11 for new Intel cpus to reduce number of |
|
787 // generated NOP instructions. 11 is the largest size of one |
|
788 // address NOP instruction '0F 1F' (see Assembler::nop(i)). |
|
789 MaxLoopPad = 11; |
|
790 } |
|
791 #endif // COMPILER2 |
|
792 if (FLAG_IS_DEFAULT(UseXMMForArrayCopy)) { |
|
793 UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus |
|
794 } |
|
795 if (supports_sse4_2() && supports_ht()) { // Newest Intel cpus |
|
796 if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) { |
|
797 UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus |
|
798 } |
|
799 } |
|
800 if (supports_sse4_2() && UseSSE >= 4) { |
|
801 if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) { |
|
802 UseSSE42Intrinsics = true; |
|
803 } |
|
804 } |
|
805 } |
|
806 } |
|
807 |
|
808 // Use count leading zeros count instruction if available. |
|
809 if (supports_lzcnt()) { |
|
810 if (FLAG_IS_DEFAULT(UseCountLeadingZerosInstruction)) { |
|
811 UseCountLeadingZerosInstruction = true; |
|
812 } |
|
813 } else if (UseCountLeadingZerosInstruction) { |
|
814 warning("lzcnt instruction is not available on this CPU"); |
|
815 FLAG_SET_DEFAULT(UseCountLeadingZerosInstruction, false); |
|
816 } |
|
817 |
|
818 if (supports_bmi1()) { |
|
819 if (FLAG_IS_DEFAULT(UseBMI1Instructions)) { |
|
820 UseBMI1Instructions = true; |
|
821 } |
|
822 } else if (UseBMI1Instructions) { |
|
823 warning("BMI1 instructions are not available on this CPU"); |
|
824 FLAG_SET_DEFAULT(UseBMI1Instructions, false); |
|
825 } |
|
826 |
|
827 // Use count trailing zeros instruction if available |
|
828 if (supports_bmi1()) { |
|
829 if (FLAG_IS_DEFAULT(UseCountTrailingZerosInstruction)) { |
|
830 UseCountTrailingZerosInstruction = UseBMI1Instructions; |
|
831 } |
|
832 } else if (UseCountTrailingZerosInstruction) { |
|
833 warning("tzcnt instruction is not available on this CPU"); |
|
834 FLAG_SET_DEFAULT(UseCountTrailingZerosInstruction, false); |
|
835 } |
|
836 |
|
837 // Use population count instruction if available. |
|
838 if (supports_popcnt()) { |
|
839 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) { |
|
840 UsePopCountInstruction = true; |
|
841 } |
|
842 } else if (UsePopCountInstruction) { |
|
843 warning("POPCNT instruction is not available on this CPU"); |
|
844 FLAG_SET_DEFAULT(UsePopCountInstruction, false); |
|
845 } |
|
846 |
|
847 // Use fast-string operations if available. |
|
848 if (supports_erms()) { |
|
849 if (FLAG_IS_DEFAULT(UseFastStosb)) { |
|
850 UseFastStosb = true; |
|
851 } |
|
852 } else if (UseFastStosb) { |
|
853 warning("fast-string operations are not available on this CPU"); |
|
854 FLAG_SET_DEFAULT(UseFastStosb, false); |
|
855 } |
|
856 |
|
857 #ifdef COMPILER2 |
|
858 if (FLAG_IS_DEFAULT(AlignVector)) { |
|
859 // Modern processors allow misaligned memory operations for vectors. |
|
860 AlignVector = !UseUnalignedLoadStores; |
|
861 } |
|
862 #endif // COMPILER2 |
|
863 |
|
864 assert(0 <= ReadPrefetchInstr && ReadPrefetchInstr <= 3, "invalid value"); |
|
865 assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 3, "invalid value"); |
|
866 |
|
867 // set valid Prefetch instruction |
|
868 if( ReadPrefetchInstr < 0 ) ReadPrefetchInstr = 0; |
|
869 if( ReadPrefetchInstr > 3 ) ReadPrefetchInstr = 3; |
|
870 if( ReadPrefetchInstr == 3 && !supports_3dnow_prefetch() ) ReadPrefetchInstr = 0; |
|
871 if( !supports_sse() && supports_3dnow_prefetch() ) ReadPrefetchInstr = 3; |
|
872 |
|
873 if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0; |
|
874 if( AllocatePrefetchInstr > 3 ) AllocatePrefetchInstr = 3; |
|
875 if( AllocatePrefetchInstr == 3 && !supports_3dnow_prefetch() ) AllocatePrefetchInstr=0; |
|
876 if( !supports_sse() && supports_3dnow_prefetch() ) AllocatePrefetchInstr = 3; |
|
877 |
|
878 // Allocation prefetch settings |
|
879 intx cache_line_size = prefetch_data_size(); |
|
880 if( cache_line_size > AllocatePrefetchStepSize ) |
|
881 AllocatePrefetchStepSize = cache_line_size; |
|
882 |
|
883 assert(AllocatePrefetchLines > 0, "invalid value"); |
|
884 if( AllocatePrefetchLines < 1 ) // set valid value in product VM |
|
885 AllocatePrefetchLines = 3; |
|
886 assert(AllocateInstancePrefetchLines > 0, "invalid value"); |
|
887 if( AllocateInstancePrefetchLines < 1 ) // set valid value in product VM |
|
888 AllocateInstancePrefetchLines = 1; |
|
889 |
|
890 AllocatePrefetchDistance = allocate_prefetch_distance(); |
|
891 AllocatePrefetchStyle = allocate_prefetch_style(); |
|
892 |
|
893 if( is_intel() && cpu_family() == 6 && supports_sse3() ) { |
|
894 if( AllocatePrefetchStyle == 2 ) { // watermark prefetching on Core |
|
895 #ifdef _LP64 |
|
896 AllocatePrefetchDistance = 384; |
|
897 #else |
|
898 AllocatePrefetchDistance = 320; |
|
899 #endif |
|
900 } |
|
901 if( supports_sse4_2() && supports_ht() ) { // Nehalem based cpus |
|
902 AllocatePrefetchDistance = 192; |
|
903 AllocatePrefetchLines = 4; |
|
904 #ifdef COMPILER2 |
|
905 if (AggressiveOpts && FLAG_IS_DEFAULT(UseFPUForSpilling)) { |
|
906 FLAG_SET_DEFAULT(UseFPUForSpilling, true); |
|
907 } |
|
908 #endif |
|
909 } |
|
910 } |
|
911 assert(AllocatePrefetchDistance % AllocatePrefetchStepSize == 0, "invalid value"); |
|
912 |
|
913 #ifdef _LP64 |
|
914 // Prefetch settings |
|
915 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes(); |
|
916 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes(); |
|
917 PrefetchFieldsAhead = prefetch_fields_ahead(); |
|
918 #endif |
|
919 |
|
920 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) && |
|
921 (cache_line_size > ContendedPaddingWidth)) |
|
922 ContendedPaddingWidth = cache_line_size; |
|
923 |
|
924 #ifndef PRODUCT |
|
925 if (PrintMiscellaneous && Verbose) { |
|
926 tty->print_cr("Logical CPUs per core: %u", |
|
927 logical_processors_per_package()); |
|
928 tty->print("UseSSE=%d", (int) UseSSE); |
|
929 if (UseAVX > 0) { |
|
930 tty->print(" UseAVX=%d", (int) UseAVX); |
|
931 } |
|
932 if (UseAES) { |
|
933 tty->print(" UseAES=1"); |
|
934 } |
|
935 #ifdef COMPILER2 |
|
936 if (MaxVectorSize > 0) { |
|
937 tty->print(" MaxVectorSize=%d", (int) MaxVectorSize); |
|
938 } |
|
939 #endif |
|
940 tty->cr(); |
|
941 tty->print("Allocation"); |
|
942 if (AllocatePrefetchStyle <= 0 || UseSSE == 0 && !supports_3dnow_prefetch()) { |
|
943 tty->print_cr(": no prefetching"); |
|
944 } else { |
|
945 tty->print(" prefetching: "); |
|
946 if (UseSSE == 0 && supports_3dnow_prefetch()) { |
|
947 tty->print("PREFETCHW"); |
|
948 } else if (UseSSE >= 1) { |
|
949 if (AllocatePrefetchInstr == 0) { |
|
950 tty->print("PREFETCHNTA"); |
|
951 } else if (AllocatePrefetchInstr == 1) { |
|
952 tty->print("PREFETCHT0"); |
|
953 } else if (AllocatePrefetchInstr == 2) { |
|
954 tty->print("PREFETCHT2"); |
|
955 } else if (AllocatePrefetchInstr == 3) { |
|
956 tty->print("PREFETCHW"); |
|
957 } |
|
958 } |
|
959 if (AllocatePrefetchLines > 1) { |
|
960 tty->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize); |
|
961 } else { |
|
962 tty->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize); |
|
963 } |
|
964 } |
|
965 |
|
966 if (PrefetchCopyIntervalInBytes > 0) { |
|
967 tty->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes); |
|
968 } |
|
969 if (PrefetchScanIntervalInBytes > 0) { |
|
970 tty->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes); |
|
971 } |
|
972 if (PrefetchFieldsAhead > 0) { |
|
973 tty->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead); |
|
974 } |
|
975 if (ContendedPaddingWidth > 0) { |
|
976 tty->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth); |
|
977 } |
|
978 } |
|
979 #endif // !PRODUCT |
|
980 } |
|
981 |
|
982 bool VM_Version::use_biased_locking() { |
|
983 #if INCLUDE_RTM_OPT |
|
984 // RTM locking is most useful when there is high lock contention and |
|
985 // low data contention. With high lock contention the lock is usually |
|
986 // inflated and biased locking is not suitable for that case. |
|
987 // RTM locking code requires that biased locking is off. |
|
988 // Note: we can't switch off UseBiasedLocking in get_processor_features() |
|
989 // because it is used by Thread::allocate() which is called before |
|
990 // VM_Version::initialize(). |
|
991 if (UseRTMLocking && UseBiasedLocking) { |
|
992 if (FLAG_IS_DEFAULT(UseBiasedLocking)) { |
|
993 FLAG_SET_DEFAULT(UseBiasedLocking, false); |
|
994 } else { |
|
995 warning("Biased locking is not supported with RTM locking; ignoring UseBiasedLocking flag." ); |
|
996 UseBiasedLocking = false; |
|
997 } |
|
998 } |
|
999 #endif |
|
1000 return UseBiasedLocking; |
|
1001 } |
|
1002 |
|
1003 void VM_Version::initialize() { |
|
1004 ResourceMark rm; |
|
1005 // Making this stub must be FIRST use of assembler |
|
1006 |
|
1007 stub_blob = BufferBlob::create("get_cpu_info_stub", stub_size); |
|
1008 if (stub_blob == NULL) { |
|
1009 vm_exit_during_initialization("Unable to allocate get_cpu_info_stub"); |
|
1010 } |
|
1011 CodeBuffer c(stub_blob); |
|
1012 VM_Version_StubGenerator g(&c); |
|
1013 get_cpu_info_stub = CAST_TO_FN_PTR(get_cpu_info_stub_t, |
|
1014 g.generate_get_cpu_info()); |
|
1015 |
|
1016 get_processor_features(); |
|
1017 } |