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1 /* |
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2 * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved. |
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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4 * |
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5 * This code is free software; you can redistribute it and/or modify it |
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6 * under the terms of the GNU General Public License version 2 only, as |
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7 * published by the Free Software Foundation. |
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8 * |
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9 * This code is distributed in the hope that it will be useful, but WITHOUT |
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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12 * version 2 for more details (a copy is included in the LICENSE file that |
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13 * accompanied this code). |
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14 * |
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15 * You should have received a copy of the GNU General Public License version |
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16 * 2 along with this work; if not, write to the Free Software Foundation, |
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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18 * |
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
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22 * |
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23 */ |
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24 |
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25 #ifndef CPU_X86_VM_NATIVEINST_X86_HPP |
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26 #define CPU_X86_VM_NATIVEINST_X86_HPP |
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27 |
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28 #include "asm/assembler.hpp" |
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29 #include "memory/allocation.hpp" |
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30 #include "runtime/icache.hpp" |
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31 #include "runtime/os.hpp" |
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32 #include "utilities/top.hpp" |
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33 |
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34 // We have interfaces for the following instructions: |
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35 // - NativeInstruction |
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36 // - - NativeCall |
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37 // - - NativeMovConstReg |
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38 // - - NativeMovConstRegPatching |
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39 // - - NativeMovRegMem |
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40 // - - NativeMovRegMemPatching |
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41 // - - NativeJump |
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42 // - - NativeIllegalOpCode |
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43 // - - NativeGeneralJump |
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44 // - - NativeReturn |
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45 // - - NativeReturnX (return with argument) |
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46 // - - NativePushConst |
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47 // - - NativeTstRegMem |
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48 |
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49 // The base class for different kinds of native instruction abstractions. |
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50 // Provides the primitive operations to manipulate code relative to this. |
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51 |
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52 class NativeInstruction VALUE_OBJ_CLASS_SPEC { |
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53 friend class Relocation; |
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54 |
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55 public: |
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56 enum Intel_specific_constants { |
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57 nop_instruction_code = 0x90, |
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58 nop_instruction_size = 1 |
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59 }; |
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60 |
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61 bool is_nop() { return ubyte_at(0) == nop_instruction_code; } |
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62 bool is_dtrace_trap(); |
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63 inline bool is_call(); |
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64 inline bool is_illegal(); |
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65 inline bool is_return(); |
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66 inline bool is_jump(); |
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67 inline bool is_cond_jump(); |
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68 inline bool is_safepoint_poll(); |
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69 inline bool is_mov_literal64(); |
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70 |
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71 protected: |
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72 address addr_at(int offset) const { return address(this) + offset; } |
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73 |
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74 s_char sbyte_at(int offset) const { return *(s_char*) addr_at(offset); } |
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75 u_char ubyte_at(int offset) const { return *(u_char*) addr_at(offset); } |
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76 |
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77 jint int_at(int offset) const { return *(jint*) addr_at(offset); } |
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78 |
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79 intptr_t ptr_at(int offset) const { return *(intptr_t*) addr_at(offset); } |
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80 |
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81 oop oop_at (int offset) const { return *(oop*) addr_at(offset); } |
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82 |
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83 |
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84 void set_char_at(int offset, char c) { *addr_at(offset) = (u_char)c; wrote(offset); } |
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85 void set_int_at(int offset, jint i) { *(jint*)addr_at(offset) = i; wrote(offset); } |
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86 void set_ptr_at (int offset, intptr_t ptr) { *(intptr_t*) addr_at(offset) = ptr; wrote(offset); } |
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87 void set_oop_at (int offset, oop o) { *(oop*) addr_at(offset) = o; wrote(offset); } |
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88 |
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89 // This doesn't really do anything on Intel, but it is the place where |
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90 // cache invalidation belongs, generically: |
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91 void wrote(int offset); |
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92 |
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93 public: |
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94 |
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95 // unit test stuff |
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96 static void test() {} // override for testing |
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97 |
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98 inline friend NativeInstruction* nativeInstruction_at(address address); |
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99 }; |
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100 |
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101 inline NativeInstruction* nativeInstruction_at(address address) { |
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102 NativeInstruction* inst = (NativeInstruction*)address; |
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103 #ifdef ASSERT |
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104 //inst->verify(); |
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105 #endif |
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106 return inst; |
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107 } |
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108 |
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109 inline NativeCall* nativeCall_at(address address); |
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110 // The NativeCall is an abstraction for accessing/manipulating native call imm32/rel32off |
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111 // instructions (used to manipulate inline caches, primitive & dll calls, etc.). |
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112 |
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113 class NativeCall: public NativeInstruction { |
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114 public: |
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115 enum Intel_specific_constants { |
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116 instruction_code = 0xE8, |
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117 instruction_size = 5, |
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118 instruction_offset = 0, |
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119 displacement_offset = 1, |
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120 return_address_offset = 5 |
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121 }; |
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122 |
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123 enum { cache_line_size = BytesPerWord }; // conservative estimate! |
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124 |
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125 address instruction_address() const { return addr_at(instruction_offset); } |
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126 address next_instruction_address() const { return addr_at(return_address_offset); } |
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127 int displacement() const { return (jint) int_at(displacement_offset); } |
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128 address displacement_address() const { return addr_at(displacement_offset); } |
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129 address return_address() const { return addr_at(return_address_offset); } |
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130 address destination() const; |
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131 void set_destination(address dest) { |
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132 #ifdef AMD64 |
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133 assert((labs((intptr_t) dest - (intptr_t) return_address()) & |
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134 0xFFFFFFFF00000000) == 0, |
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135 "must be 32bit offset"); |
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136 #endif // AMD64 |
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137 set_int_at(displacement_offset, dest - return_address()); |
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138 } |
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139 void set_destination_mt_safe(address dest); |
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140 |
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141 void verify_alignment() { assert((intptr_t)addr_at(displacement_offset) % BytesPerInt == 0, "must be aligned"); } |
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142 void verify(); |
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143 void print(); |
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144 |
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145 // Creation |
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146 inline friend NativeCall* nativeCall_at(address address); |
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147 inline friend NativeCall* nativeCall_before(address return_address); |
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148 |
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149 static bool is_call_at(address instr) { |
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150 return ((*instr) & 0xFF) == NativeCall::instruction_code; |
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151 } |
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152 |
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153 static bool is_call_before(address return_address) { |
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154 return is_call_at(return_address - NativeCall::return_address_offset); |
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155 } |
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156 |
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157 static bool is_call_to(address instr, address target) { |
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158 return nativeInstruction_at(instr)->is_call() && |
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159 nativeCall_at(instr)->destination() == target; |
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160 } |
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161 |
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162 // MT-safe patching of a call instruction. |
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163 static void insert(address code_pos, address entry); |
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164 |
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165 static void replace_mt_safe(address instr_addr, address code_buffer); |
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166 }; |
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167 |
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168 inline NativeCall* nativeCall_at(address address) { |
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169 NativeCall* call = (NativeCall*)(address - NativeCall::instruction_offset); |
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170 #ifdef ASSERT |
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171 call->verify(); |
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172 #endif |
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173 return call; |
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174 } |
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175 |
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176 inline NativeCall* nativeCall_before(address return_address) { |
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177 NativeCall* call = (NativeCall*)(return_address - NativeCall::return_address_offset); |
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178 #ifdef ASSERT |
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179 call->verify(); |
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180 #endif |
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181 return call; |
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182 } |
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183 |
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184 // An interface for accessing/manipulating native mov reg, imm32 instructions. |
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185 // (used to manipulate inlined 32bit data dll calls, etc.) |
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186 class NativeMovConstReg: public NativeInstruction { |
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187 #ifdef AMD64 |
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188 static const bool has_rex = true; |
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189 static const int rex_size = 1; |
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190 #else |
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191 static const bool has_rex = false; |
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192 static const int rex_size = 0; |
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193 #endif // AMD64 |
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194 public: |
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195 enum Intel_specific_constants { |
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196 instruction_code = 0xB8, |
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197 instruction_size = 1 + rex_size + wordSize, |
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198 instruction_offset = 0, |
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199 data_offset = 1 + rex_size, |
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200 next_instruction_offset = instruction_size, |
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201 register_mask = 0x07 |
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202 }; |
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203 |
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204 address instruction_address() const { return addr_at(instruction_offset); } |
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205 address next_instruction_address() const { return addr_at(next_instruction_offset); } |
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206 intptr_t data() const { return ptr_at(data_offset); } |
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207 void set_data(intptr_t x) { set_ptr_at(data_offset, x); } |
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208 |
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209 void verify(); |
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210 void print(); |
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211 |
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212 // unit test stuff |
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213 static void test() {} |
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214 |
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215 // Creation |
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216 inline friend NativeMovConstReg* nativeMovConstReg_at(address address); |
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217 inline friend NativeMovConstReg* nativeMovConstReg_before(address address); |
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218 }; |
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219 |
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220 inline NativeMovConstReg* nativeMovConstReg_at(address address) { |
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221 NativeMovConstReg* test = (NativeMovConstReg*)(address - NativeMovConstReg::instruction_offset); |
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222 #ifdef ASSERT |
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223 test->verify(); |
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224 #endif |
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225 return test; |
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226 } |
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227 |
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228 inline NativeMovConstReg* nativeMovConstReg_before(address address) { |
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229 NativeMovConstReg* test = (NativeMovConstReg*)(address - NativeMovConstReg::instruction_size - NativeMovConstReg::instruction_offset); |
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230 #ifdef ASSERT |
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231 test->verify(); |
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232 #endif |
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233 return test; |
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234 } |
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235 |
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236 class NativeMovConstRegPatching: public NativeMovConstReg { |
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237 private: |
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238 friend NativeMovConstRegPatching* nativeMovConstRegPatching_at(address address) { |
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239 NativeMovConstRegPatching* test = (NativeMovConstRegPatching*)(address - instruction_offset); |
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240 #ifdef ASSERT |
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241 test->verify(); |
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242 #endif |
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243 return test; |
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244 } |
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245 }; |
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246 |
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247 // An interface for accessing/manipulating native moves of the form: |
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248 // mov[b/w/l/q] [reg + offset], reg (instruction_code_reg2mem) |
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249 // mov[b/w/l/q] reg, [reg+offset] (instruction_code_mem2reg |
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250 // mov[s/z]x[w/b/q] [reg + offset], reg |
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251 // fld_s [reg+offset] |
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252 // fld_d [reg+offset] |
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253 // fstp_s [reg + offset] |
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254 // fstp_d [reg + offset] |
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255 // mov_literal64 scratch,<pointer> ; mov[b/w/l/q] 0(scratch),reg | mov[b/w/l/q] reg,0(scratch) |
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256 // |
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257 // Warning: These routines must be able to handle any instruction sequences |
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258 // that are generated as a result of the load/store byte,word,long |
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259 // macros. For example: The load_unsigned_byte instruction generates |
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260 // an xor reg,reg inst prior to generating the movb instruction. This |
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261 // class must skip the xor instruction. |
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262 |
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263 class NativeMovRegMem: public NativeInstruction { |
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264 public: |
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265 enum Intel_specific_constants { |
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266 instruction_prefix_wide_lo = Assembler::REX, |
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267 instruction_prefix_wide_hi = Assembler::REX_WRXB, |
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268 instruction_code_xor = 0x33, |
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269 instruction_extended_prefix = 0x0F, |
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270 instruction_code_mem2reg_movslq = 0x63, |
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271 instruction_code_mem2reg_movzxb = 0xB6, |
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272 instruction_code_mem2reg_movsxb = 0xBE, |
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273 instruction_code_mem2reg_movzxw = 0xB7, |
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274 instruction_code_mem2reg_movsxw = 0xBF, |
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275 instruction_operandsize_prefix = 0x66, |
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276 instruction_code_reg2mem = 0x89, |
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277 instruction_code_mem2reg = 0x8b, |
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278 instruction_code_reg2memb = 0x88, |
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279 instruction_code_mem2regb = 0x8a, |
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280 instruction_code_float_s = 0xd9, |
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281 instruction_code_float_d = 0xdd, |
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282 instruction_code_long_volatile = 0xdf, |
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283 instruction_code_xmm_ss_prefix = 0xf3, |
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284 instruction_code_xmm_sd_prefix = 0xf2, |
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285 instruction_code_xmm_code = 0x0f, |
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286 instruction_code_xmm_load = 0x10, |
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287 instruction_code_xmm_store = 0x11, |
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288 instruction_code_xmm_lpd = 0x12, |
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289 |
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290 instruction_VEX_prefix_2bytes = Assembler::VEX_2bytes, |
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291 instruction_VEX_prefix_3bytes = Assembler::VEX_3bytes, |
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292 |
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293 instruction_size = 4, |
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294 instruction_offset = 0, |
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295 data_offset = 2, |
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296 next_instruction_offset = 4 |
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297 }; |
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298 |
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299 // helper |
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300 int instruction_start() const; |
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301 |
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302 address instruction_address() const; |
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303 |
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304 address next_instruction_address() const; |
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305 |
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306 int offset() const; |
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307 |
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308 void set_offset(int x); |
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309 |
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310 void add_offset_in_bytes(int add_offset) { set_offset ( ( offset() + add_offset ) ); } |
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311 |
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312 void verify(); |
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313 void print (); |
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314 |
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315 // unit test stuff |
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316 static void test() {} |
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317 |
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318 private: |
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319 inline friend NativeMovRegMem* nativeMovRegMem_at (address address); |
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320 }; |
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321 |
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322 inline NativeMovRegMem* nativeMovRegMem_at (address address) { |
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323 NativeMovRegMem* test = (NativeMovRegMem*)(address - NativeMovRegMem::instruction_offset); |
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324 #ifdef ASSERT |
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325 test->verify(); |
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326 #endif |
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327 return test; |
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328 } |
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329 |
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330 class NativeMovRegMemPatching: public NativeMovRegMem { |
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331 private: |
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332 friend NativeMovRegMemPatching* nativeMovRegMemPatching_at (address address) { |
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333 NativeMovRegMemPatching* test = (NativeMovRegMemPatching*)(address - instruction_offset); |
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334 #ifdef ASSERT |
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335 test->verify(); |
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336 #endif |
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337 return test; |
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338 } |
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339 }; |
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340 |
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341 |
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342 |
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343 // An interface for accessing/manipulating native leal instruction of form: |
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344 // leal reg, [reg + offset] |
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345 |
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346 class NativeLoadAddress: public NativeMovRegMem { |
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347 #ifdef AMD64 |
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348 static const bool has_rex = true; |
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349 static const int rex_size = 1; |
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350 #else |
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351 static const bool has_rex = false; |
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352 static const int rex_size = 0; |
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353 #endif // AMD64 |
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354 public: |
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355 enum Intel_specific_constants { |
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356 instruction_prefix_wide = Assembler::REX_W, |
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357 instruction_prefix_wide_extended = Assembler::REX_WB, |
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358 lea_instruction_code = 0x8D, |
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359 mov64_instruction_code = 0xB8 |
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360 }; |
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361 |
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362 void verify(); |
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363 void print (); |
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364 |
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365 // unit test stuff |
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366 static void test() {} |
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367 |
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368 private: |
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369 friend NativeLoadAddress* nativeLoadAddress_at (address address) { |
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370 NativeLoadAddress* test = (NativeLoadAddress*)(address - instruction_offset); |
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371 #ifdef ASSERT |
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372 test->verify(); |
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373 #endif |
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374 return test; |
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375 } |
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376 }; |
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377 |
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378 // jump rel32off |
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379 |
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380 class NativeJump: public NativeInstruction { |
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381 public: |
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382 enum Intel_specific_constants { |
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383 instruction_code = 0xe9, |
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384 instruction_size = 5, |
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385 instruction_offset = 0, |
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386 data_offset = 1, |
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387 next_instruction_offset = 5 |
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388 }; |
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389 |
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390 address instruction_address() const { return addr_at(instruction_offset); } |
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391 address next_instruction_address() const { return addr_at(next_instruction_offset); } |
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392 address jump_destination() const { |
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393 address dest = (int_at(data_offset)+next_instruction_address()); |
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394 // 32bit used to encode unresolved jmp as jmp -1 |
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395 // 64bit can't produce this so it used jump to self. |
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396 // Now 32bit and 64bit use jump to self as the unresolved address |
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397 // which the inline cache code (and relocs) know about |
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398 |
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399 // return -1 if jump to self |
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400 dest = (dest == (address) this) ? (address) -1 : dest; |
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401 return dest; |
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402 } |
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403 |
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404 void set_jump_destination(address dest) { |
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405 intptr_t val = dest - next_instruction_address(); |
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406 if (dest == (address) -1) { |
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407 val = -5; // jump to self |
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408 } |
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409 #ifdef AMD64 |
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410 assert((labs(val) & 0xFFFFFFFF00000000) == 0 || dest == (address)-1, "must be 32bit offset or -1"); |
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411 #endif // AMD64 |
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412 set_int_at(data_offset, (jint)val); |
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413 } |
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414 |
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415 // Creation |
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416 inline friend NativeJump* nativeJump_at(address address); |
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417 |
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418 void verify(); |
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419 |
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420 // Unit testing stuff |
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421 static void test() {} |
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422 |
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423 // Insertion of native jump instruction |
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424 static void insert(address code_pos, address entry); |
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425 // MT-safe insertion of native jump at verified method entry |
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426 static void check_verified_entry_alignment(address entry, address verified_entry); |
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427 static void patch_verified_entry(address entry, address verified_entry, address dest); |
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428 }; |
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429 |
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430 inline NativeJump* nativeJump_at(address address) { |
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431 NativeJump* jump = (NativeJump*)(address - NativeJump::instruction_offset); |
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432 #ifdef ASSERT |
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433 jump->verify(); |
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434 #endif |
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435 return jump; |
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436 } |
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437 |
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438 // Handles all kinds of jump on Intel. Long/far, conditional/unconditional |
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439 class NativeGeneralJump: public NativeInstruction { |
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440 public: |
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441 enum Intel_specific_constants { |
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442 // Constants does not apply, since the lengths and offsets depends on the actual jump |
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443 // used |
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444 // Instruction codes: |
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445 // Unconditional jumps: 0xE9 (rel32off), 0xEB (rel8off) |
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446 // Conditional jumps: 0x0F8x (rel32off), 0x7x (rel8off) |
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447 unconditional_long_jump = 0xe9, |
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448 unconditional_short_jump = 0xeb, |
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449 instruction_size = 5 |
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450 }; |
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451 |
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452 address instruction_address() const { return addr_at(0); } |
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453 address jump_destination() const; |
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454 |
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455 // Creation |
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456 inline friend NativeGeneralJump* nativeGeneralJump_at(address address); |
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457 |
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458 // Insertion of native general jump instruction |
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459 static void insert_unconditional(address code_pos, address entry); |
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460 static void replace_mt_safe(address instr_addr, address code_buffer); |
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461 |
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462 void verify(); |
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463 }; |
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464 |
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465 inline NativeGeneralJump* nativeGeneralJump_at(address address) { |
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466 NativeGeneralJump* jump = (NativeGeneralJump*)(address); |
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467 debug_only(jump->verify();) |
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468 return jump; |
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469 } |
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470 |
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471 class NativePopReg : public NativeInstruction { |
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472 public: |
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473 enum Intel_specific_constants { |
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474 instruction_code = 0x58, |
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475 instruction_size = 1, |
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476 instruction_offset = 0, |
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477 data_offset = 1, |
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478 next_instruction_offset = 1 |
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479 }; |
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480 |
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481 // Insert a pop instruction |
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482 static void insert(address code_pos, Register reg); |
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483 }; |
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484 |
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485 |
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486 class NativeIllegalInstruction: public NativeInstruction { |
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487 public: |
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488 enum Intel_specific_constants { |
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489 instruction_code = 0x0B0F, // Real byte order is: 0x0F, 0x0B |
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490 instruction_size = 2, |
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491 instruction_offset = 0, |
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492 next_instruction_offset = 2 |
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493 }; |
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494 |
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495 // Insert illegal opcode as specific address |
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496 static void insert(address code_pos); |
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497 }; |
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498 |
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499 // return instruction that does not pop values of the stack |
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500 class NativeReturn: public NativeInstruction { |
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501 public: |
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502 enum Intel_specific_constants { |
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503 instruction_code = 0xC3, |
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504 instruction_size = 1, |
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505 instruction_offset = 0, |
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506 next_instruction_offset = 1 |
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507 }; |
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508 }; |
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509 |
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510 // return instruction that does pop values of the stack |
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511 class NativeReturnX: public NativeInstruction { |
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512 public: |
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513 enum Intel_specific_constants { |
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514 instruction_code = 0xC2, |
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515 instruction_size = 2, |
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516 instruction_offset = 0, |
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517 next_instruction_offset = 2 |
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518 }; |
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519 }; |
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520 |
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521 // Simple test vs memory |
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522 class NativeTstRegMem: public NativeInstruction { |
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523 public: |
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524 enum Intel_specific_constants { |
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525 instruction_rex_prefix_mask = 0xF0, |
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526 instruction_rex_prefix = Assembler::REX, |
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527 instruction_code_memXregl = 0x85, |
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528 modrm_mask = 0x38, // select reg from the ModRM byte |
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529 modrm_reg = 0x00 // rax |
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530 }; |
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531 }; |
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532 |
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533 inline bool NativeInstruction::is_illegal() { return (short)int_at(0) == (short)NativeIllegalInstruction::instruction_code; } |
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534 inline bool NativeInstruction::is_call() { return ubyte_at(0) == NativeCall::instruction_code; } |
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535 inline bool NativeInstruction::is_return() { return ubyte_at(0) == NativeReturn::instruction_code || |
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536 ubyte_at(0) == NativeReturnX::instruction_code; } |
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537 inline bool NativeInstruction::is_jump() { return ubyte_at(0) == NativeJump::instruction_code || |
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538 ubyte_at(0) == 0xEB; /* short jump */ } |
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539 inline bool NativeInstruction::is_cond_jump() { return (int_at(0) & 0xF0FF) == 0x800F /* long jump */ || |
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540 (ubyte_at(0) & 0xF0) == 0x70; /* short jump */ } |
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541 inline bool NativeInstruction::is_safepoint_poll() { |
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542 #ifdef AMD64 |
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543 if (Assembler::is_polling_page_far()) { |
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544 // two cases, depending on the choice of the base register in the address. |
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545 if (((ubyte_at(0) & NativeTstRegMem::instruction_rex_prefix_mask) == NativeTstRegMem::instruction_rex_prefix && |
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546 ubyte_at(1) == NativeTstRegMem::instruction_code_memXregl && |
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547 (ubyte_at(2) & NativeTstRegMem::modrm_mask) == NativeTstRegMem::modrm_reg) || |
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548 ubyte_at(0) == NativeTstRegMem::instruction_code_memXregl && |
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549 (ubyte_at(1) & NativeTstRegMem::modrm_mask) == NativeTstRegMem::modrm_reg) { |
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550 return true; |
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551 } else { |
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552 return false; |
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553 } |
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554 } else { |
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555 if (ubyte_at(0) == NativeTstRegMem::instruction_code_memXregl && |
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556 ubyte_at(1) == 0x05) { // 00 rax 101 |
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557 address fault = addr_at(6) + int_at(2); |
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558 return os::is_poll_address(fault); |
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559 } else { |
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560 return false; |
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561 } |
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562 } |
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563 #else |
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564 return ( ubyte_at(0) == NativeMovRegMem::instruction_code_mem2reg || |
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565 ubyte_at(0) == NativeTstRegMem::instruction_code_memXregl ) && |
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566 (ubyte_at(1)&0xC7) == 0x05 && /* Mod R/M == disp32 */ |
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567 (os::is_poll_address((address)int_at(2))); |
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568 #endif // AMD64 |
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569 } |
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570 |
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571 inline bool NativeInstruction::is_mov_literal64() { |
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572 #ifdef AMD64 |
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573 return ((ubyte_at(0) == Assembler::REX_W || ubyte_at(0) == Assembler::REX_WB) && |
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574 (ubyte_at(1) & (0xff ^ NativeMovConstReg::register_mask)) == 0xB8); |
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575 #else |
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576 return false; |
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577 #endif // AMD64 |
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578 } |
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579 |
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580 #endif // CPU_X86_VM_NATIVEINST_X86_HPP |