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1 /* |
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2 * Copyright (c) 2005, 2014, Oracle and/or its affiliates. All rights reserved. |
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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4 * |
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5 * This code is free software; you can redistribute it and/or modify it |
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6 * under the terms of the GNU General Public License version 2 only, as |
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7 * published by the Free Software Foundation. |
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8 * |
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9 * This code is distributed in the hope that it will be useful, but WITHOUT |
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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12 * version 2 for more details (a copy is included in the LICENSE file that |
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13 * accompanied this code). |
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14 * |
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15 * You should have received a copy of the GNU General Public License version |
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16 * 2 along with this work; if not, write to the Free Software Foundation, |
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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18 * |
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
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22 * |
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23 */ |
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24 |
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25 #include "precompiled.hpp" |
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26 #include "c1/c1_Instruction.hpp" |
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27 #include "c1/c1_LinearScan.hpp" |
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28 #include "utilities/bitMap.inline.hpp" |
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29 |
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30 |
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31 //---------------------------------------------------------------------- |
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32 // Allocation of FPU stack slots (Intel x86 only) |
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33 //---------------------------------------------------------------------- |
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34 |
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35 void LinearScan::allocate_fpu_stack() { |
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36 // First compute which FPU registers are live at the start of each basic block |
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37 // (To minimize the amount of work we have to do if we have to merge FPU stacks) |
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38 if (ComputeExactFPURegisterUsage) { |
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39 Interval* intervals_in_register, *intervals_in_memory; |
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40 create_unhandled_lists(&intervals_in_register, &intervals_in_memory, is_in_fpu_register, NULL); |
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41 |
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42 // ignore memory intervals by overwriting intervals_in_memory |
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43 // the dummy interval is needed to enforce the walker to walk until the given id: |
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44 // without it, the walker stops when the unhandled-list is empty -> live information |
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45 // beyond this point would be incorrect. |
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46 Interval* dummy_interval = new Interval(any_reg); |
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47 dummy_interval->add_range(max_jint - 2, max_jint - 1); |
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48 dummy_interval->set_next(Interval::end()); |
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49 intervals_in_memory = dummy_interval; |
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50 |
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51 IntervalWalker iw(this, intervals_in_register, intervals_in_memory); |
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52 |
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53 const int num_blocks = block_count(); |
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54 for (int i = 0; i < num_blocks; i++) { |
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55 BlockBegin* b = block_at(i); |
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56 |
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57 // register usage is only needed for merging stacks -> compute only |
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58 // when more than one predecessor. |
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59 // the block must not have any spill moves at the beginning (checked by assertions) |
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60 // spill moves would use intervals that are marked as handled and so the usage bit |
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61 // would been set incorrectly |
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62 |
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63 // NOTE: the check for number_of_preds > 1 is necessary. A block with only one |
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64 // predecessor may have spill moves at the begin of the block. |
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65 // If an interval ends at the current instruction id, it is not possible |
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66 // to decide if the register is live or not at the block begin -> the |
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67 // register information would be incorrect. |
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68 if (b->number_of_preds() > 1) { |
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69 int id = b->first_lir_instruction_id(); |
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70 BitMap regs(FrameMap::nof_fpu_regs); |
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71 regs.clear(); |
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72 |
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73 iw.walk_to(id); // walk after the first instruction (always a label) of the block |
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74 assert(iw.current_position() == id, "did not walk completely to id"); |
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75 |
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76 // Only consider FPU values in registers |
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77 Interval* interval = iw.active_first(fixedKind); |
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78 while (interval != Interval::end()) { |
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79 int reg = interval->assigned_reg(); |
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80 assert(reg >= pd_first_fpu_reg && reg <= pd_last_fpu_reg, "no fpu register"); |
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81 assert(interval->assigned_regHi() == -1, "must not have hi register (doubles stored in one register)"); |
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82 assert(interval->from() <= id && id < interval->to(), "interval out of range"); |
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83 |
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84 #ifndef PRODUCT |
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85 if (TraceFPURegisterUsage) { |
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86 tty->print("fpu reg %d is live because of ", reg - pd_first_fpu_reg); interval->print(); |
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87 } |
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88 #endif |
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89 |
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90 regs.set_bit(reg - pd_first_fpu_reg); |
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91 interval = interval->next(); |
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92 } |
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93 |
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94 b->set_fpu_register_usage(regs); |
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95 |
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96 #ifndef PRODUCT |
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97 if (TraceFPURegisterUsage) { |
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98 tty->print("FPU regs for block %d, LIR instr %d): ", b->block_id(), id); regs.print_on(tty); tty->cr(); |
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99 } |
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100 #endif |
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101 } |
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102 } |
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103 } |
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104 |
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105 FpuStackAllocator alloc(ir()->compilation(), this); |
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106 _fpu_stack_allocator = &alloc; |
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107 alloc.allocate(); |
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108 _fpu_stack_allocator = NULL; |
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109 } |
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110 |
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111 |
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112 FpuStackAllocator::FpuStackAllocator(Compilation* compilation, LinearScan* allocator) |
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113 : _compilation(compilation) |
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114 , _lir(NULL) |
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115 , _pos(-1) |
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116 , _allocator(allocator) |
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117 , _sim(compilation) |
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118 , _temp_sim(compilation) |
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119 {} |
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120 |
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121 void FpuStackAllocator::allocate() { |
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122 int num_blocks = allocator()->block_count(); |
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123 for (int i = 0; i < num_blocks; i++) { |
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124 // Set up to process block |
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125 BlockBegin* block = allocator()->block_at(i); |
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126 intArray* fpu_stack_state = block->fpu_stack_state(); |
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127 |
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128 #ifndef PRODUCT |
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129 if (TraceFPUStack) { |
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130 tty->cr(); |
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131 tty->print_cr("------- Begin of new Block %d -------", block->block_id()); |
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132 } |
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133 #endif |
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134 |
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135 assert(fpu_stack_state != NULL || |
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136 block->end()->as_Base() != NULL || |
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137 block->is_set(BlockBegin::exception_entry_flag), |
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138 "FPU stack state must be present due to linear-scan order for FPU stack allocation"); |
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139 // note: exception handler entries always start with an empty fpu stack |
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140 // because stack merging would be too complicated |
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141 |
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142 if (fpu_stack_state != NULL) { |
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143 sim()->read_state(fpu_stack_state); |
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144 } else { |
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145 sim()->clear(); |
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146 } |
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147 |
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148 #ifndef PRODUCT |
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149 if (TraceFPUStack) { |
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150 tty->print("Reading FPU state for block %d:", block->block_id()); |
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151 sim()->print(); |
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152 tty->cr(); |
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153 } |
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154 #endif |
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155 |
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156 allocate_block(block); |
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157 CHECK_BAILOUT(); |
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158 } |
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159 } |
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160 |
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161 void FpuStackAllocator::allocate_block(BlockBegin* block) { |
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162 bool processed_merge = false; |
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163 LIR_OpList* insts = block->lir()->instructions_list(); |
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164 set_lir(block->lir()); |
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165 set_pos(0); |
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166 |
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167 |
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168 // Note: insts->length() may change during loop |
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169 while (pos() < insts->length()) { |
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170 LIR_Op* op = insts->at(pos()); |
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171 _debug_information_computed = false; |
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172 |
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173 #ifndef PRODUCT |
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174 if (TraceFPUStack) { |
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175 op->print(); |
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176 } |
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177 check_invalid_lir_op(op); |
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178 #endif |
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179 |
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180 LIR_OpBranch* branch = op->as_OpBranch(); |
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181 LIR_Op1* op1 = op->as_Op1(); |
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182 LIR_Op2* op2 = op->as_Op2(); |
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183 LIR_OpCall* opCall = op->as_OpCall(); |
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184 |
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185 if (branch != NULL && branch->block() != NULL) { |
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186 if (!processed_merge) { |
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187 // propagate stack at first branch to a successor |
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188 processed_merge = true; |
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189 bool required_merge = merge_fpu_stack_with_successors(block); |
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190 |
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191 assert(!required_merge || branch->cond() == lir_cond_always, "splitting of critical edges should prevent FPU stack mismatches at cond branches"); |
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192 } |
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193 |
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194 } else if (op1 != NULL) { |
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195 handle_op1(op1); |
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196 } else if (op2 != NULL) { |
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197 handle_op2(op2); |
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198 } else if (opCall != NULL) { |
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199 handle_opCall(opCall); |
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200 } |
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201 |
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202 compute_debug_information(op); |
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203 |
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204 set_pos(1 + pos()); |
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205 } |
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206 |
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207 // Propagate stack when block does not end with branch |
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208 if (!processed_merge) { |
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209 merge_fpu_stack_with_successors(block); |
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210 } |
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211 } |
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212 |
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213 |
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214 void FpuStackAllocator::compute_debug_information(LIR_Op* op) { |
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215 if (!_debug_information_computed && op->id() != -1 && allocator()->has_info(op->id())) { |
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216 visitor.visit(op); |
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217 |
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218 // exception handling |
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219 if (allocator()->compilation()->has_exception_handlers()) { |
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220 XHandlers* xhandlers = visitor.all_xhandler(); |
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221 int n = xhandlers->length(); |
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222 for (int k = 0; k < n; k++) { |
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223 allocate_exception_handler(xhandlers->handler_at(k)); |
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224 } |
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225 } else { |
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226 assert(visitor.all_xhandler()->length() == 0, "missed exception handler"); |
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227 } |
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228 |
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229 // compute debug information |
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230 int n = visitor.info_count(); |
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231 assert(n > 0, "should not visit operation otherwise"); |
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232 |
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233 for (int j = 0; j < n; j++) { |
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234 CodeEmitInfo* info = visitor.info_at(j); |
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235 // Compute debug information |
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236 allocator()->compute_debug_info(info, op->id()); |
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237 } |
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238 } |
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239 _debug_information_computed = true; |
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240 } |
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241 |
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242 void FpuStackAllocator::allocate_exception_handler(XHandler* xhandler) { |
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243 if (!sim()->is_empty()) { |
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244 LIR_List* old_lir = lir(); |
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245 int old_pos = pos(); |
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246 intArray* old_state = sim()->write_state(); |
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247 |
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248 #ifndef PRODUCT |
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249 if (TraceFPUStack) { |
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250 tty->cr(); |
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251 tty->print_cr("------- begin of exception handler -------"); |
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252 } |
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253 #endif |
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254 |
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255 if (xhandler->entry_code() == NULL) { |
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256 // need entry code to clear FPU stack |
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257 LIR_List* entry_code = new LIR_List(_compilation); |
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258 entry_code->jump(xhandler->entry_block()); |
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259 xhandler->set_entry_code(entry_code); |
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260 } |
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261 |
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262 LIR_OpList* insts = xhandler->entry_code()->instructions_list(); |
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263 set_lir(xhandler->entry_code()); |
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264 set_pos(0); |
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265 |
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266 // Note: insts->length() may change during loop |
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267 while (pos() < insts->length()) { |
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268 LIR_Op* op = insts->at(pos()); |
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269 |
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270 #ifndef PRODUCT |
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271 if (TraceFPUStack) { |
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272 op->print(); |
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273 } |
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274 check_invalid_lir_op(op); |
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275 #endif |
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276 |
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277 switch (op->code()) { |
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278 case lir_move: |
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279 assert(op->as_Op1() != NULL, "must be LIR_Op1"); |
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280 assert(pos() != insts->length() - 1, "must not be last operation"); |
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281 |
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282 handle_op1((LIR_Op1*)op); |
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283 break; |
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284 |
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285 case lir_branch: |
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286 assert(op->as_OpBranch()->cond() == lir_cond_always, "must be unconditional branch"); |
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287 assert(pos() == insts->length() - 1, "must be last operation"); |
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288 |
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289 // remove all remaining dead registers from FPU stack |
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290 clear_fpu_stack(LIR_OprFact::illegalOpr); |
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291 break; |
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292 |
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293 default: |
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294 // other operations not allowed in exception entry code |
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295 ShouldNotReachHere(); |
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296 } |
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297 |
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298 set_pos(pos() + 1); |
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299 } |
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300 |
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301 #ifndef PRODUCT |
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302 if (TraceFPUStack) { |
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303 tty->cr(); |
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304 tty->print_cr("------- end of exception handler -------"); |
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305 } |
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306 #endif |
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307 |
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308 set_lir(old_lir); |
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309 set_pos(old_pos); |
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310 sim()->read_state(old_state); |
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311 } |
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312 } |
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313 |
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314 |
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315 int FpuStackAllocator::fpu_num(LIR_Opr opr) { |
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316 assert(opr->is_fpu_register() && !opr->is_xmm_register(), "shouldn't call this otherwise"); |
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317 return opr->is_single_fpu() ? opr->fpu_regnr() : opr->fpu_regnrLo(); |
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318 } |
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319 |
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320 int FpuStackAllocator::tos_offset(LIR_Opr opr) { |
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321 return sim()->offset_from_tos(fpu_num(opr)); |
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322 } |
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323 |
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324 |
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325 LIR_Opr FpuStackAllocator::to_fpu_stack(LIR_Opr opr) { |
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326 assert(opr->is_fpu_register() && !opr->is_xmm_register(), "shouldn't call this otherwise"); |
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327 |
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328 int stack_offset = tos_offset(opr); |
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329 if (opr->is_single_fpu()) { |
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330 return LIR_OprFact::single_fpu(stack_offset)->make_fpu_stack_offset(); |
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331 } else { |
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332 assert(opr->is_double_fpu(), "shouldn't call this otherwise"); |
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333 return LIR_OprFact::double_fpu(stack_offset)->make_fpu_stack_offset(); |
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334 } |
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335 } |
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336 |
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337 LIR_Opr FpuStackAllocator::to_fpu_stack_top(LIR_Opr opr, bool dont_check_offset) { |
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338 assert(opr->is_fpu_register() && !opr->is_xmm_register(), "shouldn't call this otherwise"); |
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339 assert(dont_check_offset || tos_offset(opr) == 0, "operand is not on stack top"); |
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340 |
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341 int stack_offset = 0; |
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342 if (opr->is_single_fpu()) { |
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343 return LIR_OprFact::single_fpu(stack_offset)->make_fpu_stack_offset(); |
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344 } else { |
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345 assert(opr->is_double_fpu(), "shouldn't call this otherwise"); |
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346 return LIR_OprFact::double_fpu(stack_offset)->make_fpu_stack_offset(); |
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347 } |
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348 } |
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349 |
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350 |
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351 |
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352 void FpuStackAllocator::insert_op(LIR_Op* op) { |
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353 lir()->insert_before(pos(), op); |
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354 set_pos(1 + pos()); |
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355 } |
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356 |
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357 |
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358 void FpuStackAllocator::insert_exchange(int offset) { |
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359 if (offset > 0) { |
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360 LIR_Op1* fxch_op = new LIR_Op1(lir_fxch, LIR_OprFact::intConst(offset), LIR_OprFact::illegalOpr); |
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361 insert_op(fxch_op); |
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362 sim()->swap(offset); |
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363 |
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364 #ifndef PRODUCT |
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365 if (TraceFPUStack) { |
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366 tty->print("Exchanged register: %d New state: ", sim()->get_slot(0)); sim()->print(); tty->cr(); |
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367 } |
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368 #endif |
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369 |
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370 } |
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371 } |
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372 |
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373 void FpuStackAllocator::insert_exchange(LIR_Opr opr) { |
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374 insert_exchange(tos_offset(opr)); |
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375 } |
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376 |
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377 |
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378 void FpuStackAllocator::insert_free(int offset) { |
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379 // move stack slot to the top of stack and then pop it |
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380 insert_exchange(offset); |
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381 |
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382 LIR_Op* fpop = new LIR_Op0(lir_fpop_raw); |
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383 insert_op(fpop); |
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384 sim()->pop(); |
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385 |
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386 #ifndef PRODUCT |
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387 if (TraceFPUStack) { |
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388 tty->print("Inserted pop New state: "); sim()->print(); tty->cr(); |
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389 } |
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390 #endif |
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391 } |
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392 |
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393 |
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394 void FpuStackAllocator::insert_free_if_dead(LIR_Opr opr) { |
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395 if (sim()->contains(fpu_num(opr))) { |
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396 int res_slot = tos_offset(opr); |
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397 insert_free(res_slot); |
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398 } |
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399 } |
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400 |
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401 void FpuStackAllocator::insert_free_if_dead(LIR_Opr opr, LIR_Opr ignore) { |
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402 if (fpu_num(opr) != fpu_num(ignore) && sim()->contains(fpu_num(opr))) { |
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403 int res_slot = tos_offset(opr); |
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404 insert_free(res_slot); |
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405 } |
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406 } |
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407 |
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408 void FpuStackAllocator::insert_copy(LIR_Opr from, LIR_Opr to) { |
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409 int offset = tos_offset(from); |
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410 LIR_Op1* fld = new LIR_Op1(lir_fld, LIR_OprFact::intConst(offset), LIR_OprFact::illegalOpr); |
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411 insert_op(fld); |
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412 |
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413 sim()->push(fpu_num(to)); |
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414 |
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415 #ifndef PRODUCT |
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416 if (TraceFPUStack) { |
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417 tty->print("Inserted copy (%d -> %d) New state: ", fpu_num(from), fpu_num(to)); sim()->print(); tty->cr(); |
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418 } |
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419 #endif |
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420 } |
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421 |
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422 void FpuStackAllocator::do_rename(LIR_Opr from, LIR_Opr to) { |
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423 sim()->rename(fpu_num(from), fpu_num(to)); |
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424 } |
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425 |
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426 void FpuStackAllocator::do_push(LIR_Opr opr) { |
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427 sim()->push(fpu_num(opr)); |
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428 } |
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429 |
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430 void FpuStackAllocator::pop_if_last_use(LIR_Op* op, LIR_Opr opr) { |
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431 assert(op->fpu_pop_count() == 0, "fpu_pop_count alredy set"); |
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432 assert(tos_offset(opr) == 0, "can only pop stack top"); |
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433 |
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434 if (opr->is_last_use()) { |
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435 op->set_fpu_pop_count(1); |
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436 sim()->pop(); |
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437 } |
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438 } |
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439 |
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440 void FpuStackAllocator::pop_always(LIR_Op* op, LIR_Opr opr) { |
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441 assert(op->fpu_pop_count() == 0, "fpu_pop_count alredy set"); |
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442 assert(tos_offset(opr) == 0, "can only pop stack top"); |
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443 |
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444 op->set_fpu_pop_count(1); |
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445 sim()->pop(); |
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446 } |
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447 |
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448 void FpuStackAllocator::clear_fpu_stack(LIR_Opr preserve) { |
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449 int result_stack_size = (preserve->is_fpu_register() && !preserve->is_xmm_register() ? 1 : 0); |
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450 while (sim()->stack_size() > result_stack_size) { |
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451 assert(!sim()->slot_is_empty(0), "not allowed"); |
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452 |
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453 if (result_stack_size == 0 || sim()->get_slot(0) != fpu_num(preserve)) { |
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454 insert_free(0); |
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455 } else { |
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456 // move "preserve" to bottom of stack so that all other stack slots can be popped |
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457 insert_exchange(sim()->stack_size() - 1); |
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458 } |
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459 } |
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460 } |
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461 |
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462 |
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463 void FpuStackAllocator::handle_op1(LIR_Op1* op1) { |
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464 LIR_Opr in = op1->in_opr(); |
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465 LIR_Opr res = op1->result_opr(); |
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466 |
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467 LIR_Opr new_in = in; // new operands relative to the actual fpu stack top |
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468 LIR_Opr new_res = res; |
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469 |
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470 // Note: this switch is processed for all LIR_Op1, regardless if they have FPU-arguments, |
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471 // so checks for is_float_kind() are necessary inside the cases |
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472 switch (op1->code()) { |
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473 |
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474 case lir_return: { |
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475 // FPU-Stack must only contain the (optional) fpu return value. |
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476 // All remaining dead values are popped from the stack |
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477 // If the input operand is a fpu-register, it is exchanged to the bottom of the stack |
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478 |
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479 clear_fpu_stack(in); |
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480 if (in->is_fpu_register() && !in->is_xmm_register()) { |
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481 new_in = to_fpu_stack_top(in); |
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482 } |
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483 |
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484 break; |
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485 } |
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486 |
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487 case lir_move: { |
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488 if (in->is_fpu_register() && !in->is_xmm_register()) { |
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489 if (res->is_xmm_register()) { |
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490 // move from fpu register to xmm register (necessary for operations that |
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491 // are not available in the SSE instruction set) |
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492 insert_exchange(in); |
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493 new_in = to_fpu_stack_top(in); |
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494 pop_always(op1, in); |
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495 |
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496 } else if (res->is_fpu_register() && !res->is_xmm_register()) { |
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497 // move from fpu-register to fpu-register: |
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498 // * input and result register equal: |
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499 // nothing to do |
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500 // * input register is last use: |
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501 // rename the input register to result register -> input register |
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502 // not present on fpu-stack afterwards |
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503 // * input register not last use: |
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504 // duplicate input register to result register to preserve input |
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505 // |
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506 // Note: The LIR-Assembler does not produce any code for fpu register moves, |
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507 // so input and result stack index must be equal |
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508 |
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509 if (fpu_num(in) == fpu_num(res)) { |
|
510 // nothing to do |
|
511 } else if (in->is_last_use()) { |
|
512 insert_free_if_dead(res);//, in); |
|
513 do_rename(in, res); |
|
514 } else { |
|
515 insert_free_if_dead(res); |
|
516 insert_copy(in, res); |
|
517 } |
|
518 new_in = to_fpu_stack(res); |
|
519 new_res = new_in; |
|
520 |
|
521 } else { |
|
522 // move from fpu-register to memory |
|
523 // input operand must be on top of stack |
|
524 |
|
525 insert_exchange(in); |
|
526 |
|
527 // create debug information here because afterwards the register may have been popped |
|
528 compute_debug_information(op1); |
|
529 |
|
530 new_in = to_fpu_stack_top(in); |
|
531 pop_if_last_use(op1, in); |
|
532 } |
|
533 |
|
534 } else if (res->is_fpu_register() && !res->is_xmm_register()) { |
|
535 // move from memory/constant to fpu register |
|
536 // result is pushed on the stack |
|
537 |
|
538 insert_free_if_dead(res); |
|
539 |
|
540 // create debug information before register is pushed |
|
541 compute_debug_information(op1); |
|
542 |
|
543 do_push(res); |
|
544 new_res = to_fpu_stack_top(res); |
|
545 } |
|
546 break; |
|
547 } |
|
548 |
|
549 case lir_neg: { |
|
550 if (in->is_fpu_register() && !in->is_xmm_register()) { |
|
551 assert(res->is_fpu_register() && !res->is_xmm_register(), "must be"); |
|
552 assert(in->is_last_use(), "old value gets destroyed"); |
|
553 |
|
554 insert_free_if_dead(res, in); |
|
555 insert_exchange(in); |
|
556 new_in = to_fpu_stack_top(in); |
|
557 |
|
558 do_rename(in, res); |
|
559 new_res = to_fpu_stack_top(res); |
|
560 } |
|
561 break; |
|
562 } |
|
563 |
|
564 case lir_convert: { |
|
565 Bytecodes::Code bc = op1->as_OpConvert()->bytecode(); |
|
566 switch (bc) { |
|
567 case Bytecodes::_d2f: |
|
568 case Bytecodes::_f2d: |
|
569 assert(res->is_fpu_register(), "must be"); |
|
570 assert(in->is_fpu_register(), "must be"); |
|
571 |
|
572 if (!in->is_xmm_register() && !res->is_xmm_register()) { |
|
573 // this is quite the same as a move from fpu-register to fpu-register |
|
574 // Note: input and result operands must have different types |
|
575 if (fpu_num(in) == fpu_num(res)) { |
|
576 // nothing to do |
|
577 new_in = to_fpu_stack(in); |
|
578 } else if (in->is_last_use()) { |
|
579 insert_free_if_dead(res);//, in); |
|
580 new_in = to_fpu_stack(in); |
|
581 do_rename(in, res); |
|
582 } else { |
|
583 insert_free_if_dead(res); |
|
584 insert_copy(in, res); |
|
585 new_in = to_fpu_stack_top(in, true); |
|
586 } |
|
587 new_res = to_fpu_stack(res); |
|
588 } |
|
589 |
|
590 break; |
|
591 |
|
592 case Bytecodes::_i2f: |
|
593 case Bytecodes::_l2f: |
|
594 case Bytecodes::_i2d: |
|
595 case Bytecodes::_l2d: |
|
596 assert(res->is_fpu_register(), "must be"); |
|
597 if (!res->is_xmm_register()) { |
|
598 insert_free_if_dead(res); |
|
599 do_push(res); |
|
600 new_res = to_fpu_stack_top(res); |
|
601 } |
|
602 break; |
|
603 |
|
604 case Bytecodes::_f2i: |
|
605 case Bytecodes::_d2i: |
|
606 assert(in->is_fpu_register(), "must be"); |
|
607 if (!in->is_xmm_register()) { |
|
608 insert_exchange(in); |
|
609 new_in = to_fpu_stack_top(in); |
|
610 |
|
611 // TODO: update registes of stub |
|
612 } |
|
613 break; |
|
614 |
|
615 case Bytecodes::_f2l: |
|
616 case Bytecodes::_d2l: |
|
617 assert(in->is_fpu_register(), "must be"); |
|
618 if (!in->is_xmm_register()) { |
|
619 insert_exchange(in); |
|
620 new_in = to_fpu_stack_top(in); |
|
621 pop_always(op1, in); |
|
622 } |
|
623 break; |
|
624 |
|
625 case Bytecodes::_i2l: |
|
626 case Bytecodes::_l2i: |
|
627 case Bytecodes::_i2b: |
|
628 case Bytecodes::_i2c: |
|
629 case Bytecodes::_i2s: |
|
630 // no fpu operands |
|
631 break; |
|
632 |
|
633 default: |
|
634 ShouldNotReachHere(); |
|
635 } |
|
636 break; |
|
637 } |
|
638 |
|
639 case lir_roundfp: { |
|
640 assert(in->is_fpu_register() && !in->is_xmm_register(), "input must be in register"); |
|
641 assert(res->is_stack(), "result must be on stack"); |
|
642 |
|
643 insert_exchange(in); |
|
644 new_in = to_fpu_stack_top(in); |
|
645 pop_if_last_use(op1, in); |
|
646 break; |
|
647 } |
|
648 |
|
649 default: { |
|
650 assert(!in->is_float_kind() && !res->is_float_kind(), "missed a fpu-operation"); |
|
651 } |
|
652 } |
|
653 |
|
654 op1->set_in_opr(new_in); |
|
655 op1->set_result_opr(new_res); |
|
656 } |
|
657 |
|
658 void FpuStackAllocator::handle_op2(LIR_Op2* op2) { |
|
659 LIR_Opr left = op2->in_opr1(); |
|
660 if (!left->is_float_kind()) { |
|
661 return; |
|
662 } |
|
663 if (left->is_xmm_register()) { |
|
664 return; |
|
665 } |
|
666 |
|
667 LIR_Opr right = op2->in_opr2(); |
|
668 LIR_Opr res = op2->result_opr(); |
|
669 LIR_Opr new_left = left; // new operands relative to the actual fpu stack top |
|
670 LIR_Opr new_right = right; |
|
671 LIR_Opr new_res = res; |
|
672 |
|
673 assert(!left->is_xmm_register() && !right->is_xmm_register() && !res->is_xmm_register(), "not for xmm registers"); |
|
674 |
|
675 switch (op2->code()) { |
|
676 case lir_cmp: |
|
677 case lir_cmp_fd2i: |
|
678 case lir_ucmp_fd2i: |
|
679 case lir_assert: { |
|
680 assert(left->is_fpu_register(), "invalid LIR"); |
|
681 assert(right->is_fpu_register(), "invalid LIR"); |
|
682 |
|
683 // the left-hand side must be on top of stack. |
|
684 // the right-hand side is never popped, even if is_last_use is set |
|
685 insert_exchange(left); |
|
686 new_left = to_fpu_stack_top(left); |
|
687 new_right = to_fpu_stack(right); |
|
688 pop_if_last_use(op2, left); |
|
689 break; |
|
690 } |
|
691 |
|
692 case lir_mul_strictfp: |
|
693 case lir_div_strictfp: { |
|
694 assert(op2->tmp1_opr()->is_fpu_register(), "strict operations need temporary fpu stack slot"); |
|
695 insert_free_if_dead(op2->tmp1_opr()); |
|
696 assert(sim()->stack_size() <= 7, "at least one stack slot must be free"); |
|
697 // fall-through: continue with the normal handling of lir_mul and lir_div |
|
698 } |
|
699 case lir_add: |
|
700 case lir_sub: |
|
701 case lir_mul: |
|
702 case lir_div: { |
|
703 assert(left->is_fpu_register(), "must be"); |
|
704 assert(res->is_fpu_register(), "must be"); |
|
705 assert(left->is_equal(res), "must be"); |
|
706 |
|
707 // either the left-hand or the right-hand side must be on top of stack |
|
708 // (if right is not a register, left must be on top) |
|
709 if (!right->is_fpu_register()) { |
|
710 insert_exchange(left); |
|
711 new_left = to_fpu_stack_top(left); |
|
712 } else { |
|
713 // no exchange necessary if right is alredy on top of stack |
|
714 if (tos_offset(right) == 0) { |
|
715 new_left = to_fpu_stack(left); |
|
716 new_right = to_fpu_stack_top(right); |
|
717 } else { |
|
718 insert_exchange(left); |
|
719 new_left = to_fpu_stack_top(left); |
|
720 new_right = to_fpu_stack(right); |
|
721 } |
|
722 |
|
723 if (right->is_last_use()) { |
|
724 op2->set_fpu_pop_count(1); |
|
725 |
|
726 if (tos_offset(right) == 0) { |
|
727 sim()->pop(); |
|
728 } else { |
|
729 // if left is on top of stack, the result is placed in the stack |
|
730 // slot of right, so a renaming from right to res is necessary |
|
731 assert(tos_offset(left) == 0, "must be"); |
|
732 sim()->pop(); |
|
733 do_rename(right, res); |
|
734 } |
|
735 } |
|
736 } |
|
737 new_res = to_fpu_stack(res); |
|
738 |
|
739 break; |
|
740 } |
|
741 |
|
742 case lir_rem: { |
|
743 assert(left->is_fpu_register(), "must be"); |
|
744 assert(right->is_fpu_register(), "must be"); |
|
745 assert(res->is_fpu_register(), "must be"); |
|
746 assert(left->is_equal(res), "must be"); |
|
747 |
|
748 // Must bring both operands to top of stack with following operand ordering: |
|
749 // * fpu stack before rem: ... right left |
|
750 // * fpu stack after rem: ... left |
|
751 if (tos_offset(right) != 1) { |
|
752 insert_exchange(right); |
|
753 insert_exchange(1); |
|
754 } |
|
755 insert_exchange(left); |
|
756 assert(tos_offset(right) == 1, "check"); |
|
757 assert(tos_offset(left) == 0, "check"); |
|
758 |
|
759 new_left = to_fpu_stack_top(left); |
|
760 new_right = to_fpu_stack(right); |
|
761 |
|
762 op2->set_fpu_pop_count(1); |
|
763 sim()->pop(); |
|
764 do_rename(right, res); |
|
765 |
|
766 new_res = to_fpu_stack_top(res); |
|
767 break; |
|
768 } |
|
769 |
|
770 case lir_abs: |
|
771 case lir_sqrt: { |
|
772 // Right argument appears to be unused |
|
773 assert(right->is_illegal(), "must be"); |
|
774 assert(left->is_fpu_register(), "must be"); |
|
775 assert(res->is_fpu_register(), "must be"); |
|
776 assert(left->is_last_use(), "old value gets destroyed"); |
|
777 |
|
778 insert_free_if_dead(res, left); |
|
779 insert_exchange(left); |
|
780 do_rename(left, res); |
|
781 |
|
782 new_left = to_fpu_stack_top(res); |
|
783 new_res = new_left; |
|
784 |
|
785 op2->set_fpu_stack_size(sim()->stack_size()); |
|
786 break; |
|
787 } |
|
788 |
|
789 case lir_log: |
|
790 case lir_log10: { |
|
791 // log and log10 need one temporary fpu stack slot, so |
|
792 // there is one temporary registers stored in temp of the |
|
793 // operation. the stack allocator must guarantee that the stack |
|
794 // slots are really free, otherwise there might be a stack |
|
795 // overflow. |
|
796 assert(right->is_illegal(), "must be"); |
|
797 assert(left->is_fpu_register(), "must be"); |
|
798 assert(res->is_fpu_register(), "must be"); |
|
799 assert(op2->tmp1_opr()->is_fpu_register(), "must be"); |
|
800 |
|
801 insert_free_if_dead(op2->tmp1_opr()); |
|
802 insert_free_if_dead(res, left); |
|
803 insert_exchange(left); |
|
804 do_rename(left, res); |
|
805 |
|
806 new_left = to_fpu_stack_top(res); |
|
807 new_res = new_left; |
|
808 |
|
809 op2->set_fpu_stack_size(sim()->stack_size()); |
|
810 assert(sim()->stack_size() <= 7, "at least one stack slot must be free"); |
|
811 break; |
|
812 } |
|
813 |
|
814 |
|
815 case lir_tan: |
|
816 case lir_sin: |
|
817 case lir_cos: |
|
818 case lir_exp: { |
|
819 // sin, cos and exp need two temporary fpu stack slots, so there are two temporary |
|
820 // registers (stored in right and temp of the operation). |
|
821 // the stack allocator must guarantee that the stack slots are really free, |
|
822 // otherwise there might be a stack overflow. |
|
823 assert(left->is_fpu_register(), "must be"); |
|
824 assert(res->is_fpu_register(), "must be"); |
|
825 // assert(left->is_last_use(), "old value gets destroyed"); |
|
826 assert(right->is_fpu_register(), "right is used as the first temporary register"); |
|
827 assert(op2->tmp1_opr()->is_fpu_register(), "temp is used as the second temporary register"); |
|
828 assert(fpu_num(left) != fpu_num(right) && fpu_num(right) != fpu_num(op2->tmp1_opr()) && fpu_num(op2->tmp1_opr()) != fpu_num(res), "need distinct temp registers"); |
|
829 |
|
830 insert_free_if_dead(right); |
|
831 insert_free_if_dead(op2->tmp1_opr()); |
|
832 |
|
833 insert_free_if_dead(res, left); |
|
834 insert_exchange(left); |
|
835 do_rename(left, res); |
|
836 |
|
837 new_left = to_fpu_stack_top(res); |
|
838 new_res = new_left; |
|
839 |
|
840 op2->set_fpu_stack_size(sim()->stack_size()); |
|
841 assert(sim()->stack_size() <= 6, "at least two stack slots must be free"); |
|
842 break; |
|
843 } |
|
844 |
|
845 case lir_pow: { |
|
846 // pow needs two temporary fpu stack slots, so there are two temporary |
|
847 // registers (stored in tmp1 and tmp2 of the operation). |
|
848 // the stack allocator must guarantee that the stack slots are really free, |
|
849 // otherwise there might be a stack overflow. |
|
850 assert(left->is_fpu_register(), "must be"); |
|
851 assert(right->is_fpu_register(), "must be"); |
|
852 assert(res->is_fpu_register(), "must be"); |
|
853 |
|
854 assert(op2->tmp1_opr()->is_fpu_register(), "tmp1 is the first temporary register"); |
|
855 assert(op2->tmp2_opr()->is_fpu_register(), "tmp2 is the second temporary register"); |
|
856 assert(fpu_num(left) != fpu_num(right) && fpu_num(left) != fpu_num(op2->tmp1_opr()) && fpu_num(left) != fpu_num(op2->tmp2_opr()) && fpu_num(left) != fpu_num(res), "need distinct temp registers"); |
|
857 assert(fpu_num(right) != fpu_num(op2->tmp1_opr()) && fpu_num(right) != fpu_num(op2->tmp2_opr()) && fpu_num(right) != fpu_num(res), "need distinct temp registers"); |
|
858 assert(fpu_num(op2->tmp1_opr()) != fpu_num(op2->tmp2_opr()) && fpu_num(op2->tmp1_opr()) != fpu_num(res), "need distinct temp registers"); |
|
859 assert(fpu_num(op2->tmp2_opr()) != fpu_num(res), "need distinct temp registers"); |
|
860 |
|
861 insert_free_if_dead(op2->tmp1_opr()); |
|
862 insert_free_if_dead(op2->tmp2_opr()); |
|
863 |
|
864 // Must bring both operands to top of stack with following operand ordering: |
|
865 // * fpu stack before pow: ... right left |
|
866 // * fpu stack after pow: ... left |
|
867 |
|
868 insert_free_if_dead(res, right); |
|
869 |
|
870 if (tos_offset(right) != 1) { |
|
871 insert_exchange(right); |
|
872 insert_exchange(1); |
|
873 } |
|
874 insert_exchange(left); |
|
875 assert(tos_offset(right) == 1, "check"); |
|
876 assert(tos_offset(left) == 0, "check"); |
|
877 |
|
878 new_left = to_fpu_stack_top(left); |
|
879 new_right = to_fpu_stack(right); |
|
880 |
|
881 op2->set_fpu_stack_size(sim()->stack_size()); |
|
882 assert(sim()->stack_size() <= 6, "at least two stack slots must be free"); |
|
883 |
|
884 sim()->pop(); |
|
885 |
|
886 do_rename(right, res); |
|
887 |
|
888 new_res = to_fpu_stack_top(res); |
|
889 break; |
|
890 } |
|
891 |
|
892 default: { |
|
893 assert(false, "missed a fpu-operation"); |
|
894 } |
|
895 } |
|
896 |
|
897 op2->set_in_opr1(new_left); |
|
898 op2->set_in_opr2(new_right); |
|
899 op2->set_result_opr(new_res); |
|
900 } |
|
901 |
|
902 void FpuStackAllocator::handle_opCall(LIR_OpCall* opCall) { |
|
903 LIR_Opr res = opCall->result_opr(); |
|
904 |
|
905 // clear fpu-stack before call |
|
906 // it may contain dead values that could not have been remved by previous operations |
|
907 clear_fpu_stack(LIR_OprFact::illegalOpr); |
|
908 assert(sim()->is_empty(), "fpu stack must be empty now"); |
|
909 |
|
910 // compute debug information before (possible) fpu result is pushed |
|
911 compute_debug_information(opCall); |
|
912 |
|
913 if (res->is_fpu_register() && !res->is_xmm_register()) { |
|
914 do_push(res); |
|
915 opCall->set_result_opr(to_fpu_stack_top(res)); |
|
916 } |
|
917 } |
|
918 |
|
919 #ifndef PRODUCT |
|
920 void FpuStackAllocator::check_invalid_lir_op(LIR_Op* op) { |
|
921 switch (op->code()) { |
|
922 case lir_24bit_FPU: |
|
923 case lir_reset_FPU: |
|
924 case lir_ffree: |
|
925 assert(false, "operations not allowed in lir. If one of these operations is needed, check if they have fpu operands"); |
|
926 break; |
|
927 |
|
928 case lir_fpop_raw: |
|
929 case lir_fxch: |
|
930 case lir_fld: |
|
931 assert(false, "operations only inserted by FpuStackAllocator"); |
|
932 break; |
|
933 } |
|
934 } |
|
935 #endif |
|
936 |
|
937 |
|
938 void FpuStackAllocator::merge_insert_add(LIR_List* instrs, FpuStackSim* cur_sim, int reg) { |
|
939 LIR_Op1* move = new LIR_Op1(lir_move, LIR_OprFact::doubleConst(0), LIR_OprFact::double_fpu(reg)->make_fpu_stack_offset()); |
|
940 |
|
941 instrs->instructions_list()->push(move); |
|
942 |
|
943 cur_sim->push(reg); |
|
944 move->set_result_opr(to_fpu_stack(move->result_opr())); |
|
945 |
|
946 #ifndef PRODUCT |
|
947 if (TraceFPUStack) { |
|
948 tty->print("Added new register: %d New state: ", reg); cur_sim->print(); tty->cr(); |
|
949 } |
|
950 #endif |
|
951 } |
|
952 |
|
953 void FpuStackAllocator::merge_insert_xchg(LIR_List* instrs, FpuStackSim* cur_sim, int slot) { |
|
954 assert(slot > 0, "no exchange necessary"); |
|
955 |
|
956 LIR_Op1* fxch = new LIR_Op1(lir_fxch, LIR_OprFact::intConst(slot)); |
|
957 instrs->instructions_list()->push(fxch); |
|
958 cur_sim->swap(slot); |
|
959 |
|
960 #ifndef PRODUCT |
|
961 if (TraceFPUStack) { |
|
962 tty->print("Exchanged register: %d New state: ", cur_sim->get_slot(slot)); cur_sim->print(); tty->cr(); |
|
963 } |
|
964 #endif |
|
965 } |
|
966 |
|
967 void FpuStackAllocator::merge_insert_pop(LIR_List* instrs, FpuStackSim* cur_sim) { |
|
968 int reg = cur_sim->get_slot(0); |
|
969 |
|
970 LIR_Op* fpop = new LIR_Op0(lir_fpop_raw); |
|
971 instrs->instructions_list()->push(fpop); |
|
972 cur_sim->pop(reg); |
|
973 |
|
974 #ifndef PRODUCT |
|
975 if (TraceFPUStack) { |
|
976 tty->print("Removed register: %d New state: ", reg); cur_sim->print(); tty->cr(); |
|
977 } |
|
978 #endif |
|
979 } |
|
980 |
|
981 bool FpuStackAllocator::merge_rename(FpuStackSim* cur_sim, FpuStackSim* sux_sim, int start_slot, int change_slot) { |
|
982 int reg = cur_sim->get_slot(change_slot); |
|
983 |
|
984 for (int slot = start_slot; slot >= 0; slot--) { |
|
985 int new_reg = sux_sim->get_slot(slot); |
|
986 |
|
987 if (!cur_sim->contains(new_reg)) { |
|
988 cur_sim->set_slot(change_slot, new_reg); |
|
989 |
|
990 #ifndef PRODUCT |
|
991 if (TraceFPUStack) { |
|
992 tty->print("Renamed register %d to %d New state: ", reg, new_reg); cur_sim->print(); tty->cr(); |
|
993 } |
|
994 #endif |
|
995 |
|
996 return true; |
|
997 } |
|
998 } |
|
999 return false; |
|
1000 } |
|
1001 |
|
1002 |
|
1003 void FpuStackAllocator::merge_fpu_stack(LIR_List* instrs, FpuStackSim* cur_sim, FpuStackSim* sux_sim) { |
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1004 #ifndef PRODUCT |
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1005 if (TraceFPUStack) { |
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1006 tty->cr(); |
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1007 tty->print("before merging: pred: "); cur_sim->print(); tty->cr(); |
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1008 tty->print(" sux: "); sux_sim->print(); tty->cr(); |
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1009 } |
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1010 |
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1011 int slot; |
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1012 for (slot = 0; slot < cur_sim->stack_size(); slot++) { |
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1013 assert(!cur_sim->slot_is_empty(slot), "not handled by algorithm"); |
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1014 } |
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1015 for (slot = 0; slot < sux_sim->stack_size(); slot++) { |
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1016 assert(!sux_sim->slot_is_empty(slot), "not handled by algorithm"); |
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1017 } |
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1018 #endif |
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1019 |
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1020 // size difference between cur and sux that must be resolved by adding or removing values form the stack |
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1021 int size_diff = cur_sim->stack_size() - sux_sim->stack_size(); |
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1022 |
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1023 if (!ComputeExactFPURegisterUsage) { |
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1024 // add slots that are currently free, but used in successor |
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1025 // When the exact FPU register usage is computed, the stack does |
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1026 // not contain dead values at merging -> no values must be added |
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1027 |
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1028 int sux_slot = sux_sim->stack_size() - 1; |
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1029 while (size_diff < 0) { |
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1030 assert(sux_slot >= 0, "slot out of bounds -> error in algorithm"); |
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1031 |
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1032 int reg = sux_sim->get_slot(sux_slot); |
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1033 if (!cur_sim->contains(reg)) { |
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1034 merge_insert_add(instrs, cur_sim, reg); |
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1035 size_diff++; |
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1036 |
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1037 if (sux_slot + size_diff != 0) { |
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1038 merge_insert_xchg(instrs, cur_sim, sux_slot + size_diff); |
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1039 } |
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1040 } |
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1041 sux_slot--; |
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1042 } |
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1043 } |
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1044 |
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1045 assert(cur_sim->stack_size() >= sux_sim->stack_size(), "stack size must be equal or greater now"); |
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1046 assert(size_diff == cur_sim->stack_size() - sux_sim->stack_size(), "must be"); |
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1047 |
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1048 // stack merge algorithm: |
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1049 // 1) as long as the current stack top is not in the right location (that meens |
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1050 // it should not be on the stack top), exchange it into the right location |
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1051 // 2) if the stack top is right, but the remaining stack is not ordered correctly, |
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1052 // the stack top is exchanged away to get another value on top -> |
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1053 // now step 1) can be continued |
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1054 // the stack can also contain unused items -> these items are removed from stack |
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1055 |
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1056 int finished_slot = sux_sim->stack_size() - 1; |
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1057 while (finished_slot >= 0 || size_diff > 0) { |
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1058 while (size_diff > 0 || (cur_sim->stack_size() > 0 && cur_sim->get_slot(0) != sux_sim->get_slot(0))) { |
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1059 int reg = cur_sim->get_slot(0); |
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1060 if (sux_sim->contains(reg)) { |
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1061 int sux_slot = sux_sim->offset_from_tos(reg); |
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1062 merge_insert_xchg(instrs, cur_sim, sux_slot + size_diff); |
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1063 |
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1064 } else if (!merge_rename(cur_sim, sux_sim, finished_slot, 0)) { |
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1065 assert(size_diff > 0, "must be"); |
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1066 |
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1067 merge_insert_pop(instrs, cur_sim); |
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1068 size_diff--; |
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1069 } |
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1070 assert(cur_sim->stack_size() == 0 || cur_sim->get_slot(0) != reg, "register must have been changed"); |
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1071 } |
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1072 |
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1073 while (finished_slot >= 0 && cur_sim->get_slot(finished_slot) == sux_sim->get_slot(finished_slot)) { |
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1074 finished_slot--; |
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1075 } |
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1076 |
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1077 if (finished_slot >= 0) { |
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1078 int reg = cur_sim->get_slot(finished_slot); |
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1079 |
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1080 if (sux_sim->contains(reg) || !merge_rename(cur_sim, sux_sim, finished_slot, finished_slot)) { |
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1081 assert(sux_sim->contains(reg) || size_diff > 0, "must be"); |
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1082 merge_insert_xchg(instrs, cur_sim, finished_slot); |
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1083 } |
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1084 assert(cur_sim->get_slot(finished_slot) != reg, "register must have been changed"); |
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1085 } |
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1086 } |
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1087 |
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1088 #ifndef PRODUCT |
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1089 if (TraceFPUStack) { |
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1090 tty->print("after merging: pred: "); cur_sim->print(); tty->cr(); |
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1091 tty->print(" sux: "); sux_sim->print(); tty->cr(); |
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1092 tty->cr(); |
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1093 } |
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1094 #endif |
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1095 assert(cur_sim->stack_size() == sux_sim->stack_size(), "stack size must be equal now"); |
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1096 } |
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1097 |
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1098 |
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1099 void FpuStackAllocator::merge_cleanup_fpu_stack(LIR_List* instrs, FpuStackSim* cur_sim, BitMap& live_fpu_regs) { |
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1100 #ifndef PRODUCT |
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1101 if (TraceFPUStack) { |
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1102 tty->cr(); |
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1103 tty->print("before cleanup: state: "); cur_sim->print(); tty->cr(); |
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1104 tty->print(" live: "); live_fpu_regs.print_on(tty); tty->cr(); |
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1105 } |
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1106 #endif |
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1107 |
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1108 int slot = 0; |
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1109 while (slot < cur_sim->stack_size()) { |
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1110 int reg = cur_sim->get_slot(slot); |
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1111 if (!live_fpu_regs.at(reg)) { |
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1112 if (slot != 0) { |
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1113 merge_insert_xchg(instrs, cur_sim, slot); |
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1114 } |
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1115 merge_insert_pop(instrs, cur_sim); |
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1116 } else { |
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1117 slot++; |
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1118 } |
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1119 } |
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1120 |
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1121 #ifndef PRODUCT |
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1122 if (TraceFPUStack) { |
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1123 tty->print("after cleanup: state: "); cur_sim->print(); tty->cr(); |
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1124 tty->print(" live: "); live_fpu_regs.print_on(tty); tty->cr(); |
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1125 tty->cr(); |
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1126 } |
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1127 |
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1128 // check if fpu stack only contains live registers |
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1129 for (unsigned int i = 0; i < live_fpu_regs.size(); i++) { |
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1130 if (live_fpu_regs.at(i) != cur_sim->contains(i)) { |
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1131 tty->print_cr("mismatch between required and actual stack content"); |
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1132 break; |
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1133 } |
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1134 } |
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1135 #endif |
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1136 } |
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1137 |
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1138 |
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1139 bool FpuStackAllocator::merge_fpu_stack_with_successors(BlockBegin* block) { |
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1140 #ifndef PRODUCT |
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1141 if (TraceFPUStack) { |
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1142 tty->print_cr("Propagating FPU stack state for B%d at LIR_Op position %d to successors:", |
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1143 block->block_id(), pos()); |
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1144 sim()->print(); |
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1145 tty->cr(); |
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1146 } |
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1147 #endif |
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1148 |
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1149 bool changed = false; |
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1150 int number_of_sux = block->number_of_sux(); |
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1151 |
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1152 if (number_of_sux == 1 && block->sux_at(0)->number_of_preds() > 1) { |
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1153 // The successor has at least two incoming edges, so a stack merge will be necessary |
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1154 // If this block is the first predecessor, cleanup the current stack and propagate it |
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1155 // If this block is not the first predecessor, a stack merge will be necessary |
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1156 |
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1157 BlockBegin* sux = block->sux_at(0); |
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1158 intArray* state = sux->fpu_stack_state(); |
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1159 LIR_List* instrs = new LIR_List(_compilation); |
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1160 |
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1161 if (state != NULL) { |
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1162 // Merge with a successors that already has a FPU stack state |
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1163 // the block must only have one successor because critical edges must been split |
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1164 FpuStackSim* cur_sim = sim(); |
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1165 FpuStackSim* sux_sim = temp_sim(); |
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1166 sux_sim->read_state(state); |
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1167 |
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1168 merge_fpu_stack(instrs, cur_sim, sux_sim); |
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1169 |
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1170 } else { |
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1171 // propagate current FPU stack state to successor without state |
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1172 // clean up stack first so that there are no dead values on the stack |
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1173 if (ComputeExactFPURegisterUsage) { |
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1174 FpuStackSim* cur_sim = sim(); |
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1175 BitMap live_fpu_regs = block->sux_at(0)->fpu_register_usage(); |
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1176 assert(live_fpu_regs.size() == FrameMap::nof_fpu_regs, "missing register usage"); |
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1177 |
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1178 merge_cleanup_fpu_stack(instrs, cur_sim, live_fpu_regs); |
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1179 } |
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1180 |
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1181 intArray* state = sim()->write_state(); |
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1182 if (TraceFPUStack) { |
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1183 tty->print_cr("Setting FPU stack state of B%d (merge path)", sux->block_id()); |
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1184 sim()->print(); tty->cr(); |
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1185 } |
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1186 sux->set_fpu_stack_state(state); |
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1187 } |
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1188 |
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1189 if (instrs->instructions_list()->length() > 0) { |
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1190 lir()->insert_before(pos(), instrs); |
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1191 set_pos(instrs->instructions_list()->length() + pos()); |
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1192 changed = true; |
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1193 } |
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1194 |
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1195 } else { |
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1196 // Propagate unmodified Stack to successors where a stack merge is not necessary |
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1197 intArray* state = sim()->write_state(); |
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1198 for (int i = 0; i < number_of_sux; i++) { |
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1199 BlockBegin* sux = block->sux_at(i); |
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1200 |
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1201 #ifdef ASSERT |
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1202 for (int j = 0; j < sux->number_of_preds(); j++) { |
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1203 assert(block == sux->pred_at(j), "all critical edges must be broken"); |
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1204 } |
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1205 |
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1206 // check if new state is same |
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1207 if (sux->fpu_stack_state() != NULL) { |
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1208 intArray* sux_state = sux->fpu_stack_state(); |
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1209 assert(state->length() == sux_state->length(), "overwriting existing stack state"); |
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1210 for (int j = 0; j < state->length(); j++) { |
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1211 assert(state->at(j) == sux_state->at(j), "overwriting existing stack state"); |
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1212 } |
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1213 } |
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1214 #endif |
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1215 #ifndef PRODUCT |
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1216 if (TraceFPUStack) { |
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1217 tty->print_cr("Setting FPU stack state of B%d", sux->block_id()); |
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1218 sim()->print(); tty->cr(); |
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1219 } |
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1220 #endif |
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1221 |
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1222 sux->set_fpu_stack_state(state); |
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1223 } |
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1224 } |
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1225 |
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1226 #ifndef PRODUCT |
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1227 // assertions that FPU stack state conforms to all successors' states |
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1228 intArray* cur_state = sim()->write_state(); |
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1229 for (int i = 0; i < number_of_sux; i++) { |
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1230 BlockBegin* sux = block->sux_at(i); |
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1231 intArray* sux_state = sux->fpu_stack_state(); |
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1232 |
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1233 assert(sux_state != NULL, "no fpu state"); |
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1234 assert(cur_state->length() == sux_state->length(), "incorrect length"); |
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1235 for (int i = 0; i < cur_state->length(); i++) { |
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1236 assert(cur_state->at(i) == sux_state->at(i), "element not equal"); |
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1237 } |
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1238 } |
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1239 #endif |
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1240 |
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1241 return changed; |
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1242 } |