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1 /* |
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2 * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. |
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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4 * |
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5 * This code is free software; you can redistribute it and/or modify it |
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6 * under the terms of the GNU General Public License version 2 only, as |
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7 * published by the Free Software Foundation. |
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8 * |
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9 * This code is distributed in the hope that it will be useful, but WITHOUT |
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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12 * version 2 for more details (a copy is included in the LICENSE file that |
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13 * accompanied this code). |
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14 * |
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15 * You should have received a copy of the GNU General Public License version |
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16 * 2 along with this work; if not, write to the Free Software Foundation, |
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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18 * |
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
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22 * |
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23 */ |
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24 |
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25 #include "precompiled.hpp" |
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26 #include "asm/macroAssembler.inline.hpp" |
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27 #include "memory/resourceArea.hpp" |
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28 #include "runtime/java.hpp" |
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29 #include "runtime/stubCodeGenerator.hpp" |
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30 #include "vm_version_sparc.hpp" |
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31 #ifdef TARGET_OS_FAMILY_linux |
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32 # include "os_linux.inline.hpp" |
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33 #endif |
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34 #ifdef TARGET_OS_FAMILY_solaris |
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35 # include "os_solaris.inline.hpp" |
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36 #endif |
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37 |
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38 int VM_Version::_features = VM_Version::unknown_m; |
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39 const char* VM_Version::_features_str = ""; |
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40 |
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41 void VM_Version::initialize() { |
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42 _features = determine_features(); |
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43 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes(); |
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44 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes(); |
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45 PrefetchFieldsAhead = prefetch_fields_ahead(); |
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46 |
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47 assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 1, "invalid value"); |
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48 if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0; |
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49 if( AllocatePrefetchInstr > 1 ) AllocatePrefetchInstr = 0; |
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50 |
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51 // Allocation prefetch settings |
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52 intx cache_line_size = prefetch_data_size(); |
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53 if( cache_line_size > AllocatePrefetchStepSize ) |
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54 AllocatePrefetchStepSize = cache_line_size; |
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55 |
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56 assert(AllocatePrefetchLines > 0, "invalid value"); |
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57 if( AllocatePrefetchLines < 1 ) // set valid value in product VM |
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58 AllocatePrefetchLines = 3; |
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59 assert(AllocateInstancePrefetchLines > 0, "invalid value"); |
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60 if( AllocateInstancePrefetchLines < 1 ) // set valid value in product VM |
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61 AllocateInstancePrefetchLines = 1; |
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62 |
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63 AllocatePrefetchDistance = allocate_prefetch_distance(); |
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64 AllocatePrefetchStyle = allocate_prefetch_style(); |
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65 |
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66 assert((AllocatePrefetchDistance % AllocatePrefetchStepSize) == 0 && |
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67 (AllocatePrefetchDistance > 0), "invalid value"); |
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68 if ((AllocatePrefetchDistance % AllocatePrefetchStepSize) != 0 || |
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69 (AllocatePrefetchDistance <= 0)) { |
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70 AllocatePrefetchDistance = AllocatePrefetchStepSize; |
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71 } |
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72 |
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73 if (AllocatePrefetchStyle == 3 && !has_blk_init()) { |
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74 warning("BIS instructions are not available on this CPU"); |
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75 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 1); |
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76 } |
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77 |
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78 guarantee(VM_Version::has_v9(), "only SPARC v9 is supported"); |
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79 |
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80 assert(ArraycopySrcPrefetchDistance < 4096, "invalid value"); |
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81 if (ArraycopySrcPrefetchDistance >= 4096) |
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82 ArraycopySrcPrefetchDistance = 4064; |
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83 assert(ArraycopyDstPrefetchDistance < 4096, "invalid value"); |
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84 if (ArraycopyDstPrefetchDistance >= 4096) |
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85 ArraycopyDstPrefetchDistance = 4064; |
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86 |
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87 UseSSE = 0; // Only on x86 and x64 |
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88 |
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89 _supports_cx8 = has_v9(); |
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90 _supports_atomic_getset4 = true; // swap instruction |
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91 |
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92 // There are Fujitsu Sparc64 CPUs which support blk_init as well so |
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93 // we have to take this check out of the 'is_niagara()' block below. |
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94 if (has_blk_init()) { |
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95 // When using CMS or G1, we cannot use memset() in BOT updates |
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96 // because the sun4v/CMT version in libc_psr uses BIS which |
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97 // exposes "phantom zeros" to concurrent readers. See 6948537. |
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98 if (FLAG_IS_DEFAULT(UseMemSetInBOT) && (UseConcMarkSweepGC || UseG1GC)) { |
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99 FLAG_SET_DEFAULT(UseMemSetInBOT, false); |
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100 } |
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101 // Issue a stern warning if the user has explicitly set |
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102 // UseMemSetInBOT (it is known to cause issues), but allow |
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103 // use for experimentation and debugging. |
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104 if (UseConcMarkSweepGC || UseG1GC) { |
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105 if (UseMemSetInBOT) { |
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106 assert(!FLAG_IS_DEFAULT(UseMemSetInBOT), "Error"); |
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107 warning("Experimental flag -XX:+UseMemSetInBOT is known to cause instability" |
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108 " on sun4v; please understand that you are using at your own risk!"); |
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109 } |
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110 } |
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111 } |
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112 |
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113 if (is_niagara()) { |
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114 // Indirect branch is the same cost as direct |
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115 if (FLAG_IS_DEFAULT(UseInlineCaches)) { |
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116 FLAG_SET_DEFAULT(UseInlineCaches, false); |
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117 } |
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118 // Align loops on a single instruction boundary. |
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119 if (FLAG_IS_DEFAULT(OptoLoopAlignment)) { |
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120 FLAG_SET_DEFAULT(OptoLoopAlignment, 4); |
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121 } |
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122 #ifdef _LP64 |
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123 // 32-bit oops don't make sense for the 64-bit VM on sparc |
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124 // since the 32-bit VM has the same registers and smaller objects. |
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125 Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes); |
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126 Universe::set_narrow_klass_shift(LogKlassAlignmentInBytes); |
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127 #endif // _LP64 |
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128 #ifdef COMPILER2 |
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129 // Indirect branch is the same cost as direct |
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130 if (FLAG_IS_DEFAULT(UseJumpTables)) { |
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131 FLAG_SET_DEFAULT(UseJumpTables, true); |
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132 } |
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133 // Single-issue, so entry and loop tops are |
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134 // aligned on a single instruction boundary |
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135 if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) { |
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136 FLAG_SET_DEFAULT(InteriorEntryAlignment, 4); |
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137 } |
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138 if (is_niagara_plus()) { |
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139 if (has_blk_init() && UseTLAB && |
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140 FLAG_IS_DEFAULT(AllocatePrefetchInstr)) { |
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141 // Use BIS instruction for TLAB allocation prefetch. |
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142 FLAG_SET_ERGO(intx, AllocatePrefetchInstr, 1); |
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143 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) { |
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144 FLAG_SET_ERGO(intx, AllocatePrefetchStyle, 3); |
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145 } |
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146 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) { |
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147 // Use smaller prefetch distance with BIS |
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148 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64); |
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149 } |
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150 } |
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151 if (is_T4()) { |
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152 // Double number of prefetched cache lines on T4 |
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153 // since L2 cache line size is smaller (32 bytes). |
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154 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) { |
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155 FLAG_SET_ERGO(intx, AllocatePrefetchLines, AllocatePrefetchLines*2); |
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156 } |
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157 if (FLAG_IS_DEFAULT(AllocateInstancePrefetchLines)) { |
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158 FLAG_SET_ERGO(intx, AllocateInstancePrefetchLines, AllocateInstancePrefetchLines*2); |
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159 } |
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160 } |
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161 if (AllocatePrefetchStyle != 3 && FLAG_IS_DEFAULT(AllocatePrefetchDistance)) { |
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162 // Use different prefetch distance without BIS |
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163 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256); |
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164 } |
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165 if (AllocatePrefetchInstr == 1) { |
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166 // Need a space at the end of TLAB for BIS since it |
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167 // will fault when accessing memory outside of heap. |
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168 |
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169 // +1 for rounding up to next cache line, +1 to be safe |
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170 int lines = AllocatePrefetchLines + 2; |
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171 int step_size = AllocatePrefetchStepSize; |
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172 int distance = AllocatePrefetchDistance; |
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173 _reserve_for_allocation_prefetch = (distance + step_size*lines)/(int)HeapWordSize; |
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174 } |
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175 } |
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176 #endif |
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177 } |
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178 |
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179 // Use hardware population count instruction if available. |
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180 if (has_hardware_popc()) { |
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181 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) { |
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182 FLAG_SET_DEFAULT(UsePopCountInstruction, true); |
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183 } |
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184 } else if (UsePopCountInstruction) { |
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185 warning("POPC instruction is not available on this CPU"); |
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186 FLAG_SET_DEFAULT(UsePopCountInstruction, false); |
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187 } |
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188 |
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189 // T4 and newer Sparc cpus have new compare and branch instruction. |
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190 if (has_cbcond()) { |
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191 if (FLAG_IS_DEFAULT(UseCBCond)) { |
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192 FLAG_SET_DEFAULT(UseCBCond, true); |
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193 } |
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194 } else if (UseCBCond) { |
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195 warning("CBCOND instruction is not available on this CPU"); |
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196 FLAG_SET_DEFAULT(UseCBCond, false); |
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197 } |
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198 |
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199 assert(BlockZeroingLowLimit > 0, "invalid value"); |
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200 if (has_block_zeroing()) { |
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201 if (FLAG_IS_DEFAULT(UseBlockZeroing)) { |
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202 FLAG_SET_DEFAULT(UseBlockZeroing, true); |
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203 } |
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204 } else if (UseBlockZeroing) { |
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205 warning("BIS zeroing instructions are not available on this CPU"); |
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206 FLAG_SET_DEFAULT(UseBlockZeroing, false); |
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207 } |
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208 |
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209 assert(BlockCopyLowLimit > 0, "invalid value"); |
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210 if (has_block_zeroing()) { // has_blk_init() && is_T4(): core's local L2 cache |
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211 if (FLAG_IS_DEFAULT(UseBlockCopy)) { |
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212 FLAG_SET_DEFAULT(UseBlockCopy, true); |
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213 } |
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214 } else if (UseBlockCopy) { |
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215 warning("BIS instructions are not available or expensive on this CPU"); |
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216 FLAG_SET_DEFAULT(UseBlockCopy, false); |
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217 } |
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218 |
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219 #ifdef COMPILER2 |
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220 // T4 and newer Sparc cpus have fast RDPC. |
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221 if (has_fast_rdpc() && FLAG_IS_DEFAULT(UseRDPCForConstantTableBase)) { |
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222 FLAG_SET_DEFAULT(UseRDPCForConstantTableBase, true); |
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223 } |
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224 |
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225 // Currently not supported anywhere. |
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226 FLAG_SET_DEFAULT(UseFPUForSpilling, false); |
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227 |
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228 MaxVectorSize = 8; |
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229 |
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230 assert((InteriorEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size"); |
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231 #endif |
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232 |
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233 assert((CodeEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size"); |
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234 assert((OptoLoopAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size"); |
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235 |
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236 char buf[512]; |
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237 jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", |
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238 (has_v9() ? ", v9" : (has_v8() ? ", v8" : "")), |
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239 (has_hardware_popc() ? ", popc" : ""), |
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240 (has_vis1() ? ", vis1" : ""), |
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241 (has_vis2() ? ", vis2" : ""), |
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242 (has_vis3() ? ", vis3" : ""), |
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243 (has_blk_init() ? ", blk_init" : ""), |
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244 (has_cbcond() ? ", cbcond" : ""), |
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245 (has_aes() ? ", aes" : ""), |
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246 (is_ultra3() ? ", ultra3" : ""), |
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247 (is_sun4v() ? ", sun4v" : ""), |
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248 (is_niagara_plus() ? ", niagara_plus" : (is_niagara() ? ", niagara" : "")), |
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249 (is_sparc64() ? ", sparc64" : ""), |
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250 (!has_hardware_mul32() ? ", no-mul32" : ""), |
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251 (!has_hardware_div32() ? ", no-div32" : ""), |
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252 (!has_hardware_fsmuld() ? ", no-fsmuld" : "")); |
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253 |
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254 // buf is started with ", " or is empty |
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255 _features_str = strdup(strlen(buf) > 2 ? buf + 2 : buf); |
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256 |
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257 // UseVIS is set to the smallest of what hardware supports and what |
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258 // the command line requires. I.e., you cannot set UseVIS to 3 on |
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259 // older UltraSparc which do not support it. |
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260 if (UseVIS > 3) UseVIS=3; |
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261 if (UseVIS < 0) UseVIS=0; |
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262 if (!has_vis3()) // Drop to 2 if no VIS3 support |
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263 UseVIS = MIN2((intx)2,UseVIS); |
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264 if (!has_vis2()) // Drop to 1 if no VIS2 support |
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265 UseVIS = MIN2((intx)1,UseVIS); |
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266 if (!has_vis1()) // Drop to 0 if no VIS1 support |
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267 UseVIS = 0; |
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268 |
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269 // SPARC T4 and above should have support for AES instructions |
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270 if (has_aes()) { |
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271 if (UseVIS > 2) { // AES intrinsics use MOVxTOd/MOVdTOx which are VIS3 |
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272 if (FLAG_IS_DEFAULT(UseAES)) { |
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273 FLAG_SET_DEFAULT(UseAES, true); |
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274 } |
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275 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) { |
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276 FLAG_SET_DEFAULT(UseAESIntrinsics, true); |
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277 } |
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278 // we disable both the AES flags if either of them is disabled on the command line |
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279 if (!UseAES || !UseAESIntrinsics) { |
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280 FLAG_SET_DEFAULT(UseAES, false); |
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281 FLAG_SET_DEFAULT(UseAESIntrinsics, false); |
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282 } |
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283 } else { |
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284 if (UseAES || UseAESIntrinsics) { |
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285 warning("SPARC AES intrinsics require VIS3 instruction support. Intrinsics will be disabled."); |
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286 if (UseAES) { |
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287 FLAG_SET_DEFAULT(UseAES, false); |
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288 } |
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289 if (UseAESIntrinsics) { |
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290 FLAG_SET_DEFAULT(UseAESIntrinsics, false); |
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291 } |
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292 } |
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293 } |
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294 } else if (UseAES || UseAESIntrinsics) { |
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295 warning("AES instructions are not available on this CPU"); |
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296 if (UseAES) { |
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297 FLAG_SET_DEFAULT(UseAES, false); |
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298 } |
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299 if (UseAESIntrinsics) { |
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300 FLAG_SET_DEFAULT(UseAESIntrinsics, false); |
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301 } |
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302 } |
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303 |
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304 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) && |
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305 (cache_line_size > ContendedPaddingWidth)) |
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306 ContendedPaddingWidth = cache_line_size; |
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307 |
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308 #ifndef PRODUCT |
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309 if (PrintMiscellaneous && Verbose) { |
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310 tty->print("Allocation"); |
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311 if (AllocatePrefetchStyle <= 0) { |
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312 tty->print_cr(": no prefetching"); |
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313 } else { |
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314 tty->print(" prefetching: "); |
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315 if (AllocatePrefetchInstr == 0) { |
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316 tty->print("PREFETCH"); |
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317 } else if (AllocatePrefetchInstr == 1) { |
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318 tty->print("BIS"); |
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319 } |
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320 if (AllocatePrefetchLines > 1) { |
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321 tty->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize); |
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322 } else { |
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323 tty->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize); |
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324 } |
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325 } |
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326 if (PrefetchCopyIntervalInBytes > 0) { |
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327 tty->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes); |
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328 } |
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329 if (PrefetchScanIntervalInBytes > 0) { |
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330 tty->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes); |
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331 } |
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332 if (PrefetchFieldsAhead > 0) { |
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333 tty->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead); |
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334 } |
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335 if (ContendedPaddingWidth > 0) { |
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336 tty->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth); |
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337 } |
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338 } |
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339 #endif // PRODUCT |
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340 } |
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341 |
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342 void VM_Version::print_features() { |
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343 tty->print_cr("Version:%s", cpu_features()); |
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344 } |
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345 |
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346 int VM_Version::determine_features() { |
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347 if (UseV8InstrsOnly) { |
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348 NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-V8");) |
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349 return generic_v8_m; |
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350 } |
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351 |
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352 int features = platform_features(unknown_m); // platform_features() is os_arch specific |
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353 |
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354 if (features == unknown_m) { |
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355 features = generic_v9_m; |
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356 warning("Cannot recognize SPARC version. Default to V9"); |
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357 } |
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358 |
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359 assert(is_T_family(features) == is_niagara(features), "Niagara should be T series"); |
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360 if (UseNiagaraInstrs) { // Force code generation for Niagara |
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361 if (is_T_family(features)) { |
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362 // Happy to accomodate... |
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363 } else { |
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364 NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-Niagara");) |
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365 features |= T_family_m; |
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366 } |
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367 } else { |
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368 if (is_T_family(features) && !FLAG_IS_DEFAULT(UseNiagaraInstrs)) { |
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369 NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-Not-Niagara");) |
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370 features &= ~(T_family_m | T1_model_m); |
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371 } else { |
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372 // Happy to accomodate... |
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373 } |
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374 } |
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375 |
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376 return features; |
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377 } |
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378 |
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379 static int saved_features = 0; |
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380 |
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381 void VM_Version::allow_all() { |
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382 saved_features = _features; |
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383 _features = all_features_m; |
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384 } |
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385 |
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386 void VM_Version::revert() { |
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387 _features = saved_features; |
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388 } |
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389 |
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390 unsigned int VM_Version::calc_parallel_worker_threads() { |
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391 unsigned int result; |
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392 if (is_M_series()) { |
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393 // for now, use same gc thread calculation for M-series as for niagara-plus |
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394 // in future, we may want to tweak parameters for nof_parallel_worker_thread |
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395 result = nof_parallel_worker_threads(5, 16, 8); |
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396 } else if (is_niagara_plus()) { |
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397 result = nof_parallel_worker_threads(5, 16, 8); |
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398 } else { |
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399 result = nof_parallel_worker_threads(5, 8, 8); |
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400 } |
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401 return result; |
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402 } |