src/cpu/x86/vm/x86_32.ad

changeset 6506
f040cf9fc9c0
parent 6489
50fdb38839eb
parent 6288
984401824c5e
child 6517
a433eb716ce1
equal deleted inserted replaced
6505:2fcab8ba885a 6506:f040cf9fc9c0
3895 op_cost(10); 3895 op_cost(10);
3896 format %{ %} 3896 format %{ %}
3897 interface(CONST_INTER); 3897 interface(CONST_INTER);
3898 %} 3898 %}
3899 3899
3900 // Int Immediate non-negative
3901 operand immU31()
3902 %{
3903 predicate(n->get_int() >= 0);
3904 match(ConI);
3905
3906 op_cost(0);
3907 format %{ %}
3908 interface(CONST_INTER);
3909 %}
3910
3900 // Constant for long shifts 3911 // Constant for long shifts
3901 operand immI_32() %{ 3912 operand immI_32() %{
3902 predicate( n->get_int() == 32 ); 3913 predicate( n->get_int() == 32 );
3903 match(ConI); 3914 match(ConI);
3904 3915
6125 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); 6136 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6126 %} 6137 %}
6127 ins_pipe(ialu_reg_mem); 6138 ins_pipe(ialu_reg_mem);
6128 %} 6139 %}
6129 6140
6130 // Load Integer with 32-bit mask into Long Register 6141 // Load Integer with 31-bit mask into Long Register
6131 instruct loadI2L_immI(eRegL dst, memory mem, immI mask, eFlagsReg cr) %{ 6142 instruct loadI2L_immU31(eRegL dst, memory mem, immU31 mask, eFlagsReg cr) %{
6132 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 6143 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6133 effect(KILL cr); 6144 effect(KILL cr);
6134 6145
6135 format %{ "MOV $dst.lo,$mem\t# int & 32-bit mask -> long\n\t" 6146 format %{ "MOV $dst.lo,$mem\t# int & 31-bit mask -> long\n\t"
6136 "XOR $dst.hi,$dst.hi\n\t" 6147 "XOR $dst.hi,$dst.hi\n\t"
6137 "AND $dst.lo,$mask" %} 6148 "AND $dst.lo,$mask" %}
6138 ins_encode %{ 6149 ins_encode %{
6139 Register Rdst = $dst$$Register; 6150 Register Rdst = $dst$$Register;
6140 __ movl(Rdst, $mem$$Address); 6151 __ movl(Rdst, $mem$$Address);

mercurial