72 if ((AllocatePrefetchDistance % AllocatePrefetchStepSize) != 0 || |
72 if ((AllocatePrefetchDistance % AllocatePrefetchStepSize) != 0 || |
73 (AllocatePrefetchDistance <= 0)) { |
73 (AllocatePrefetchDistance <= 0)) { |
74 AllocatePrefetchDistance = AllocatePrefetchStepSize; |
74 AllocatePrefetchDistance = AllocatePrefetchStepSize; |
75 } |
75 } |
76 |
76 |
77 if (AllocatePrefetchStyle == 3 && (!has_blk_init() || cache_line_size <= 0)) { |
77 if (AllocatePrefetchStyle == 3 && !has_blk_init()) { |
78 warning("BIS instructions are not available on this CPU"); |
78 warning("BIS instructions are not available on this CPU"); |
79 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 1); |
79 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 1); |
80 } |
80 } |
81 |
81 |
82 assert(ArraycopySrcPrefetchDistance < 4096, "invalid value"); |
82 assert(ArraycopySrcPrefetchDistance < 4096, "invalid value"); |
136 // aligned on a single instruction boundary |
136 // aligned on a single instruction boundary |
137 if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) { |
137 if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) { |
138 FLAG_SET_DEFAULT(InteriorEntryAlignment, 4); |
138 FLAG_SET_DEFAULT(InteriorEntryAlignment, 4); |
139 } |
139 } |
140 if (is_niagara_plus()) { |
140 if (is_niagara_plus()) { |
141 if (has_blk_init() && (cache_line_size > 0) && UseTLAB && |
141 if (has_blk_init() && UseTLAB && |
142 FLAG_IS_DEFAULT(AllocatePrefetchInstr)) { |
142 FLAG_IS_DEFAULT(AllocatePrefetchInstr)) { |
143 // Use BIS instruction for TLAB allocation prefetch. |
143 // Use BIS instruction for TLAB allocation prefetch. |
144 FLAG_SET_ERGO(intx, AllocatePrefetchInstr, 1); |
144 FLAG_SET_ERGO(intx, AllocatePrefetchInstr, 1); |
145 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) { |
145 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) { |
146 FLAG_SET_ERGO(intx, AllocatePrefetchStyle, 3); |
146 FLAG_SET_ERGO(intx, AllocatePrefetchStyle, 3); |