src/cpu/sparc/vm/sparc.ad

changeset 5001
e10e43e58e92
parent 5000
a6e09d6dd8e5
parent 4944
886d1fd67dc3
child 5283
46c544b8fbfc
equal deleted inserted replaced
5000:a6e09d6dd8e5 5001:e10e43e58e92
1 // 1 //
2 // Copyright (c) 1998, 2012, Oracle and/or its affiliates. All rights reserved. 2 // Copyright (c) 1998, 2013, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 // 4 //
5 // This code is free software; you can redistribute it and/or modify it 5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as 6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation. 7 // published by the Free Software Foundation.
8174 ins_cost(DEFAULT_COST*3); 8174 ins_cost(DEFAULT_COST*3);
8175 8175
8176 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t" 8176 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t"
8177 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t" 8177 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t"
8178 "MOVlt $tmp,$p\t! p' < 0 ? p'+y : p'" %} 8178 "MOVlt $tmp,$p\t! p' < 0 ? p'+y : p'" %}
8179 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) ); 8179 ins_encode(enc_cadd_cmpLTMask(p, q, y, tmp));
8180 ins_pipe( cadd_cmpltmask ); 8180 ins_pipe(cadd_cmpltmask);
8181 %} 8181 %}
8182 8182
8183 instruct and_cmpLTMask(iRegI p, iRegI q, iRegI y, flagsReg ccr) %{
8184 match(Set p (AndI (CmpLTMask p q) y));
8185 effect(KILL ccr);
8186 ins_cost(DEFAULT_COST*3);
8187
8188 format %{ "CMP $p,$q\n\t"
8189 "MOV $y,$p\n\t"
8190 "MOVge G0,$p" %}
8191 ins_encode %{
8192 __ cmp($p$$Register, $q$$Register);
8193 __ mov($y$$Register, $p$$Register);
8194 __ movcc(Assembler::greaterEqual, false, Assembler::icc, G0, $p$$Register);
8195 %}
8196 ins_pipe(ialu_reg_reg_ialu);
8197 %}
8183 8198
8184 //----------------------------------------------------------------- 8199 //-----------------------------------------------------------------
8185 // Direct raw moves between float and general registers using VIS3. 8200 // Direct raw moves between float and general registers using VIS3.
8186 8201
8187 // ins_pipe(faddF_reg); 8202 // ins_pipe(faddF_reg);

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