src/cpu/sparc/vm/vm_version_sparc.hpp

changeset 7135
d635fd1ac81c
parent 7027
b20a35eae442
child 7535
7ae4e26cb1e0
child 7767
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equal deleted inserted replaced
7133:2219e830b668 7135:d635fd1ac81c
94 }; 94 };
95 95
96 static int _features; 96 static int _features;
97 static const char* _features_str; 97 static const char* _features_str;
98 98
99 static unsigned int _L2_cache_line_size;
100 static unsigned int L2_cache_line_size() { return _L2_cache_line_size; }
101
99 static void print_features(); 102 static void print_features();
100 static int determine_features(); 103 static int determine_features();
101 static int platform_features(int features); 104 static int platform_features(int features);
102 105
103 // Returns true if the platform is in the niagara line (T series) 106 // Returns true if the platform is in the niagara line (T series)
165 // On T4 and newer Sparc BIS to the beginning of cache line always zeros it. 168 // On T4 and newer Sparc BIS to the beginning of cache line always zeros it.
166 static bool has_block_zeroing() { return has_blk_init() && is_T4(); } 169 static bool has_block_zeroing() { return has_blk_init() && is_T4(); }
167 170
168 static const char* cpu_features() { return _features_str; } 171 static const char* cpu_features() { return _features_str; }
169 172
170 static intx prefetch_data_size() { 173 // default prefetch block size on sparc
171 return is_T4() && !is_T7() ? 32 : 64; // default prefetch block size on sparc 174 static intx prefetch_data_size() { return L2_cache_line_size(); }
172 }
173 175
174 // Prefetch 176 // Prefetch
175 static intx prefetch_copy_interval_in_bytes() { 177 static intx prefetch_copy_interval_in_bytes() {
176 intx interval = PrefetchCopyIntervalInBytes; 178 intx interval = PrefetchCopyIntervalInBytes;
177 return interval >= 0 ? interval : (has_v9() ? 512 : 0); 179 return interval >= 0 ? interval : (has_v9() ? 512 : 0);

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