26 #define CPU_X86_VM_ASSEMBLER_X86_INLINE_HPP |
26 #define CPU_X86_VM_ASSEMBLER_X86_INLINE_HPP |
27 |
27 |
28 #include "asm/assembler.inline.hpp" |
28 #include "asm/assembler.inline.hpp" |
29 #include "asm/codeBuffer.hpp" |
29 #include "asm/codeBuffer.hpp" |
30 #include "code/codeCache.hpp" |
30 #include "code/codeCache.hpp" |
31 #include "runtime/handles.inline.hpp" |
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32 |
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33 inline void MacroAssembler::pd_patch_instruction(address branch, address target) { |
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34 unsigned char op = branch[0]; |
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35 assert(op == 0xE8 /* call */ || |
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36 op == 0xE9 /* jmp */ || |
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37 op == 0xEB /* short jmp */ || |
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38 (op & 0xF0) == 0x70 /* short jcc */ || |
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39 op == 0x0F && (branch[1] & 0xF0) == 0x80 /* jcc */, |
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40 "Invalid opcode at patch point"); |
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41 |
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42 if (op == 0xEB || (op & 0xF0) == 0x70) { |
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43 // short offset operators (jmp and jcc) |
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44 char* disp = (char*) &branch[1]; |
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45 int imm8 = target - (address) &disp[1]; |
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46 guarantee(this->is8bit(imm8), "Short forward jump exceeds 8-bit offset"); |
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47 *disp = imm8; |
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48 } else { |
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49 int* disp = (int*) &branch[(op == 0x0F)? 2: 1]; |
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50 int imm32 = target - (address) &disp[1]; |
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51 *disp = imm32; |
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52 } |
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53 } |
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54 |
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55 #ifndef PRODUCT |
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56 inline void MacroAssembler::pd_print_patched_instruction(address branch) { |
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57 const char* s; |
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58 unsigned char op = branch[0]; |
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59 if (op == 0xE8) { |
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60 s = "call"; |
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61 } else if (op == 0xE9 || op == 0xEB) { |
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62 s = "jmp"; |
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63 } else if ((op & 0xF0) == 0x70) { |
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64 s = "jcc"; |
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65 } else if (op == 0x0F) { |
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66 s = "jcc"; |
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67 } else { |
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68 s = "????"; |
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69 } |
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70 tty->print("%s (unresolved)", s); |
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71 } |
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72 #endif // ndef PRODUCT |
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73 |
31 |
74 #ifndef _LP64 |
32 #ifndef _LP64 |
75 inline int Assembler::prefix_and_encode(int reg_enc, bool byteinst) { return reg_enc; } |
33 inline int Assembler::prefix_and_encode(int reg_enc, bool byteinst) { return reg_enc; } |
76 inline int Assembler::prefixq_and_encode(int reg_enc) { return reg_enc; } |
34 inline int Assembler::prefixq_and_encode(int reg_enc) { return reg_enc; } |
77 |
35 |