src/cpu/mips/vm/macroAssembler_mips.cpp

changeset 8004
941851413ebf
parent 8002
f543ff2cabcf
child 8006
b70d88852ac9
equal deleted inserted replaced
8003:8363e2ada4b5 8004:941851413ebf
1620 void MacroAssembler::g1_write_barrier_post(Register store_addr, 1620 void MacroAssembler::g1_write_barrier_post(Register store_addr,
1621 Register new_val, 1621 Register new_val,
1622 Register thread, 1622 Register thread,
1623 Register tmp, 1623 Register tmp,
1624 Register tmp2) { 1624 Register tmp2) {
1625 assert(tmp == AT, "must be"); 1625 assert(tmp != AT, "must be");
1626 assert(tmp2 == AT, "must be"); 1626 assert(tmp2 != AT, "must be");
1627 #ifdef _LP64 1627 #ifdef _LP64
1628 assert(thread == TREG, "must be"); 1628 assert(thread == TREG, "must be");
1629 #endif // _LP64 1629 #endif // _LP64
1630 1630
1631 Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() + 1631 Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() +

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