src/cpu/mips/vm/sharedRuntime_mips_64.cpp

changeset 9759
8c71022cf5f3
parent 9705
0b27fc8adf1b
child 9932
86ea9a02a717
equal deleted inserted replaced
9758:122547cfa3c8 9759:8c71022cf5f3
1268 static void float_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { 1268 static void float_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1269 assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move"); 1269 assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move");
1270 1270
1271 if (src.first()->is_stack()) { 1271 if (src.first()->is_stack()) {
1272 if (dst.first()->is_stack()) { 1272 if (dst.first()->is_stack()) {
1273 __ lwc1(F12, FP, reg2offset_in(src.first())); 1273 __ lw(AT, FP, reg2offset_in(src.first()));
1274 __ swc1(F12, SP, reg2offset_out(dst.first())); 1274 __ sw(AT, SP, reg2offset_out(dst.first()));
1275 } 1275 }
1276 else 1276 else
1277 __ lwc1(dst.first()->as_FloatRegister(), FP, reg2offset_in(src.first())); 1277 __ lwc1(dst.first()->as_FloatRegister(), FP, reg2offset_in(src.first()));
1278 } else { 1278 } else {
1279 // reg to stack 1279 // reg to stack
1322 1322
1323 1323
1324 if (src.first()->is_stack()) { 1324 if (src.first()->is_stack()) {
1325 // source is all stack 1325 // source is all stack
1326 if( dst.first()->is_stack()){ 1326 if( dst.first()->is_stack()){
1327 __ ldc1(F12, FP, reg2offset_in(src.first())); 1327 __ ld(AT, FP, reg2offset_in(src.first()));
1328 1328 __ sd(AT, SP, reg2offset_out(dst.first()));
1329 __ sdc1(F12, SP, reg2offset_out(dst.first()));
1330 } else { 1329 } else {
1331 __ ldc1( (dst.first())->as_FloatRegister(), FP, reg2offset_in(src.first())); 1330 __ ldc1( (dst.first())->as_FloatRegister(), FP, reg2offset_in(src.first()));
1332 } 1331 }
1333 1332
1334 } else { 1333 } else {

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