8610 ins_encode(REX_mem(dst), OpcSE(src), |
8636 ins_encode(REX_mem(dst), OpcSE(src), |
8611 RM_opc_mem(secondary, dst), Con8or32(src)); |
8637 RM_opc_mem(secondary, dst), Con8or32(src)); |
8612 ins_pipe(ialu_mem_imm); |
8638 ins_pipe(ialu_mem_imm); |
8613 %} |
8639 %} |
8614 |
8640 |
|
8641 // BMI1 instructions |
|
8642 instruct andnI_rReg_rReg_mem(rRegI dst, rRegI src1, memory src2, immI_M1 minus_1, rFlagsReg cr) %{ |
|
8643 match(Set dst (AndI (XorI src1 minus_1) (LoadI src2))); |
|
8644 predicate(UseBMI1Instructions); |
|
8645 effect(KILL cr); |
|
8646 |
|
8647 ins_cost(125); |
|
8648 format %{ "andnl $dst, $src1, $src2" %} |
|
8649 |
|
8650 ins_encode %{ |
|
8651 __ andnl($dst$$Register, $src1$$Register, $src2$$Address); |
|
8652 %} |
|
8653 ins_pipe(ialu_reg_mem); |
|
8654 %} |
|
8655 |
|
8656 instruct andnI_rReg_rReg_rReg(rRegI dst, rRegI src1, rRegI src2, immI_M1 minus_1, rFlagsReg cr) %{ |
|
8657 match(Set dst (AndI (XorI src1 minus_1) src2)); |
|
8658 predicate(UseBMI1Instructions); |
|
8659 effect(KILL cr); |
|
8660 |
|
8661 format %{ "andnl $dst, $src1, $src2" %} |
|
8662 |
|
8663 ins_encode %{ |
|
8664 __ andnl($dst$$Register, $src1$$Register, $src2$$Register); |
|
8665 %} |
|
8666 ins_pipe(ialu_reg); |
|
8667 %} |
|
8668 |
|
8669 instruct blsiI_rReg_rReg(rRegI dst, rRegI src, immI0 imm_zero, rFlagsReg cr) %{ |
|
8670 match(Set dst (AndI (SubI imm_zero src) src)); |
|
8671 predicate(UseBMI1Instructions); |
|
8672 effect(KILL cr); |
|
8673 |
|
8674 format %{ "blsil $dst, $src" %} |
|
8675 |
|
8676 ins_encode %{ |
|
8677 __ blsil($dst$$Register, $src$$Register); |
|
8678 %} |
|
8679 ins_pipe(ialu_reg); |
|
8680 %} |
|
8681 |
|
8682 instruct blsiI_rReg_mem(rRegI dst, memory src, immI0 imm_zero, rFlagsReg cr) %{ |
|
8683 match(Set dst (AndI (SubI imm_zero (LoadI src) ) (LoadI src) )); |
|
8684 predicate(UseBMI1Instructions); |
|
8685 effect(KILL cr); |
|
8686 |
|
8687 ins_cost(125); |
|
8688 format %{ "blsil $dst, $src" %} |
|
8689 |
|
8690 ins_encode %{ |
|
8691 __ blsil($dst$$Register, $src$$Address); |
|
8692 %} |
|
8693 ins_pipe(ialu_reg_mem); |
|
8694 %} |
|
8695 |
|
8696 instruct blsmskI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr) |
|
8697 %{ |
|
8698 match(Set dst (XorI (AddI (LoadI src) minus_1) (LoadI src) ) ); |
|
8699 predicate(UseBMI1Instructions); |
|
8700 effect(KILL cr); |
|
8701 |
|
8702 ins_cost(125); |
|
8703 format %{ "blsmskl $dst, $src" %} |
|
8704 |
|
8705 ins_encode %{ |
|
8706 __ blsmskl($dst$$Register, $src$$Address); |
|
8707 %} |
|
8708 ins_pipe(ialu_reg_mem); |
|
8709 %} |
|
8710 |
|
8711 instruct blsmskI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr) |
|
8712 %{ |
|
8713 match(Set dst (XorI (AddI src minus_1) src)); |
|
8714 predicate(UseBMI1Instructions); |
|
8715 effect(KILL cr); |
|
8716 |
|
8717 format %{ "blsmskl $dst, $src" %} |
|
8718 |
|
8719 ins_encode %{ |
|
8720 __ blsmskl($dst$$Register, $src$$Register); |
|
8721 %} |
|
8722 |
|
8723 ins_pipe(ialu_reg); |
|
8724 %} |
|
8725 |
|
8726 instruct blsrI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr) |
|
8727 %{ |
|
8728 match(Set dst (AndI (AddI src minus_1) src) ); |
|
8729 predicate(UseBMI1Instructions); |
|
8730 effect(KILL cr); |
|
8731 |
|
8732 format %{ "blsrl $dst, $src" %} |
|
8733 |
|
8734 ins_encode %{ |
|
8735 __ blsrl($dst$$Register, $src$$Register); |
|
8736 %} |
|
8737 |
|
8738 ins_pipe(ialu_reg_mem); |
|
8739 %} |
|
8740 |
|
8741 instruct blsrI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr) |
|
8742 %{ |
|
8743 match(Set dst (AndI (AddI (LoadI src) minus_1) (LoadI src) ) ); |
|
8744 predicate(UseBMI1Instructions); |
|
8745 effect(KILL cr); |
|
8746 |
|
8747 ins_cost(125); |
|
8748 format %{ "blsrl $dst, $src" %} |
|
8749 |
|
8750 ins_encode %{ |
|
8751 __ blsrl($dst$$Register, $src$$Address); |
|
8752 %} |
|
8753 |
|
8754 ins_pipe(ialu_reg); |
|
8755 %} |
|
8756 |
8615 // Or Instructions |
8757 // Or Instructions |
8616 // Or Register with Register |
8758 // Or Register with Register |
8617 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr) |
8759 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr) |
8618 %{ |
8760 %{ |
8619 match(Set dst (OrI dst src)); |
8761 match(Set dst (OrI dst src)); |
8839 format %{ "andq $dst, $src\t# long" %} |
8981 format %{ "andq $dst, $src\t# long" %} |
8840 opcode(0x81, 0x4); /* Opcode 81 /4 id */ |
8982 opcode(0x81, 0x4); /* Opcode 81 /4 id */ |
8841 ins_encode(REX_mem_wide(dst), OpcSE(src), |
8983 ins_encode(REX_mem_wide(dst), OpcSE(src), |
8842 RM_opc_mem(secondary, dst), Con8or32(src)); |
8984 RM_opc_mem(secondary, dst), Con8or32(src)); |
8843 ins_pipe(ialu_mem_imm); |
8985 ins_pipe(ialu_mem_imm); |
|
8986 %} |
|
8987 |
|
8988 // BMI1 instructions |
|
8989 instruct andnL_rReg_rReg_mem(rRegL dst, rRegL src1, memory src2, immL_M1 minus_1, rFlagsReg cr) %{ |
|
8990 match(Set dst (AndL (XorL src1 minus_1) (LoadL src2))); |
|
8991 predicate(UseBMI1Instructions); |
|
8992 effect(KILL cr); |
|
8993 |
|
8994 ins_cost(125); |
|
8995 format %{ "andnq $dst, $src1, $src2" %} |
|
8996 |
|
8997 ins_encode %{ |
|
8998 __ andnq($dst$$Register, $src1$$Register, $src2$$Address); |
|
8999 %} |
|
9000 ins_pipe(ialu_reg_mem); |
|
9001 %} |
|
9002 |
|
9003 instruct andnL_rReg_rReg_rReg(rRegL dst, rRegL src1, rRegL src2, immL_M1 minus_1, rFlagsReg cr) %{ |
|
9004 match(Set dst (AndL (XorL src1 minus_1) src2)); |
|
9005 predicate(UseBMI1Instructions); |
|
9006 effect(KILL cr); |
|
9007 |
|
9008 format %{ "andnq $dst, $src1, $src2" %} |
|
9009 |
|
9010 ins_encode %{ |
|
9011 __ andnq($dst$$Register, $src1$$Register, $src2$$Register); |
|
9012 %} |
|
9013 ins_pipe(ialu_reg_mem); |
|
9014 %} |
|
9015 |
|
9016 instruct blsiL_rReg_rReg(rRegL dst, rRegL src, immL0 imm_zero, rFlagsReg cr) %{ |
|
9017 match(Set dst (AndL (SubL imm_zero src) src)); |
|
9018 predicate(UseBMI1Instructions); |
|
9019 effect(KILL cr); |
|
9020 |
|
9021 format %{ "blsiq $dst, $src" %} |
|
9022 |
|
9023 ins_encode %{ |
|
9024 __ blsiq($dst$$Register, $src$$Register); |
|
9025 %} |
|
9026 ins_pipe(ialu_reg); |
|
9027 %} |
|
9028 |
|
9029 instruct blsiL_rReg_mem(rRegL dst, memory src, immL0 imm_zero, rFlagsReg cr) %{ |
|
9030 match(Set dst (AndL (SubL imm_zero (LoadL src) ) (LoadL src) )); |
|
9031 predicate(UseBMI1Instructions); |
|
9032 effect(KILL cr); |
|
9033 |
|
9034 ins_cost(125); |
|
9035 format %{ "blsiq $dst, $src" %} |
|
9036 |
|
9037 ins_encode %{ |
|
9038 __ blsiq($dst$$Register, $src$$Address); |
|
9039 %} |
|
9040 ins_pipe(ialu_reg_mem); |
|
9041 %} |
|
9042 |
|
9043 instruct blsmskL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr) |
|
9044 %{ |
|
9045 match(Set dst (XorL (AddL (LoadL src) minus_1) (LoadL src) ) ); |
|
9046 predicate(UseBMI1Instructions); |
|
9047 effect(KILL cr); |
|
9048 |
|
9049 ins_cost(125); |
|
9050 format %{ "blsmskq $dst, $src" %} |
|
9051 |
|
9052 ins_encode %{ |
|
9053 __ blsmskq($dst$$Register, $src$$Address); |
|
9054 %} |
|
9055 ins_pipe(ialu_reg_mem); |
|
9056 %} |
|
9057 |
|
9058 instruct blsmskL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr) |
|
9059 %{ |
|
9060 match(Set dst (XorL (AddL src minus_1) src)); |
|
9061 predicate(UseBMI1Instructions); |
|
9062 effect(KILL cr); |
|
9063 |
|
9064 format %{ "blsmskq $dst, $src" %} |
|
9065 |
|
9066 ins_encode %{ |
|
9067 __ blsmskq($dst$$Register, $src$$Register); |
|
9068 %} |
|
9069 |
|
9070 ins_pipe(ialu_reg); |
|
9071 %} |
|
9072 |
|
9073 instruct blsrL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr) |
|
9074 %{ |
|
9075 match(Set dst (AndL (AddL src minus_1) src) ); |
|
9076 predicate(UseBMI1Instructions); |
|
9077 effect(KILL cr); |
|
9078 |
|
9079 format %{ "blsrq $dst, $src" %} |
|
9080 |
|
9081 ins_encode %{ |
|
9082 __ blsrq($dst$$Register, $src$$Register); |
|
9083 %} |
|
9084 |
|
9085 ins_pipe(ialu_reg); |
|
9086 %} |
|
9087 |
|
9088 instruct blsrL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr) |
|
9089 %{ |
|
9090 match(Set dst (AndL (AddL (LoadL src) minus_1) (LoadL src)) ); |
|
9091 predicate(UseBMI1Instructions); |
|
9092 effect(KILL cr); |
|
9093 |
|
9094 ins_cost(125); |
|
9095 format %{ "blsrq $dst, $src" %} |
|
9096 |
|
9097 ins_encode %{ |
|
9098 __ blsrq($dst$$Register, $src$$Address); |
|
9099 %} |
|
9100 |
|
9101 ins_pipe(ialu_reg); |
8844 %} |
9102 %} |
8845 |
9103 |
8846 // Or Instructions |
9104 // Or Instructions |
8847 // Or Register with Register |
9105 // Or Register with Register |
8848 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr) |
9106 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr) |