2573 emit_int8(0x73); |
2573 emit_int8(0x73); |
2574 emit_int8((unsigned char)(0xC0 | encode)); |
2574 emit_int8((unsigned char)(0xC0 | encode)); |
2575 emit_int8(shift); |
2575 emit_int8(shift); |
2576 } |
2576 } |
2577 |
2577 |
|
2578 void Assembler::pslldq(XMMRegister dst, int shift) { |
|
2579 // Shift left 128 bit value in xmm register by number of bytes. |
|
2580 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
2581 int encode = simd_prefix_and_encode(xmm7, dst, dst, VEX_SIMD_66); |
|
2582 emit_int8(0x73); |
|
2583 emit_int8((unsigned char)(0xC0 | encode)); |
|
2584 emit_int8(shift); |
|
2585 } |
|
2586 |
2578 void Assembler::ptest(XMMRegister dst, Address src) { |
2587 void Assembler::ptest(XMMRegister dst, Address src) { |
2579 assert(VM_Version::supports_sse4_1(), ""); |
2588 assert(VM_Version::supports_sse4_1(), ""); |
2580 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); |
2589 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); |
2581 InstructionMark im(this); |
2590 InstructionMark im(this); |
2582 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); |
2591 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); |