src/cpu/sparc/vm/assembler_sparc.hpp

changeset 9806
758c07667682
parent 7535
7ae4e26cb1e0
parent 9788
44ef77ad417c
equal deleted inserted replaced
9762:c97db0855565 9806:758c07667682
1 /* 1 /*
2 * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. 2 * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 * 4 *
5 * This code is free software; you can redistribute it and/or modify it 5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as 6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation. 7 * published by the Free Software Foundation.
127 alignaddr_op3 = 0x36, 127 alignaddr_op3 = 0x36,
128 faligndata_op3 = 0x36, 128 faligndata_op3 = 0x36,
129 flog3_op3 = 0x36, 129 flog3_op3 = 0x36,
130 edge_op3 = 0x36, 130 edge_op3 = 0x36,
131 fsrc_op3 = 0x36, 131 fsrc_op3 = 0x36,
132 xmulx_op3 = 0x36,
132 impdep2_op3 = 0x37, 133 impdep2_op3 = 0x37,
133 stpartialf_op3 = 0x37, 134 stpartialf_op3 = 0x37,
134 jmpl_op3 = 0x38, 135 jmpl_op3 = 0x38,
135 rett_op3 = 0x39, 136 rett_op3 = 0x39,
136 trap_op3 = 0x3a, 137 trap_op3 = 0x3a,
218 fdtoi_opf = 0xd2, 219 fdtoi_opf = 0xd2,
219 220
220 mdtox_opf = 0x110, 221 mdtox_opf = 0x110,
221 mstouw_opf = 0x111, 222 mstouw_opf = 0x111,
222 mstosw_opf = 0x113, 223 mstosw_opf = 0x113,
224 xmulx_opf = 0x115,
225 xmulxhi_opf = 0x116,
223 mxtod_opf = 0x118, 226 mxtod_opf = 0x118,
224 mwtos_opf = 0x119, 227 mwtos_opf = 0x119,
225 228
226 aes_kexpand0_opf = 0x130, 229 aes_kexpand0_opf = 0x130,
227 aes_kexpand2_opf = 0x131, 230 aes_kexpand2_opf = 0x131,
1210 void movdtox( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mdtox_opf) | fs2(s, FloatRegisterImpl::D)); } 1213 void movdtox( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mdtox_opf) | fs2(s, FloatRegisterImpl::D)); }
1211 1214
1212 void movwtos( Register s, FloatRegister d ) { vis3_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::S) | op3(mftoi_op3) | opf(mwtos_opf) | rs2(s)); } 1215 void movwtos( Register s, FloatRegister d ) { vis3_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::S) | op3(mftoi_op3) | opf(mwtos_opf) | rs2(s)); }
1213 void movxtod( Register s, FloatRegister d ) { vis3_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(mftoi_op3) | opf(mxtod_opf) | rs2(s)); } 1216 void movxtod( Register s, FloatRegister d ) { vis3_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(mftoi_op3) | opf(mxtod_opf) | rs2(s)); }
1214 1217
1218 void xmulx(Register s1, Register s2, Register d) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(xmulx_op3) | rs1(s1) | opf(xmulx_opf) | rs2(s2)); }
1219 void xmulxhi(Register s1, Register s2, Register d) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(xmulx_op3) | rs1(s1) | opf(xmulxhi_opf) | rs2(s2)); }
1220
1215 // Crypto SHA instructions 1221 // Crypto SHA instructions
1216 1222
1217 void sha1() { sha1_only(); emit_int32( op(arith_op) | op3(sha_op3) | opf(sha1_opf)); } 1223 void sha1() { sha1_only(); emit_int32( op(arith_op) | op3(sha_op3) | opf(sha1_opf)); }
1218 void sha256() { sha256_only(); emit_int32( op(arith_op) | op3(sha_op3) | opf(sha256_opf)); } 1224 void sha256() { sha256_only(); emit_int32( op(arith_op) | op3(sha_op3) | opf(sha256_opf)); }
1219 void sha512() { sha512_only(); emit_int32( op(arith_op) | op3(sha_op3) | opf(sha512_opf)); } 1225 void sha512() { sha512_only(); emit_int32( op(arith_op) | op3(sha_op3) | opf(sha512_opf)); }

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