23 */ |
23 */ |
24 |
24 |
25 #include "incls/_precompiled.incl" |
25 #include "incls/_precompiled.incl" |
26 #include "incls/_assembler_sparc.cpp.incl" |
26 #include "incls/_assembler_sparc.cpp.incl" |
27 |
27 |
28 // Implementation of Address |
28 // Convert the raw encoding form into the form expected by the |
29 |
29 // constructor for Address. |
30 Address::Address( addr_type t, int which ) { |
30 Address Address::make_raw(int base, int index, int scale, int disp, bool disp_is_oop) { |
31 switch (t) { |
31 assert(scale == 0, "not supported"); |
32 case extra_in_argument: |
32 RelocationHolder rspec; |
33 case extra_out_argument: |
33 if (disp_is_oop) { |
34 _base = t == extra_in_argument ? FP : SP; |
34 rspec = Relocation::spec_simple(relocInfo::oop_type); |
35 _hi = 0; |
35 } |
36 // Warning: In LP64 mode, _disp will occupy more than 10 bits. |
36 |
37 // This is inconsistent with the other constructors but op |
37 Register rindex = as_Register(index); |
38 // codes such as ld or ldx, only access disp() to get their |
38 if (rindex != G0) { |
39 // simm13 argument. |
39 Address madr(as_Register(base), rindex); |
40 _disp = ((which - Argument::n_register_parameters + frame::memory_parameter_word_sp_offset) * BytesPerWord) + STACK_BIAS; |
40 madr._rspec = rspec; |
41 break; |
41 return madr; |
42 default: |
42 } else { |
43 ShouldNotReachHere(); |
43 Address madr(as_Register(base), disp); |
44 break; |
44 madr._rspec = rspec; |
45 } |
45 return madr; |
|
46 } |
|
47 } |
|
48 |
|
49 Address Argument::address_in_frame() const { |
|
50 // Warning: In LP64 mode disp will occupy more than 10 bits, but |
|
51 // op codes such as ld or ldx, only access disp() to get |
|
52 // their simm13 argument. |
|
53 int disp = ((_number - Argument::n_register_parameters + frame::memory_parameter_word_sp_offset) * BytesPerWord) + STACK_BIAS; |
|
54 if (is_in()) |
|
55 return Address(FP, disp); // In argument. |
|
56 else |
|
57 return Address(SP, disp); // Out argument. |
46 } |
58 } |
47 |
59 |
48 static const char* argumentNames[][2] = { |
60 static const char* argumentNames[][2] = { |
49 {"A0","P0"}, {"A1","P1"}, {"A2","P2"}, {"A3","P3"}, {"A4","P4"}, |
61 {"A0","P0"}, {"A1","P1"}, {"A2","P2"}, {"A3","P3"}, {"A4","P4"}, |
50 {"A5","P5"}, {"A6","P6"}, {"A7","P7"}, {"A8","P8"}, {"A9","P9"}, |
62 {"A5","P5"}, {"A6","P6"}, {"A7","P7"}, {"A8","P8"}, {"A9","P9"}, |
612 } |
624 } |
613 jmp(r1, offset); |
625 jmp(r1, offset); |
614 } |
626 } |
615 |
627 |
616 // This code sequence is relocatable to any address, even on LP64. |
628 // This code sequence is relocatable to any address, even on LP64. |
617 void MacroAssembler::jumpl( Address& a, Register d, int offset, const char* file, int line ) { |
629 void MacroAssembler::jumpl(AddressLiteral& addrlit, Register temp, Register d, int offset, const char* file, int line) { |
618 assert_not_delayed(); |
630 assert_not_delayed(); |
619 // Force fixed length sethi because NativeJump and NativeFarCall don't handle |
631 // Force fixed length sethi because NativeJump and NativeFarCall don't handle |
620 // variable length instruction streams. |
632 // variable length instruction streams. |
621 sethi(a, /*ForceRelocatable=*/ true); |
633 patchable_sethi(addrlit, temp); |
|
634 Address a(temp, addrlit.low10() + offset); // Add the offset to the displacement. |
622 if (TraceJumps) { |
635 if (TraceJumps) { |
623 #ifndef PRODUCT |
636 #ifndef PRODUCT |
624 // Must do the add here so relocation can find the remainder of the |
637 // Must do the add here so relocation can find the remainder of the |
625 // value to be relocated. |
638 // value to be relocated. |
626 add(a.base(), a.disp() + offset, a.base(), a.rspec(offset)); |
639 add(a.base(), a.disp(), a.base(), addrlit.rspec(offset)); |
627 save_frame(0); |
640 save_frame(0); |
628 verify_thread(); |
641 verify_thread(); |
629 ld(G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()), O0); |
642 ld(G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()), O0); |
630 add(G2_thread, in_bytes(JavaThread::jmp_ring_offset()), O1); |
643 add(G2_thread, in_bytes(JavaThread::jmp_ring_offset()), O1); |
631 sll(O0, exact_log2(4*sizeof(intptr_t)), O2); |
644 sll(O0, exact_log2(4*sizeof(intptr_t)), O2); |
650 and3(O0, JavaThread::jump_ring_buffer_size - 1, O0); |
663 and3(O0, JavaThread::jump_ring_buffer_size - 1, O0); |
651 st(O0, G2_thread, in_bytes(JavaThread::jmp_ring_index_offset())); |
664 st(O0, G2_thread, in_bytes(JavaThread::jmp_ring_index_offset())); |
652 restore(); |
665 restore(); |
653 jmpl(a.base(), G0, d); |
666 jmpl(a.base(), G0, d); |
654 #else |
667 #else |
655 jmpl(a, d, offset); |
668 jmpl(a.base(), a.disp(), d); |
656 #endif /* PRODUCT */ |
669 #endif /* PRODUCT */ |
657 } else { |
670 } else { |
658 jmpl(a, d, offset); |
671 jmpl(a.base(), a.disp(), d); |
659 } |
672 } |
660 } |
673 } |
661 |
674 |
662 void MacroAssembler::jump( Address& a, int offset, const char* file, int line ) { |
675 void MacroAssembler::jump(AddressLiteral& addrlit, Register temp, int offset, const char* file, int line) { |
663 jumpl( a, G0, offset, file, line ); |
676 jumpl(addrlit, temp, G0, offset, file, line); |
664 } |
677 } |
665 |
678 |
666 |
679 |
667 // Convert to C varargs format |
680 // Convert to C varargs format |
668 void MacroAssembler::set_varargs( Argument inArg, Register d ) { |
681 void MacroAssembler::set_varargs( Argument inArg, Register d ) { |
676 savePtr.is_register(); |
689 savePtr.is_register(); |
677 savePtr = savePtr.successor()) { |
690 savePtr = savePtr.successor()) { |
678 st_ptr(savePtr.as_register(), savePtr.address_in_frame()); |
691 st_ptr(savePtr.as_register(), savePtr.address_in_frame()); |
679 } |
692 } |
680 // return the address of the first memory slot |
693 // return the address of the first memory slot |
681 add(inArg.address_in_frame(), d); |
694 Address a = inArg.address_in_frame(); |
|
695 add(a.base(), a.disp(), d); |
682 } |
696 } |
683 |
697 |
684 // Conditional breakpoint (for assertion checks in assembly code) |
698 // Conditional breakpoint (for assertion checks in assembly code) |
685 void MacroAssembler::breakpoint_trap(Condition c, CC cc) { |
699 void MacroAssembler::breakpoint_trap(Condition c, CC cc) { |
686 trap(c, cc, G0, ST_RESERVED_FOR_USER_0); |
700 trap(c, cc, G0, ST_RESERVED_FOR_USER_0); |
700 // Write serialization page so VM thread can do a pseudo remote membar |
714 // Write serialization page so VM thread can do a pseudo remote membar |
701 // We use the current thread pointer to calculate a thread specific |
715 // We use the current thread pointer to calculate a thread specific |
702 // offset to write to within the page. This minimizes bus traffic |
716 // offset to write to within the page. This minimizes bus traffic |
703 // due to cache line collision. |
717 // due to cache line collision. |
704 void MacroAssembler::serialize_memory(Register thread, Register tmp1, Register tmp2) { |
718 void MacroAssembler::serialize_memory(Register thread, Register tmp1, Register tmp2) { |
705 Address mem_serialize_page(tmp1, os::get_memory_serialize_page()); |
|
706 srl(thread, os::get_serialize_page_shift_count(), tmp2); |
719 srl(thread, os::get_serialize_page_shift_count(), tmp2); |
707 if (Assembler::is_simm13(os::vm_page_size())) { |
720 if (Assembler::is_simm13(os::vm_page_size())) { |
708 and3(tmp2, (os::vm_page_size() - sizeof(int)), tmp2); |
721 and3(tmp2, (os::vm_page_size() - sizeof(int)), tmp2); |
709 } |
722 } |
710 else { |
723 else { |
711 set((os::vm_page_size() - sizeof(int)), tmp1); |
724 set((os::vm_page_size() - sizeof(int)), tmp1); |
712 and3(tmp2, tmp1, tmp2); |
725 and3(tmp2, tmp1, tmp2); |
713 } |
726 } |
714 load_address(mem_serialize_page); |
727 set(os::get_memory_serialize_page(), tmp1); |
715 st(G0, tmp1, tmp2); |
728 st(G0, tmp1, tmp2); |
716 } |
729 } |
717 |
730 |
718 |
731 |
719 |
732 |
828 mov(G1, L0); // avoid clobbering G1 |
841 mov(G1, L0); // avoid clobbering G1 |
829 mov(G5_method, L1); // avoid clobbering G5 |
842 mov(G5_method, L1); // avoid clobbering G5 |
830 mov(G3, L2); // avoid clobbering G3 also |
843 mov(G3, L2); // avoid clobbering G3 also |
831 mov(G4, L5); // avoid clobbering G4 |
844 mov(G4, L5); // avoid clobbering G4 |
832 #ifdef ASSERT |
845 #ifdef ASSERT |
833 Address last_get_thread_addr(L3, (address)&last_get_thread); |
846 AddressLiteral last_get_thread_addrlit(&last_get_thread); |
834 sethi(last_get_thread_addr); |
847 set(last_get_thread_addrlit, L3); |
835 inc(L4, get_pc(L4) + 2 * BytesPerInstWord); // skip getpc() code + inc + st_ptr to point L4 at call |
848 inc(L4, get_pc(L4) + 2 * BytesPerInstWord); // skip getpc() code + inc + st_ptr to point L4 at call |
836 st_ptr(L4, last_get_thread_addr); |
849 st_ptr(L4, L3, 0); |
837 #endif |
850 #endif |
838 call(CAST_FROM_FN_PTR(address, reinitialize_thread), relocInfo::runtime_call_type); |
851 call(CAST_FROM_FN_PTR(address, reinitialize_thread), relocInfo::runtime_call_type); |
839 delayed()->nop(); |
852 delayed()->nop(); |
840 mov(L0, G1); |
853 mov(L0, G1); |
841 mov(L1, G5_method); |
854 mov(L1, G5_method); |
917 |
930 |
918 |
931 |
919 // %%% maybe get rid of [re]set_last_Java_frame |
932 // %%% maybe get rid of [re]set_last_Java_frame |
920 void MacroAssembler::set_last_Java_frame(Register last_java_sp, Register last_Java_pc) { |
933 void MacroAssembler::set_last_Java_frame(Register last_java_sp, Register last_Java_pc) { |
921 assert_not_delayed(); |
934 assert_not_delayed(); |
922 Address flags(G2_thread, |
935 Address flags(G2_thread, JavaThread::frame_anchor_offset() + |
923 0, |
936 JavaFrameAnchor::flags_offset()); |
924 in_bytes(JavaThread::frame_anchor_offset()) + |
937 Address pc_addr(G2_thread, JavaThread::last_Java_pc_offset()); |
925 in_bytes(JavaFrameAnchor::flags_offset())); |
|
926 Address pc_addr(G2_thread, |
|
927 0, |
|
928 in_bytes(JavaThread::last_Java_pc_offset())); |
|
929 |
938 |
930 // Always set last_Java_pc and flags first because once last_Java_sp is visible |
939 // Always set last_Java_pc and flags first because once last_Java_sp is visible |
931 // has_last_Java_frame is true and users will look at the rest of the fields. |
940 // has_last_Java_frame is true and users will look at the rest of the fields. |
932 // (Note: flags should always be zero before we get here so doesn't need to be set.) |
941 // (Note: flags should always be zero before we get here so doesn't need to be set.) |
933 |
942 |
975 stop("Stack Not Biased in set_last_Java_frame"); |
984 stop("Stack Not Biased in set_last_Java_frame"); |
976 bind(StackOk); |
985 bind(StackOk); |
977 #endif // ASSERT |
986 #endif // ASSERT |
978 assert( last_java_sp != G4_scratch, "bad register usage in set_last_Java_frame"); |
987 assert( last_java_sp != G4_scratch, "bad register usage in set_last_Java_frame"); |
979 add( last_java_sp, STACK_BIAS, G4_scratch ); |
988 add( last_java_sp, STACK_BIAS, G4_scratch ); |
980 st_ptr(G4_scratch, Address(G2_thread, 0, in_bytes(JavaThread::last_Java_sp_offset()))); |
989 st_ptr(G4_scratch, G2_thread, JavaThread::last_Java_sp_offset()); |
981 #else |
990 #else |
982 st_ptr(last_java_sp, Address(G2_thread, 0, in_bytes(JavaThread::last_Java_sp_offset()))); |
991 st_ptr(last_java_sp, G2_thread, JavaThread::last_Java_sp_offset()); |
983 #endif // _LP64 |
992 #endif // _LP64 |
984 } |
993 } |
985 |
994 |
986 void MacroAssembler::reset_last_Java_frame(void) { |
995 void MacroAssembler::reset_last_Java_frame(void) { |
987 assert_not_delayed(); |
996 assert_not_delayed(); |
988 |
997 |
989 Address sp_addr(G2_thread, 0, in_bytes(JavaThread::last_Java_sp_offset())); |
998 Address sp_addr(G2_thread, JavaThread::last_Java_sp_offset()); |
990 Address pc_addr(G2_thread, |
999 Address pc_addr(G2_thread, JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()); |
991 0, |
1000 Address flags (G2_thread, JavaThread::frame_anchor_offset() + JavaFrameAnchor::flags_offset()); |
992 in_bytes(JavaThread::frame_anchor_offset()) + in_bytes(JavaFrameAnchor::last_Java_pc_offset())); |
|
993 Address flags(G2_thread, |
|
994 0, |
|
995 in_bytes(JavaThread::frame_anchor_offset()) + in_bytes(JavaFrameAnchor::flags_offset())); |
|
996 |
1001 |
997 #ifdef ASSERT |
1002 #ifdef ASSERT |
998 // check that it WAS previously set |
1003 // check that it WAS previously set |
999 #ifdef CC_INTERP |
1004 #ifdef CC_INTERP |
1000 save_frame(0); |
1005 save_frame(0); |
1184 } |
1189 } |
1185 |
1190 |
1186 |
1191 |
1187 void MacroAssembler::get_vm_result(Register oop_result) { |
1192 void MacroAssembler::get_vm_result(Register oop_result) { |
1188 verify_thread(); |
1193 verify_thread(); |
1189 Address vm_result_addr(G2_thread, 0, in_bytes(JavaThread::vm_result_offset())); |
1194 Address vm_result_addr(G2_thread, JavaThread::vm_result_offset()); |
1190 ld_ptr( vm_result_addr, oop_result); |
1195 ld_ptr( vm_result_addr, oop_result); |
1191 st_ptr(G0, vm_result_addr); |
1196 st_ptr(G0, vm_result_addr); |
1192 verify_oop(oop_result); |
1197 verify_oop(oop_result); |
1193 } |
1198 } |
1194 |
1199 |
1195 |
1200 |
1196 void MacroAssembler::get_vm_result_2(Register oop_result) { |
1201 void MacroAssembler::get_vm_result_2(Register oop_result) { |
1197 verify_thread(); |
1202 verify_thread(); |
1198 Address vm_result_addr_2(G2_thread, 0, in_bytes(JavaThread::vm_result_2_offset())); |
1203 Address vm_result_addr_2(G2_thread, JavaThread::vm_result_2_offset()); |
1199 ld_ptr(vm_result_addr_2, oop_result); |
1204 ld_ptr(vm_result_addr_2, oop_result); |
1200 st_ptr(G0, vm_result_addr_2); |
1205 st_ptr(G0, vm_result_addr_2); |
1201 verify_oop(oop_result); |
1206 verify_oop(oop_result); |
1202 } |
1207 } |
1203 |
1208 |
1204 |
1209 |
1205 // We require that C code which does not return a value in vm_result will |
1210 // We require that C code which does not return a value in vm_result will |
1206 // leave it undisturbed. |
1211 // leave it undisturbed. |
1207 void MacroAssembler::set_vm_result(Register oop_result) { |
1212 void MacroAssembler::set_vm_result(Register oop_result) { |
1208 verify_thread(); |
1213 verify_thread(); |
1209 Address vm_result_addr(G2_thread, 0, in_bytes(JavaThread::vm_result_offset())); |
1214 Address vm_result_addr(G2_thread, JavaThread::vm_result_offset()); |
1210 verify_oop(oop_result); |
1215 verify_oop(oop_result); |
1211 |
1216 |
1212 # ifdef ASSERT |
1217 # ifdef ASSERT |
1213 // Check that we are not overwriting any other oop. |
1218 // Check that we are not overwriting any other oop. |
1214 #ifdef CC_INTERP |
1219 #ifdef CC_INTERP |
1232 #ifdef _LP64 |
1237 #ifdef _LP64 |
1233 srlx(obj, CardTableModRefBS::card_shift, obj); |
1238 srlx(obj, CardTableModRefBS::card_shift, obj); |
1234 #else |
1239 #else |
1235 srl(obj, CardTableModRefBS::card_shift, obj); |
1240 srl(obj, CardTableModRefBS::card_shift, obj); |
1236 #endif |
1241 #endif |
1237 assert( tmp != obj, "need separate temp reg"); |
1242 assert(tmp != obj, "need separate temp reg"); |
1238 Address rs(tmp, (address)byte_map_base); |
1243 set((address) byte_map_base, tmp); |
1239 load_address(rs); |
1244 stb(G0, tmp, obj); |
1240 stb(G0, rs.base(), obj); |
1245 } |
1241 } |
1246 |
1242 |
1247 |
1243 // %%% Note: The following six instructions have been moved, |
1248 void MacroAssembler::internal_sethi(const AddressLiteral& addrlit, Register d, bool ForceRelocatable) { |
1244 // unchanged, from assembler_sparc.inline.hpp. |
|
1245 // They will be refactored at a later date. |
|
1246 |
|
1247 void MacroAssembler::sethi(intptr_t imm22a, |
|
1248 Register d, |
|
1249 bool ForceRelocatable, |
|
1250 RelocationHolder const& rspec) { |
|
1251 Address adr( d, (address)imm22a, rspec ); |
|
1252 MacroAssembler::sethi( adr, ForceRelocatable ); |
|
1253 } |
|
1254 |
|
1255 |
|
1256 void MacroAssembler::sethi(Address& a, bool ForceRelocatable) { |
|
1257 address save_pc; |
1249 address save_pc; |
1258 int shiftcnt; |
1250 int shiftcnt; |
1259 // if addr of local, do not need to load it |
|
1260 assert(a.base() != FP && a.base() != SP, "just use ld or st for locals"); |
|
1261 #ifdef _LP64 |
1251 #ifdef _LP64 |
1262 # ifdef CHECK_DELAY |
1252 # ifdef CHECK_DELAY |
1263 assert_not_delayed( (char *)"cannot put two instructions in delay slot" ); |
1253 assert_not_delayed((char*) "cannot put two instructions in delay slot"); |
1264 # endif |
1254 # endif |
1265 v9_dep(); |
1255 v9_dep(); |
1266 // ForceRelocatable = 1; |
|
1267 save_pc = pc(); |
1256 save_pc = pc(); |
1268 if (a.hi32() == 0 && a.low32() >= 0) { |
1257 |
1269 Assembler::sethi(a.low32(), a.base(), a.rspec()); |
1258 int msb32 = (int) (addrlit.value() >> 32); |
1270 } |
1259 int lsb32 = (int) (addrlit.value()); |
1271 else if (a.hi32() == -1) { |
1260 |
1272 Assembler::sethi(~a.low32(), a.base(), a.rspec()); |
1261 if (msb32 == 0 && lsb32 >= 0) { |
1273 xor3(a.base(), ~low10(~0), a.base()); |
1262 Assembler::sethi(lsb32, d, addrlit.rspec()); |
|
1263 } |
|
1264 else if (msb32 == -1) { |
|
1265 Assembler::sethi(~lsb32, d, addrlit.rspec()); |
|
1266 xor3(d, ~low10(~0), d); |
1274 } |
1267 } |
1275 else { |
1268 else { |
1276 Assembler::sethi(a.hi32(), a.base(), a.rspec() ); // 22 |
1269 Assembler::sethi(msb32, d, addrlit.rspec()); // msb 22-bits |
1277 if ( a.hi32() & 0x3ff ) // Any bits? |
1270 if (msb32 & 0x3ff) // Any bits? |
1278 or3( a.base(), a.hi32() & 0x3ff ,a.base() ); // High 32 bits are now in low 32 |
1271 or3(d, msb32 & 0x3ff, d); // msb 32-bits are now in lsb 32 |
1279 if ( a.low32() & 0xFFFFFC00 ) { // done? |
1272 if (lsb32 & 0xFFFFFC00) { // done? |
1280 if( (a.low32() >> 20) & 0xfff ) { // Any bits set? |
1273 if ((lsb32 >> 20) & 0xfff) { // Any bits set? |
1281 sllx(a.base(), 12, a.base()); // Make room for next 12 bits |
1274 sllx(d, 12, d); // Make room for next 12 bits |
1282 or3( a.base(), (a.low32() >> 20) & 0xfff,a.base() ); // Or in next 12 |
1275 or3(d, (lsb32 >> 20) & 0xfff, d); // Or in next 12 |
1283 shiftcnt = 0; // We already shifted |
1276 shiftcnt = 0; // We already shifted |
1284 } |
1277 } |
1285 else |
1278 else |
1286 shiftcnt = 12; |
1279 shiftcnt = 12; |
1287 if( (a.low32() >> 10) & 0x3ff ) { |
1280 if ((lsb32 >> 10) & 0x3ff) { |
1288 sllx(a.base(), shiftcnt+10, a.base());// Make room for last 10 bits |
1281 sllx(d, shiftcnt + 10, d); // Make room for last 10 bits |
1289 or3( a.base(), (a.low32() >> 10) & 0x3ff,a.base() ); // Or in next 10 |
1282 or3(d, (lsb32 >> 10) & 0x3ff, d); // Or in next 10 |
1290 shiftcnt = 0; |
1283 shiftcnt = 0; |
1291 } |
1284 } |
1292 else |
1285 else |
1293 shiftcnt = 10; |
1286 shiftcnt = 10; |
1294 sllx(a.base(), shiftcnt+10 , a.base()); // Shift leaving disp field 0'd |
1287 sllx(d, shiftcnt + 10, d); // Shift leaving disp field 0'd |
1295 } |
1288 } |
1296 else |
1289 else |
1297 sllx( a.base(), 32, a.base() ); |
1290 sllx(d, 32, d); |
1298 } |
1291 } |
1299 // Pad out the instruction sequence so it can be |
1292 // Pad out the instruction sequence so it can be patched later. |
1300 // patched later. |
1293 if (ForceRelocatable || (addrlit.rtype() != relocInfo::none && |
1301 if ( ForceRelocatable || (a.rtype() != relocInfo::none && |
1294 addrlit.rtype() != relocInfo::runtime_call_type)) { |
1302 a.rtype() != relocInfo::runtime_call_type) ) { |
1295 while (pc() < (save_pc + (7 * BytesPerInstWord))) |
1303 while ( pc() < (save_pc + (7 * BytesPerInstWord )) ) |
|
1304 nop(); |
1296 nop(); |
1305 } |
1297 } |
1306 #else |
1298 #else |
1307 Assembler::sethi(a.hi(), a.base(), a.rspec()); |
1299 Assembler::sethi(addrlit.value(), d, addrlit.rspec()); |
1308 #endif |
1300 #endif |
1309 |
1301 } |
1310 } |
1302 |
|
1303 |
|
1304 void MacroAssembler::sethi(const AddressLiteral& addrlit, Register d) { |
|
1305 internal_sethi(addrlit, d, false); |
|
1306 } |
|
1307 |
|
1308 |
|
1309 void MacroAssembler::patchable_sethi(const AddressLiteral& addrlit, Register d) { |
|
1310 internal_sethi(addrlit, d, true); |
|
1311 } |
|
1312 |
1311 |
1313 |
1312 int MacroAssembler::size_of_sethi(address a, bool worst_case) { |
1314 int MacroAssembler::size_of_sethi(address a, bool worst_case) { |
1313 #ifdef _LP64 |
1315 #ifdef _LP64 |
1314 if (worst_case) return 7; |
1316 if (worst_case) return 7; |
1315 intptr_t iaddr = (intptr_t)a; |
1317 intptr_t iaddr = (intptr_t)a; |
1337 |
1339 |
1338 int MacroAssembler::worst_case_size_of_set() { |
1340 int MacroAssembler::worst_case_size_of_set() { |
1339 return size_of_sethi(NULL, true) + 1; |
1341 return size_of_sethi(NULL, true) + 1; |
1340 } |
1342 } |
1341 |
1343 |
1342 void MacroAssembler::set(intptr_t value, Register d, |
1344 |
1343 RelocationHolder const& rspec) { |
1345 void MacroAssembler::internal_set(const AddressLiteral& addrlit, Register d, bool ForceRelocatable) { |
1344 Address val( d, (address)value, rspec); |
1346 intptr_t value = addrlit.value(); |
1345 |
1347 |
1346 if ( rspec.type() == relocInfo::none ) { |
1348 if (!ForceRelocatable && addrlit.rspec().type() == relocInfo::none) { |
1347 // can optimize |
1349 // can optimize |
1348 if (-4096 <= value && value <= 4095) { |
1350 if (-4096 <= value && value <= 4095) { |
1349 or3(G0, value, d); // setsw (this leaves upper 32 bits sign-extended) |
1351 or3(G0, value, d); // setsw (this leaves upper 32 bits sign-extended) |
1350 return; |
1352 return; |
1351 } |
1353 } |
1352 if (inv_hi22(hi22(value)) == value) { |
1354 if (inv_hi22(hi22(value)) == value) { |
1353 sethi(val); |
1355 sethi(addrlit, d); |
1354 return; |
1356 return; |
1355 } |
1357 } |
1356 } |
1358 } |
1357 assert_not_delayed( (char *)"cannot put two instructions in delay slot" ); |
1359 assert_not_delayed((char*) "cannot put two instructions in delay slot"); |
1358 sethi( val ); |
1360 internal_sethi(addrlit, d, ForceRelocatable); |
1359 if (rspec.type() != relocInfo::none || (value & 0x3ff) != 0) { |
1361 if (ForceRelocatable || addrlit.rspec().type() != relocInfo::none || addrlit.low10() != 0) { |
1360 add( d, value & 0x3ff, d, rspec); |
1362 add(d, addrlit.low10(), d, addrlit.rspec()); |
1361 } |
1363 } |
1362 } |
1364 } |
1363 |
1365 |
1364 void MacroAssembler::setsw(int value, Register d, |
1366 void MacroAssembler::set(const AddressLiteral& al, Register d) { |
1365 RelocationHolder const& rspec) { |
1367 internal_set(al, d, false); |
1366 Address val( d, (address)value, rspec); |
1368 } |
1367 if ( rspec.type() == relocInfo::none ) { |
1369 |
1368 // can optimize |
1370 void MacroAssembler::set(intptr_t value, Register d) { |
1369 if (-4096 <= value && value <= 4095) { |
1371 AddressLiteral al(value); |
1370 or3(G0, value, d); |
1372 internal_set(al, d, false); |
1371 return; |
1373 } |
1372 } |
1374 |
1373 if (inv_hi22(hi22(value)) == value) { |
1375 void MacroAssembler::set(address addr, Register d, RelocationHolder const& rspec) { |
1374 sethi( val ); |
1376 AddressLiteral al(addr, rspec); |
1375 #ifndef _LP64 |
1377 internal_set(al, d, false); |
1376 if ( value < 0 ) { |
1378 } |
1377 assert_not_delayed(); |
1379 |
1378 sra (d, G0, d); |
1380 void MacroAssembler::patchable_set(const AddressLiteral& al, Register d) { |
1379 } |
1381 internal_set(al, d, true); |
1380 #endif |
1382 } |
1381 return; |
1383 |
1382 } |
1384 void MacroAssembler::patchable_set(intptr_t value, Register d) { |
1383 } |
1385 AddressLiteral al(value); |
1384 assert_not_delayed(); |
1386 internal_set(al, d, true); |
1385 sethi( val ); |
1387 } |
1386 add( d, value & 0x3ff, d, rspec); |
|
1387 |
|
1388 // (A negative value could be loaded in 2 insns with sethi/xor, |
|
1389 // but it would take a more complex relocation.) |
|
1390 #ifndef _LP64 |
|
1391 if ( value < 0) |
|
1392 sra(d, G0, d); |
|
1393 #endif |
|
1394 } |
|
1395 |
|
1396 // %%% End of moved six set instructions. |
|
1397 |
1388 |
1398 |
1389 |
1399 void MacroAssembler::set64(jlong value, Register d, Register tmp) { |
1390 void MacroAssembler::set64(jlong value, Register d, Register tmp) { |
1400 assert_not_delayed(); |
1391 assert_not_delayed(); |
1401 v9_dep(); |
1392 v9_dep(); |
1510 mov(s2->after_save(), d2); |
1501 mov(s2->after_save(), d2); |
1511 } |
1502 } |
1512 } |
1503 } |
1513 |
1504 |
1514 |
1505 |
1515 Address MacroAssembler::allocate_oop_address(jobject obj, Register d) { |
1506 AddressLiteral MacroAssembler::allocate_oop_address(jobject obj) { |
1516 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder"); |
1507 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder"); |
1517 int oop_index = oop_recorder()->allocate_index(obj); |
1508 int oop_index = oop_recorder()->allocate_index(obj); |
1518 return Address(d, address(obj), oop_Relocation::spec(oop_index)); |
1509 return AddressLiteral(obj, oop_Relocation::spec(oop_index)); |
1519 } |
1510 } |
1520 |
1511 |
1521 |
1512 |
1522 Address MacroAssembler::constant_oop_address(jobject obj, Register d) { |
1513 AddressLiteral MacroAssembler::constant_oop_address(jobject obj) { |
1523 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder"); |
1514 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder"); |
1524 int oop_index = oop_recorder()->find_index(obj); |
1515 int oop_index = oop_recorder()->find_index(obj); |
1525 return Address(d, address(obj), oop_Relocation::spec(oop_index)); |
1516 return AddressLiteral(obj, oop_Relocation::spec(oop_index)); |
1526 } |
1517 } |
1527 |
1518 |
1528 void MacroAssembler::set_narrow_oop(jobject obj, Register d) { |
1519 void MacroAssembler::set_narrow_oop(jobject obj, Register d) { |
1529 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder"); |
1520 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder"); |
1530 int oop_index = oop_recorder()->find_index(obj); |
1521 int oop_index = oop_recorder()->find_index(obj); |
3105 cmp(temp_reg, markOopDesc::biased_lock_pattern); |
3092 cmp(temp_reg, markOopDesc::biased_lock_pattern); |
3106 brx(Assembler::notEqual, false, Assembler::pn, cas_label); |
3093 brx(Assembler::notEqual, false, Assembler::pn, cas_label); |
3107 delayed()->nop(); |
3094 delayed()->nop(); |
3108 |
3095 |
3109 load_klass(obj_reg, temp_reg); |
3096 load_klass(obj_reg, temp_reg); |
3110 ld_ptr(Address(temp_reg, 0, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()), temp_reg); |
3097 ld_ptr(Address(temp_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()), temp_reg); |
3111 or3(G2_thread, temp_reg, temp_reg); |
3098 or3(G2_thread, temp_reg, temp_reg); |
3112 xor3(mark_reg, temp_reg, temp_reg); |
3099 xor3(mark_reg, temp_reg, temp_reg); |
3113 andcc(temp_reg, ~((int) markOopDesc::age_mask_in_place), temp_reg); |
3100 andcc(temp_reg, ~((int) markOopDesc::age_mask_in_place), temp_reg); |
3114 if (counters != NULL) { |
3101 if (counters != NULL) { |
3115 cond_inc(Assembler::equal, (address) counters->biased_lock_entry_count_addr(), mark_reg, temp_reg); |
3102 cond_inc(Assembler::equal, (address) counters->biased_lock_entry_count_addr(), mark_reg, temp_reg); |
3116 // Reload mark_reg as we may need it later |
3103 // Reload mark_reg as we may need it later |
3117 ld_ptr(Address(obj_reg, 0, oopDesc::mark_offset_in_bytes()), mark_reg); |
3104 ld_ptr(Address(obj_reg, oopDesc::mark_offset_in_bytes()), mark_reg); |
3118 } |
3105 } |
3119 brx(Assembler::equal, true, Assembler::pt, done); |
3106 brx(Assembler::equal, true, Assembler::pt, done); |
3120 delayed()->nop(); |
3107 delayed()->nop(); |
3121 |
3108 |
3122 Label try_revoke_bias; |
3109 Label try_revoke_bias; |
3123 Label try_rebias; |
3110 Label try_rebias; |
3124 Address mark_addr = Address(obj_reg, 0, oopDesc::mark_offset_in_bytes()); |
3111 Address mark_addr = Address(obj_reg, oopDesc::mark_offset_in_bytes()); |
3125 assert(mark_addr.disp() == 0, "cas must take a zero displacement"); |
3112 assert(mark_addr.disp() == 0, "cas must take a zero displacement"); |
3126 |
3113 |
3127 // At this point we know that the header has the bias pattern and |
3114 // At this point we know that the header has the bias pattern and |
3128 // that we are not the bias owner in the current epoch. We need to |
3115 // that we are not the bias owner in the current epoch. We need to |
3129 // figure out more details about the state of the header in order to |
3116 // figure out more details about the state of the header in order to |
3183 // the bias from one thread to another directly in this situation. |
3170 // the bias from one thread to another directly in this situation. |
3184 // |
3171 // |
3185 // FIXME: due to a lack of registers we currently blow away the age |
3172 // FIXME: due to a lack of registers we currently blow away the age |
3186 // bits in this situation. Should attempt to preserve them. |
3173 // bits in this situation. Should attempt to preserve them. |
3187 load_klass(obj_reg, temp_reg); |
3174 load_klass(obj_reg, temp_reg); |
3188 ld_ptr(Address(temp_reg, 0, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()), temp_reg); |
3175 ld_ptr(Address(temp_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()), temp_reg); |
3189 or3(G2_thread, temp_reg, temp_reg); |
3176 or3(G2_thread, temp_reg, temp_reg); |
3190 casn(mark_addr.base(), mark_reg, temp_reg); |
3177 casn(mark_addr.base(), mark_reg, temp_reg); |
3191 // If the biasing toward our thread failed, this means that |
3178 // If the biasing toward our thread failed, this means that |
3192 // another thread succeeded in biasing it toward itself and we |
3179 // another thread succeeded in biasing it toward itself and we |
3193 // need to revoke that bias. The revocation will occur in the |
3180 // need to revoke that bias. The revocation will occur in the |
3214 // normal locking code. |
3201 // normal locking code. |
3215 // |
3202 // |
3216 // FIXME: due to a lack of registers we currently blow away the age |
3203 // FIXME: due to a lack of registers we currently blow away the age |
3217 // bits in this situation. Should attempt to preserve them. |
3204 // bits in this situation. Should attempt to preserve them. |
3218 load_klass(obj_reg, temp_reg); |
3205 load_klass(obj_reg, temp_reg); |
3219 ld_ptr(Address(temp_reg, 0, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()), temp_reg); |
3206 ld_ptr(Address(temp_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()), temp_reg); |
3220 casn(mark_addr.base(), mark_reg, temp_reg); |
3207 casn(mark_addr.base(), mark_reg, temp_reg); |
3221 // Fall through to the normal CAS-based lock, because no matter what |
3208 // Fall through to the normal CAS-based lock, because no matter what |
3222 // the result of the above CAS, some thread must have succeeded in |
3209 // the result of the above CAS, some thread must have succeeded in |
3223 // removing the bias bit from the object's header. |
3210 // removing the bias bit from the object's header. |
3224 if (counters != NULL) { |
3211 if (counters != NULL) { |
3480 if (EmitSync & 64) { |
3467 if (EmitSync & 64) { |
3481 // If m->owner != null goto IsLocked |
3468 // If m->owner != null goto IsLocked |
3482 // Test-and-CAS vs CAS |
3469 // Test-and-CAS vs CAS |
3483 // Pessimistic form avoids futile (doomed) CAS attempts |
3470 // Pessimistic form avoids futile (doomed) CAS attempts |
3484 // The optimistic form avoids RTS->RTO cache line upgrades. |
3471 // The optimistic form avoids RTS->RTO cache line upgrades. |
3485 ld_ptr (Address (Rmark, 0, ObjectMonitor::owner_offset_in_bytes()-2), Rscratch) ; |
3472 ld_ptr (Rmark, ObjectMonitor::owner_offset_in_bytes() - 2, Rscratch); |
3486 andcc (Rscratch, Rscratch, G0) ; |
3473 andcc (Rscratch, Rscratch, G0) ; |
3487 brx (Assembler::notZero, false, Assembler::pn, done) ; |
3474 brx (Assembler::notZero, false, Assembler::pn, done) ; |
3488 delayed()->nop() ; |
3475 delayed()->nop() ; |
3489 // m->owner == null : it's unlocked. |
3476 // m->owner == null : it's unlocked. |
3490 } |
3477 } |
3566 // past the store that releases the lock. But TSO is a strong memory model |
3553 // past the store that releases the lock. But TSO is a strong memory model |
3567 // and that particular flavor of barrier is a noop, so we can safely elide it. |
3554 // and that particular flavor of barrier is a noop, so we can safely elide it. |
3568 // Note that we use 1-0 locking by default for the inflated case. We |
3555 // Note that we use 1-0 locking by default for the inflated case. We |
3569 // close the resultant (and rare) race by having contented threads in |
3556 // close the resultant (and rare) race by having contented threads in |
3570 // monitorenter periodically poll _owner. |
3557 // monitorenter periodically poll _owner. |
3571 ld_ptr (Address(Rmark, 0, ObjectMonitor::owner_offset_in_bytes()-2), Rscratch) ; |
3558 ld_ptr (Rmark, ObjectMonitor::owner_offset_in_bytes() - 2, Rscratch); |
3572 ld_ptr (Address(Rmark, 0, ObjectMonitor::recursions_offset_in_bytes()-2), Rbox) ; |
3559 ld_ptr (Rmark, ObjectMonitor::recursions_offset_in_bytes() - 2, Rbox); |
3573 xor3 (Rscratch, G2_thread, Rscratch) ; |
3560 xor3 (Rscratch, G2_thread, Rscratch) ; |
3574 orcc (Rbox, Rscratch, Rbox) ; |
3561 orcc (Rbox, Rscratch, Rbox) ; |
3575 brx (Assembler::notZero, false, Assembler::pn, done) ; |
3562 brx (Assembler::notZero, false, Assembler::pn, done) ; |
3576 delayed()-> |
3563 delayed()-> |
3577 ld_ptr (Address (Rmark, 0, ObjectMonitor::EntryList_offset_in_bytes()-2), Rscratch) ; |
3564 ld_ptr (Rmark, ObjectMonitor::EntryList_offset_in_bytes() - 2, Rscratch); |
3578 ld_ptr (Address (Rmark, 0, ObjectMonitor::cxq_offset_in_bytes()-2), Rbox) ; |
3565 ld_ptr (Rmark, ObjectMonitor::cxq_offset_in_bytes() - 2, Rbox); |
3579 orcc (Rbox, Rscratch, G0) ; |
3566 orcc (Rbox, Rscratch, G0) ; |
3580 if (EmitSync & 65536) { |
3567 if (EmitSync & 65536) { |
3581 Label LSucc ; |
3568 Label LSucc ; |
3582 brx (Assembler::notZero, false, Assembler::pn, LSucc) ; |
3569 brx (Assembler::notZero, false, Assembler::pn, LSucc) ; |
3583 delayed()->nop() ; |
3570 delayed()->nop() ; |
3584 br (Assembler::always, false, Assembler::pt, done) ; |
3571 br (Assembler::always, false, Assembler::pt, done) ; |
3585 delayed()-> |
3572 delayed()-> |
3586 st_ptr (G0, Address (Rmark, 0, ObjectMonitor::owner_offset_in_bytes()-2)) ; |
3573 st_ptr (G0, Rmark, ObjectMonitor::owner_offset_in_bytes() - 2); |
3587 |
3574 |
3588 bind (LSucc) ; |
3575 bind (LSucc) ; |
3589 st_ptr (G0, Address (Rmark, 0, ObjectMonitor::owner_offset_in_bytes()-2)) ; |
3576 st_ptr (G0, Rmark, ObjectMonitor::owner_offset_in_bytes() - 2); |
3590 if (os::is_MP()) { membar (StoreLoad) ; } |
3577 if (os::is_MP()) { membar (StoreLoad) ; } |
3591 ld_ptr (Address (Rmark, 0, ObjectMonitor::succ_offset_in_bytes()-2), Rscratch) ; |
3578 ld_ptr (Rmark, ObjectMonitor::succ_offset_in_bytes() - 2, Rscratch); |
3592 andcc (Rscratch, Rscratch, G0) ; |
3579 andcc (Rscratch, Rscratch, G0) ; |
3593 brx (Assembler::notZero, false, Assembler::pt, done) ; |
3580 brx (Assembler::notZero, false, Assembler::pt, done) ; |
3594 delayed()-> andcc (G0, G0, G0) ; |
3581 delayed()-> andcc (G0, G0, G0) ; |
3595 add (Rmark, ObjectMonitor::owner_offset_in_bytes()-2, Rmark) ; |
3582 add (Rmark, ObjectMonitor::owner_offset_in_bytes()-2, Rmark) ; |
3596 mov (G2_thread, Rscratch) ; |
3583 mov (G2_thread, Rscratch) ; |
4003 delayed()->nop(); |
3990 delayed()->nop(); |
4004 inc_counter(counter_ptr, Rtmp1, Rtmp2); |
3991 inc_counter(counter_ptr, Rtmp1, Rtmp2); |
4005 bind(L); |
3992 bind(L); |
4006 } |
3993 } |
4007 |
3994 |
4008 void MacroAssembler::inc_counter(address counter_ptr, Register Rtmp1, Register Rtmp2) { |
3995 void MacroAssembler::inc_counter(address counter_addr, Register Rtmp1, Register Rtmp2) { |
4009 Address counter_addr(Rtmp1, counter_ptr); |
3996 AddressLiteral addrlit(counter_addr); |
4010 load_contents(counter_addr, Rtmp2); |
3997 sethi(addrlit, Rtmp1); // Move hi22 bits into temporary register. |
|
3998 Address addr(Rtmp1, addrlit.low10()); // Build an address with low10 bits. |
|
3999 ld(addr, Rtmp2); |
4011 inc(Rtmp2); |
4000 inc(Rtmp2); |
4012 store_contents(Rtmp2, counter_addr); |
4001 st(Rtmp2, addr); |
|
4002 } |
|
4003 |
|
4004 void MacroAssembler::inc_counter(int* counter_addr, Register Rtmp1, Register Rtmp2) { |
|
4005 inc_counter((address) counter_addr, Rtmp1, Rtmp2); |
4013 } |
4006 } |
4014 |
4007 |
4015 SkipIfEqual::SkipIfEqual( |
4008 SkipIfEqual::SkipIfEqual( |
4016 MacroAssembler* masm, Register temp, const bool* flag_addr, |
4009 MacroAssembler* masm, Register temp, const bool* flag_addr, |
4017 Assembler::Condition condition) { |
4010 Assembler::Condition condition) { |
4018 _masm = masm; |
4011 _masm = masm; |
4019 Address flag(temp, (address)flag_addr, relocInfo::none); |
4012 AddressLiteral flag(flag_addr); |
4020 _masm->sethi(flag); |
4013 _masm->sethi(flag, temp); |
4021 _masm->ldub(flag, temp); |
4014 _masm->ldub(temp, flag.low10(), temp); |
4022 _masm->tst(temp); |
4015 _masm->tst(temp); |
4023 _masm->br(condition, false, Assembler::pt, _label); |
4016 _masm->br(condition, false, Assembler::pt, _label); |
4024 _masm->delayed()->nop(); |
4017 _masm->delayed()->nop(); |
4025 } |
4018 } |
4026 |
4019 |
4331 #ifdef _LP64 |
4324 #ifdef _LP64 |
4332 masm.srlx(O0, CardTableModRefBS::card_shift, O0); |
4325 masm.srlx(O0, CardTableModRefBS::card_shift, O0); |
4333 #else |
4326 #else |
4334 masm.srl(O0, CardTableModRefBS::card_shift, O0); |
4327 masm.srl(O0, CardTableModRefBS::card_shift, O0); |
4335 #endif |
4328 #endif |
4336 Address rs(O1, (address)byte_map_base); |
4329 AddressLiteral addrlit(byte_map_base); |
4337 masm.load_address(rs); // O1 := <card table base> |
4330 masm.set(addrlit, O1); // O1 := <card table base> |
4338 masm.ldub(O0, O1, O2); // O2 := [O0 + O1] |
4331 masm.ldub(O0, O1, O2); // O2 := [O0 + O1] |
4339 |
4332 |
4340 masm.br_on_reg_cond(Assembler::rc_nz, /*annul*/false, Assembler::pt, |
4333 masm.br_on_reg_cond(Assembler::rc_nz, /*annul*/false, Assembler::pt, |
4341 O2, not_already_dirty); |
4334 O2, not_already_dirty); |
4342 // Get O1 + O2 into a reg by itself -- useful in the take-the-branch |
4335 // Get O1 + O2 into a reg by itself -- useful in the take-the-branch |
4513 CardTableModRefBS* bs = (CardTableModRefBS*) Universe::heap()->barrier_set(); |
4505 CardTableModRefBS* bs = (CardTableModRefBS*) Universe::heap()->barrier_set(); |
4514 assert(bs->kind() == BarrierSet::CardTableModRef || |
4506 assert(bs->kind() == BarrierSet::CardTableModRef || |
4515 bs->kind() == BarrierSet::CardTableExtension, "wrong barrier"); |
4507 bs->kind() == BarrierSet::CardTableExtension, "wrong barrier"); |
4516 card_table_write(bs->byte_map_base, tmp, store_addr); |
4508 card_table_write(bs->byte_map_base, tmp, store_addr); |
4517 } |
4509 } |
4518 |
|
4519 // Loading values by size and signed-ness |
|
4520 void MacroAssembler::load_sized_value(Register s1, RegisterOrConstant s2, Register d, |
|
4521 int size_in_bytes, bool is_signed) { |
|
4522 switch (size_in_bytes ^ (is_signed ? -1 : 0)) { |
|
4523 case ~8: // fall through: |
|
4524 case 8: ld_long( s1, s2, d ); break; |
|
4525 case ~4: ldsw( s1, s2, d ); break; |
|
4526 case 4: lduw( s1, s2, d ); break; |
|
4527 case ~2: ldsh( s1, s2, d ); break; |
|
4528 case 2: lduh( s1, s2, d ); break; |
|
4529 case ~1: ldsb( s1, s2, d ); break; |
|
4530 case 1: ldub( s1, s2, d ); break; |
|
4531 default: ShouldNotReachHere(); |
|
4532 } |
|
4533 } |
|
4534 |
|
4535 |
|
4536 |
4510 |
4537 void MacroAssembler::load_klass(Register src_oop, Register klass) { |
4511 void MacroAssembler::load_klass(Register src_oop, Register klass) { |
4538 // The number of bytes in this code is used by |
4512 // The number of bytes in this code is used by |
4539 // MachCallDynamicJavaNode::ret_addr_offset() |
4513 // MachCallDynamicJavaNode::ret_addr_offset() |
4540 // if this changes, change that. |
4514 // if this changes, change that. |