2537 enc_class Push_SrcXD(regD src) %{ |
2525 enc_class Push_SrcXD(regD src) %{ |
2538 MacroAssembler _masm(&cbuf); |
2526 MacroAssembler _masm(&cbuf); |
2539 __ subptr(rsp, 8); |
2527 __ subptr(rsp, 8); |
2540 __ movdbl(Address(rsp, 0), $src$$XMMRegister); |
2528 __ movdbl(Address(rsp, 0), $src$$XMMRegister); |
2541 __ fld_d(Address(rsp, 0)); |
2529 __ fld_d(Address(rsp, 0)); |
2542 %} |
|
2543 |
|
2544 |
|
2545 // obj: object to lock |
|
2546 // box: box address (header location) -- killed |
|
2547 // tmp: rax -- killed |
|
2548 // scr: rbx -- killed |
|
2549 // |
|
2550 // What follows is a direct transliteration of fast_lock() and fast_unlock() |
|
2551 // from i486.ad. See that file for comments. |
|
2552 // TODO: where possible switch from movq (r, 0) to movl(r,0) and |
|
2553 // use the shorter encoding. (Movl clears the high-order 32-bits). |
|
2554 |
|
2555 |
|
2556 enc_class Fast_Lock(rRegP obj, rRegP box, rax_RegI tmp, rRegP scr) |
|
2557 %{ |
|
2558 Register objReg = as_Register((int)$obj$$reg); |
|
2559 Register boxReg = as_Register((int)$box$$reg); |
|
2560 Register tmpReg = as_Register($tmp$$reg); |
|
2561 Register scrReg = as_Register($scr$$reg); |
|
2562 MacroAssembler masm(&cbuf); |
|
2563 |
|
2564 // Verify uniqueness of register assignments -- necessary but not sufficient |
|
2565 assert (objReg != boxReg && objReg != tmpReg && |
|
2566 objReg != scrReg && tmpReg != scrReg, "invariant") ; |
|
2567 |
|
2568 if (_counters != NULL) { |
|
2569 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr())); |
|
2570 } |
|
2571 if (EmitSync & 1) { |
|
2572 // Without cast to int32_t a movptr will destroy r10 which is typically obj |
|
2573 masm.movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())) ; |
|
2574 masm.cmpptr(rsp, (int32_t)NULL_WORD) ; |
|
2575 } else |
|
2576 if (EmitSync & 2) { |
|
2577 Label DONE_LABEL; |
|
2578 if (UseBiasedLocking) { |
|
2579 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument. |
|
2580 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters); |
|
2581 } |
|
2582 // QQQ was movl... |
|
2583 masm.movptr(tmpReg, 0x1); |
|
2584 masm.orptr(tmpReg, Address(objReg, 0)); |
|
2585 masm.movptr(Address(boxReg, 0), tmpReg); |
|
2586 if (os::is_MP()) { |
|
2587 masm.lock(); |
|
2588 } |
|
2589 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg |
|
2590 masm.jcc(Assembler::equal, DONE_LABEL); |
|
2591 |
|
2592 // Recursive locking |
|
2593 masm.subptr(tmpReg, rsp); |
|
2594 masm.andptr(tmpReg, 7 - os::vm_page_size()); |
|
2595 masm.movptr(Address(boxReg, 0), tmpReg); |
|
2596 |
|
2597 masm.bind(DONE_LABEL); |
|
2598 masm.nop(); // avoid branch to branch |
|
2599 } else { |
|
2600 Label DONE_LABEL, IsInflated, Egress; |
|
2601 |
|
2602 masm.movptr(tmpReg, Address(objReg, 0)) ; |
|
2603 masm.testl (tmpReg, 0x02) ; // inflated vs stack-locked|neutral|biased |
|
2604 masm.jcc (Assembler::notZero, IsInflated) ; |
|
2605 |
|
2606 // it's stack-locked, biased or neutral |
|
2607 // TODO: optimize markword triage order to reduce the number of |
|
2608 // conditional branches in the most common cases. |
|
2609 // Beware -- there's a subtle invariant that fetch of the markword |
|
2610 // at [FETCH], below, will never observe a biased encoding (*101b). |
|
2611 // If this invariant is not held we'll suffer exclusion (safety) failure. |
|
2612 |
|
2613 if (UseBiasedLocking && !UseOptoBiasInlining) { |
|
2614 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, true, DONE_LABEL, NULL, _counters); |
|
2615 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH] |
|
2616 } |
|
2617 |
|
2618 // was q will it destroy high? |
|
2619 masm.orl (tmpReg, 1) ; |
|
2620 masm.movptr(Address(boxReg, 0), tmpReg) ; |
|
2621 if (os::is_MP()) { masm.lock(); } |
|
2622 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg |
|
2623 if (_counters != NULL) { |
|
2624 masm.cond_inc32(Assembler::equal, |
|
2625 ExternalAddress((address) _counters->fast_path_entry_count_addr())); |
|
2626 } |
|
2627 masm.jcc (Assembler::equal, DONE_LABEL); |
|
2628 |
|
2629 // Recursive locking |
|
2630 masm.subptr(tmpReg, rsp); |
|
2631 masm.andptr(tmpReg, 7 - os::vm_page_size()); |
|
2632 masm.movptr(Address(boxReg, 0), tmpReg); |
|
2633 if (_counters != NULL) { |
|
2634 masm.cond_inc32(Assembler::equal, |
|
2635 ExternalAddress((address) _counters->fast_path_entry_count_addr())); |
|
2636 } |
|
2637 masm.jmp (DONE_LABEL) ; |
|
2638 |
|
2639 masm.bind (IsInflated) ; |
|
2640 // It's inflated |
|
2641 |
|
2642 // TODO: someday avoid the ST-before-CAS penalty by |
|
2643 // relocating (deferring) the following ST. |
|
2644 // We should also think about trying a CAS without having |
|
2645 // fetched _owner. If the CAS is successful we may |
|
2646 // avoid an RTO->RTS upgrade on the $line. |
|
2647 // Without cast to int32_t a movptr will destroy r10 which is typically obj |
|
2648 masm.movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())) ; |
|
2649 |
|
2650 masm.mov (boxReg, tmpReg) ; |
|
2651 masm.movptr (tmpReg, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; |
|
2652 masm.testptr(tmpReg, tmpReg) ; |
|
2653 masm.jcc (Assembler::notZero, DONE_LABEL) ; |
|
2654 |
|
2655 // It's inflated and appears unlocked |
|
2656 if (os::is_MP()) { masm.lock(); } |
|
2657 masm.cmpxchgptr(r15_thread, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; |
|
2658 // Intentional fall-through into DONE_LABEL ... |
|
2659 |
|
2660 masm.bind (DONE_LABEL) ; |
|
2661 masm.nop () ; // avoid jmp to jmp |
|
2662 } |
|
2663 %} |
|
2664 |
|
2665 // obj: object to unlock |
|
2666 // box: box address (displaced header location), killed |
|
2667 // RBX: killed tmp; cannot be obj nor box |
|
2668 enc_class Fast_Unlock(rRegP obj, rax_RegP box, rRegP tmp) |
|
2669 %{ |
|
2670 |
|
2671 Register objReg = as_Register($obj$$reg); |
|
2672 Register boxReg = as_Register($box$$reg); |
|
2673 Register tmpReg = as_Register($tmp$$reg); |
|
2674 MacroAssembler masm(&cbuf); |
|
2675 |
|
2676 if (EmitSync & 4) { |
|
2677 masm.cmpptr(rsp, 0) ; |
|
2678 } else |
|
2679 if (EmitSync & 8) { |
|
2680 Label DONE_LABEL; |
|
2681 if (UseBiasedLocking) { |
|
2682 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL); |
|
2683 } |
|
2684 |
|
2685 // Check whether the displaced header is 0 |
|
2686 //(=> recursive unlock) |
|
2687 masm.movptr(tmpReg, Address(boxReg, 0)); |
|
2688 masm.testptr(tmpReg, tmpReg); |
|
2689 masm.jcc(Assembler::zero, DONE_LABEL); |
|
2690 |
|
2691 // If not recursive lock, reset the header to displaced header |
|
2692 if (os::is_MP()) { |
|
2693 masm.lock(); |
|
2694 } |
|
2695 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box |
|
2696 masm.bind(DONE_LABEL); |
|
2697 masm.nop(); // avoid branch to branch |
|
2698 } else { |
|
2699 Label DONE_LABEL, Stacked, CheckSucc ; |
|
2700 |
|
2701 if (UseBiasedLocking && !UseOptoBiasInlining) { |
|
2702 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL); |
|
2703 } |
|
2704 |
|
2705 masm.movptr(tmpReg, Address(objReg, 0)) ; |
|
2706 masm.cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD) ; |
|
2707 masm.jcc (Assembler::zero, DONE_LABEL) ; |
|
2708 masm.testl (tmpReg, 0x02) ; |
|
2709 masm.jcc (Assembler::zero, Stacked) ; |
|
2710 |
|
2711 // It's inflated |
|
2712 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; |
|
2713 masm.xorptr(boxReg, r15_thread) ; |
|
2714 masm.orptr (boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ; |
|
2715 masm.jcc (Assembler::notZero, DONE_LABEL) ; |
|
2716 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ; |
|
2717 masm.orptr (boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ; |
|
2718 masm.jcc (Assembler::notZero, CheckSucc) ; |
|
2719 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD) ; |
|
2720 masm.jmp (DONE_LABEL) ; |
|
2721 |
|
2722 if ((EmitSync & 65536) == 0) { |
|
2723 Label LSuccess, LGoSlowPath ; |
|
2724 masm.bind (CheckSucc) ; |
|
2725 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD) ; |
|
2726 masm.jcc (Assembler::zero, LGoSlowPath) ; |
|
2727 |
|
2728 // I'd much rather use lock:andl m->_owner, 0 as it's faster than the |
|
2729 // the explicit ST;MEMBAR combination, but masm doesn't currently support |
|
2730 // "ANDQ M,IMM". Don't use MFENCE here. lock:add to TOS, xchg, etc |
|
2731 // are all faster when the write buffer is populated. |
|
2732 masm.movptr (Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD) ; |
|
2733 if (os::is_MP()) { |
|
2734 masm.lock () ; masm.addl (Address(rsp, 0), 0) ; |
|
2735 } |
|
2736 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD) ; |
|
2737 masm.jcc (Assembler::notZero, LSuccess) ; |
|
2738 |
|
2739 masm.movptr (boxReg, (int32_t)NULL_WORD) ; // box is really EAX |
|
2740 if (os::is_MP()) { masm.lock(); } |
|
2741 masm.cmpxchgptr(r15_thread, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)); |
|
2742 masm.jcc (Assembler::notEqual, LSuccess) ; |
|
2743 // Intentional fall-through into slow-path |
|
2744 |
|
2745 masm.bind (LGoSlowPath) ; |
|
2746 masm.orl (boxReg, 1) ; // set ICC.ZF=0 to indicate failure |
|
2747 masm.jmp (DONE_LABEL) ; |
|
2748 |
|
2749 masm.bind (LSuccess) ; |
|
2750 masm.testl (boxReg, 0) ; // set ICC.ZF=1 to indicate success |
|
2751 masm.jmp (DONE_LABEL) ; |
|
2752 } |
|
2753 |
|
2754 masm.bind (Stacked) ; |
|
2755 masm.movptr(tmpReg, Address (boxReg, 0)) ; // re-fetch |
|
2756 if (os::is_MP()) { masm.lock(); } |
|
2757 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box |
|
2758 |
|
2759 if (EmitSync & 65536) { |
|
2760 masm.bind (CheckSucc) ; |
|
2761 } |
|
2762 masm.bind(DONE_LABEL); |
|
2763 if (EmitSync & 32768) { |
|
2764 masm.nop(); // avoid branch to branch |
|
2765 } |
|
2766 } |
|
2767 %} |
2530 %} |
2768 |
2531 |
2769 |
2532 |
2770 enc_class enc_rethrow() |
2533 enc_class enc_rethrow() |
2771 %{ |
2534 %{ |
6904 %} |
6693 %} |
6905 |
6694 |
6906 //----------Arithmetic Instructions-------------------------------------------- |
6695 //----------Arithmetic Instructions-------------------------------------------- |
6907 //----------Addition Instructions---------------------------------------------- |
6696 //----------Addition Instructions---------------------------------------------- |
6908 |
6697 |
6909 instruct addExactI_rReg(rax_RegI dst, rRegI src, rFlagsReg cr) |
|
6910 %{ |
|
6911 match(AddExactI dst src); |
|
6912 effect(DEF cr); |
|
6913 |
|
6914 format %{ "addl $dst, $src\t# addExact int" %} |
|
6915 ins_encode %{ |
|
6916 __ addl($dst$$Register, $src$$Register); |
|
6917 %} |
|
6918 ins_pipe(ialu_reg_reg); |
|
6919 %} |
|
6920 |
|
6921 instruct addExactI_rReg_imm(rax_RegI dst, immI src, rFlagsReg cr) |
|
6922 %{ |
|
6923 match(AddExactI dst src); |
|
6924 effect(DEF cr); |
|
6925 |
|
6926 format %{ "addl $dst, $src\t# addExact int" %} |
|
6927 ins_encode %{ |
|
6928 __ addl($dst$$Register, $src$$constant); |
|
6929 %} |
|
6930 ins_pipe(ialu_reg_reg); |
|
6931 %} |
|
6932 |
|
6933 instruct addExactI_rReg_mem(rax_RegI dst, memory src, rFlagsReg cr) |
|
6934 %{ |
|
6935 match(AddExactI dst (LoadI src)); |
|
6936 effect(DEF cr); |
|
6937 |
|
6938 ins_cost(125); // XXX |
|
6939 format %{ "addl $dst, $src\t# addExact int" %} |
|
6940 ins_encode %{ |
|
6941 __ addl($dst$$Register, $src$$Address); |
|
6942 %} |
|
6943 |
|
6944 ins_pipe(ialu_reg_mem); |
|
6945 %} |
|
6946 |
|
6947 instruct addExactL_rReg(rax_RegL dst, rRegL src, rFlagsReg cr) |
|
6948 %{ |
|
6949 match(AddExactL dst src); |
|
6950 effect(DEF cr); |
|
6951 |
|
6952 format %{ "addq $dst, $src\t# addExact long" %} |
|
6953 ins_encode %{ |
|
6954 __ addq($dst$$Register, $src$$Register); |
|
6955 %} |
|
6956 ins_pipe(ialu_reg_reg); |
|
6957 %} |
|
6958 |
|
6959 instruct addExactL_rReg_imm(rax_RegL dst, immL32 src, rFlagsReg cr) |
|
6960 %{ |
|
6961 match(AddExactL dst src); |
|
6962 effect(DEF cr); |
|
6963 |
|
6964 format %{ "addq $dst, $src\t# addExact long" %} |
|
6965 ins_encode %{ |
|
6966 __ addq($dst$$Register, $src$$constant); |
|
6967 %} |
|
6968 ins_pipe(ialu_reg_reg); |
|
6969 %} |
|
6970 |
|
6971 instruct addExactL_rReg_mem(rax_RegL dst, memory src, rFlagsReg cr) |
|
6972 %{ |
|
6973 match(AddExactL dst (LoadL src)); |
|
6974 effect(DEF cr); |
|
6975 |
|
6976 ins_cost(125); // XXX |
|
6977 format %{ "addq $dst, $src\t# addExact long" %} |
|
6978 ins_encode %{ |
|
6979 __ addq($dst$$Register, $src$$Address); |
|
6980 %} |
|
6981 |
|
6982 ins_pipe(ialu_reg_mem); |
|
6983 %} |
|
6984 |
|
6985 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr) |
6698 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr) |
6986 %{ |
6699 %{ |
6987 match(Set dst (AddI dst src)); |
6700 match(Set dst (AddI dst src)); |
6988 effect(KILL cr); |
6701 effect(KILL cr); |
6989 |
6702 |
7592 opcode(0x81); /* Opcode 81 /5 id */ |
7305 opcode(0x81); /* Opcode 81 /5 id */ |
7593 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src)); |
7306 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src)); |
7594 ins_pipe(ialu_mem_imm); |
7307 ins_pipe(ialu_mem_imm); |
7595 %} |
7308 %} |
7596 |
7309 |
7597 instruct subExactI_rReg(rax_RegI dst, rRegI src, rFlagsReg cr) |
|
7598 %{ |
|
7599 match(SubExactI dst src); |
|
7600 effect(DEF cr); |
|
7601 |
|
7602 format %{ "subl $dst, $src\t# subExact int" %} |
|
7603 ins_encode %{ |
|
7604 __ subl($dst$$Register, $src$$Register); |
|
7605 %} |
|
7606 ins_pipe(ialu_reg_reg); |
|
7607 %} |
|
7608 |
|
7609 instruct subExactI_rReg_imm(rax_RegI dst, immI src, rFlagsReg cr) |
|
7610 %{ |
|
7611 match(SubExactI dst src); |
|
7612 effect(DEF cr); |
|
7613 |
|
7614 format %{ "subl $dst, $src\t# subExact int" %} |
|
7615 ins_encode %{ |
|
7616 __ subl($dst$$Register, $src$$constant); |
|
7617 %} |
|
7618 ins_pipe(ialu_reg_reg); |
|
7619 %} |
|
7620 |
|
7621 instruct subExactI_rReg_mem(rax_RegI dst, memory src, rFlagsReg cr) |
|
7622 %{ |
|
7623 match(SubExactI dst (LoadI src)); |
|
7624 effect(DEF cr); |
|
7625 |
|
7626 ins_cost(125); |
|
7627 format %{ "subl $dst, $src\t# subExact int" %} |
|
7628 ins_encode %{ |
|
7629 __ subl($dst$$Register, $src$$Address); |
|
7630 %} |
|
7631 ins_pipe(ialu_reg_mem); |
|
7632 %} |
|
7633 |
|
7634 instruct subExactL_rReg(rax_RegL dst, rRegL src, rFlagsReg cr) |
|
7635 %{ |
|
7636 match(SubExactL dst src); |
|
7637 effect(DEF cr); |
|
7638 |
|
7639 format %{ "subq $dst, $src\t# subExact long" %} |
|
7640 ins_encode %{ |
|
7641 __ subq($dst$$Register, $src$$Register); |
|
7642 %} |
|
7643 ins_pipe(ialu_reg_reg); |
|
7644 %} |
|
7645 |
|
7646 instruct subExactL_rReg_imm(rax_RegL dst, immL32 src, rFlagsReg cr) |
|
7647 %{ |
|
7648 match(SubExactL dst (LoadL src)); |
|
7649 effect(DEF cr); |
|
7650 |
|
7651 format %{ "subq $dst, $src\t# subExact long" %} |
|
7652 ins_encode %{ |
|
7653 __ subq($dst$$Register, $src$$constant); |
|
7654 %} |
|
7655 ins_pipe(ialu_reg_reg); |
|
7656 %} |
|
7657 |
|
7658 instruct subExactL_rReg_mem(rax_RegI dst, memory src, rFlagsReg cr) |
|
7659 %{ |
|
7660 match(SubExactI dst src); |
|
7661 effect(DEF cr); |
|
7662 |
|
7663 ins_cost(125); |
|
7664 format %{ "subq $dst, $src\t# subExact long" %} |
|
7665 ins_encode %{ |
|
7666 __ subq($dst$$Register, $src$$Address); |
|
7667 %} |
|
7668 ins_pipe(ialu_reg_mem); |
|
7669 %} |
|
7670 |
|
7671 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr) |
7310 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr) |
7672 %{ |
7311 %{ |
7673 match(Set dst (SubL dst src)); |
7312 match(Set dst (SubL dst src)); |
7674 effect(KILL cr); |
7313 effect(KILL cr); |
7675 |
7314 |
7921 ins_cost(300); |
7535 ins_cost(300); |
7922 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %} |
7536 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %} |
7923 opcode(0xF7, 0x5); /* Opcode F7 /5 */ |
7537 opcode(0xF7, 0x5); /* Opcode F7 /5 */ |
7924 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src)); |
7538 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src)); |
7925 ins_pipe(ialu_reg_reg_alu0); |
7539 ins_pipe(ialu_reg_reg_alu0); |
7926 %} |
|
7927 |
|
7928 |
|
7929 instruct mulExactI_rReg(rax_RegI dst, rRegI src, rFlagsReg cr) |
|
7930 %{ |
|
7931 match(MulExactI dst src); |
|
7932 effect(DEF cr); |
|
7933 |
|
7934 ins_cost(300); |
|
7935 format %{ "imull $dst, $src\t# mulExact int" %} |
|
7936 ins_encode %{ |
|
7937 __ imull($dst$$Register, $src$$Register); |
|
7938 %} |
|
7939 ins_pipe(ialu_reg_reg_alu0); |
|
7940 %} |
|
7941 |
|
7942 |
|
7943 instruct mulExactI_rReg_imm(rax_RegI dst, rRegI src, immI imm, rFlagsReg cr) |
|
7944 %{ |
|
7945 match(MulExactI src imm); |
|
7946 effect(DEF cr); |
|
7947 |
|
7948 ins_cost(300); |
|
7949 format %{ "imull $dst, $src, $imm\t# mulExact int" %} |
|
7950 ins_encode %{ |
|
7951 __ imull($dst$$Register, $src$$Register, $imm$$constant); |
|
7952 %} |
|
7953 ins_pipe(ialu_reg_reg_alu0); |
|
7954 %} |
|
7955 |
|
7956 instruct mulExactI_rReg_mem(rax_RegI dst, memory src, rFlagsReg cr) |
|
7957 %{ |
|
7958 match(MulExactI dst (LoadI src)); |
|
7959 effect(DEF cr); |
|
7960 |
|
7961 ins_cost(350); |
|
7962 format %{ "imull $dst, $src\t# mulExact int" %} |
|
7963 ins_encode %{ |
|
7964 __ imull($dst$$Register, $src$$Address); |
|
7965 %} |
|
7966 ins_pipe(ialu_reg_mem_alu0); |
|
7967 %} |
|
7968 |
|
7969 instruct mulExactL_rReg(rax_RegL dst, rRegL src, rFlagsReg cr) |
|
7970 %{ |
|
7971 match(MulExactL dst src); |
|
7972 effect(DEF cr); |
|
7973 |
|
7974 ins_cost(300); |
|
7975 format %{ "imulq $dst, $src\t# mulExact long" %} |
|
7976 ins_encode %{ |
|
7977 __ imulq($dst$$Register, $src$$Register); |
|
7978 %} |
|
7979 ins_pipe(ialu_reg_reg_alu0); |
|
7980 %} |
|
7981 |
|
7982 instruct mulExactL_rReg_imm(rax_RegL dst, rRegL src, immL32 imm, rFlagsReg cr) |
|
7983 %{ |
|
7984 match(MulExactL src imm); |
|
7985 effect(DEF cr); |
|
7986 |
|
7987 ins_cost(300); |
|
7988 format %{ "imulq $dst, $src, $imm\t# mulExact long" %} |
|
7989 ins_encode %{ |
|
7990 __ imulq($dst$$Register, $src$$Register, $imm$$constant); |
|
7991 %} |
|
7992 ins_pipe(ialu_reg_reg_alu0); |
|
7993 %} |
|
7994 |
|
7995 instruct mulExactL_rReg_mem(rax_RegL dst, memory src, rFlagsReg cr) |
|
7996 %{ |
|
7997 match(MulExactL dst (LoadL src)); |
|
7998 effect(DEF cr); |
|
7999 |
|
8000 ins_cost(350); |
|
8001 format %{ "imulq $dst, $src\t# mulExact long" %} |
|
8002 ins_encode %{ |
|
8003 __ imulq($dst$$Register, $src$$Address); |
|
8004 %} |
|
8005 ins_pipe(ialu_reg_mem_alu0); |
|
8006 %} |
7540 %} |
8007 |
7541 |
8008 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div, |
7542 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div, |
8009 rFlagsReg cr) |
7543 rFlagsReg cr) |
8010 %{ |
7544 %{ |
9055 ins_encode(REX_mem(dst), OpcSE(src), |
8589 ins_encode(REX_mem(dst), OpcSE(src), |
9056 RM_opc_mem(secondary, dst), Con8or32(src)); |
8590 RM_opc_mem(secondary, dst), Con8or32(src)); |
9057 ins_pipe(ialu_mem_imm); |
8591 ins_pipe(ialu_mem_imm); |
9058 %} |
8592 %} |
9059 |
8593 |
|
8594 // BMI1 instructions |
|
8595 instruct andnI_rReg_rReg_mem(rRegI dst, rRegI src1, memory src2, immI_M1 minus_1, rFlagsReg cr) %{ |
|
8596 match(Set dst (AndI (XorI src1 minus_1) (LoadI src2))); |
|
8597 predicate(UseBMI1Instructions); |
|
8598 effect(KILL cr); |
|
8599 |
|
8600 ins_cost(125); |
|
8601 format %{ "andnl $dst, $src1, $src2" %} |
|
8602 |
|
8603 ins_encode %{ |
|
8604 __ andnl($dst$$Register, $src1$$Register, $src2$$Address); |
|
8605 %} |
|
8606 ins_pipe(ialu_reg_mem); |
|
8607 %} |
|
8608 |
|
8609 instruct andnI_rReg_rReg_rReg(rRegI dst, rRegI src1, rRegI src2, immI_M1 minus_1, rFlagsReg cr) %{ |
|
8610 match(Set dst (AndI (XorI src1 minus_1) src2)); |
|
8611 predicate(UseBMI1Instructions); |
|
8612 effect(KILL cr); |
|
8613 |
|
8614 format %{ "andnl $dst, $src1, $src2" %} |
|
8615 |
|
8616 ins_encode %{ |
|
8617 __ andnl($dst$$Register, $src1$$Register, $src2$$Register); |
|
8618 %} |
|
8619 ins_pipe(ialu_reg); |
|
8620 %} |
|
8621 |
|
8622 instruct blsiI_rReg_rReg(rRegI dst, rRegI src, immI0 imm_zero, rFlagsReg cr) %{ |
|
8623 match(Set dst (AndI (SubI imm_zero src) src)); |
|
8624 predicate(UseBMI1Instructions); |
|
8625 effect(KILL cr); |
|
8626 |
|
8627 format %{ "blsil $dst, $src" %} |
|
8628 |
|
8629 ins_encode %{ |
|
8630 __ blsil($dst$$Register, $src$$Register); |
|
8631 %} |
|
8632 ins_pipe(ialu_reg); |
|
8633 %} |
|
8634 |
|
8635 instruct blsiI_rReg_mem(rRegI dst, memory src, immI0 imm_zero, rFlagsReg cr) %{ |
|
8636 match(Set dst (AndI (SubI imm_zero (LoadI src) ) (LoadI src) )); |
|
8637 predicate(UseBMI1Instructions); |
|
8638 effect(KILL cr); |
|
8639 |
|
8640 ins_cost(125); |
|
8641 format %{ "blsil $dst, $src" %} |
|
8642 |
|
8643 ins_encode %{ |
|
8644 __ blsil($dst$$Register, $src$$Address); |
|
8645 %} |
|
8646 ins_pipe(ialu_reg_mem); |
|
8647 %} |
|
8648 |
|
8649 instruct blsmskI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr) |
|
8650 %{ |
|
8651 match(Set dst (XorI (AddI (LoadI src) minus_1) (LoadI src) ) ); |
|
8652 predicate(UseBMI1Instructions); |
|
8653 effect(KILL cr); |
|
8654 |
|
8655 ins_cost(125); |
|
8656 format %{ "blsmskl $dst, $src" %} |
|
8657 |
|
8658 ins_encode %{ |
|
8659 __ blsmskl($dst$$Register, $src$$Address); |
|
8660 %} |
|
8661 ins_pipe(ialu_reg_mem); |
|
8662 %} |
|
8663 |
|
8664 instruct blsmskI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr) |
|
8665 %{ |
|
8666 match(Set dst (XorI (AddI src minus_1) src)); |
|
8667 predicate(UseBMI1Instructions); |
|
8668 effect(KILL cr); |
|
8669 |
|
8670 format %{ "blsmskl $dst, $src" %} |
|
8671 |
|
8672 ins_encode %{ |
|
8673 __ blsmskl($dst$$Register, $src$$Register); |
|
8674 %} |
|
8675 |
|
8676 ins_pipe(ialu_reg); |
|
8677 %} |
|
8678 |
|
8679 instruct blsrI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr) |
|
8680 %{ |
|
8681 match(Set dst (AndI (AddI src minus_1) src) ); |
|
8682 predicate(UseBMI1Instructions); |
|
8683 effect(KILL cr); |
|
8684 |
|
8685 format %{ "blsrl $dst, $src" %} |
|
8686 |
|
8687 ins_encode %{ |
|
8688 __ blsrl($dst$$Register, $src$$Register); |
|
8689 %} |
|
8690 |
|
8691 ins_pipe(ialu_reg_mem); |
|
8692 %} |
|
8693 |
|
8694 instruct blsrI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr) |
|
8695 %{ |
|
8696 match(Set dst (AndI (AddI (LoadI src) minus_1) (LoadI src) ) ); |
|
8697 predicate(UseBMI1Instructions); |
|
8698 effect(KILL cr); |
|
8699 |
|
8700 ins_cost(125); |
|
8701 format %{ "blsrl $dst, $src" %} |
|
8702 |
|
8703 ins_encode %{ |
|
8704 __ blsrl($dst$$Register, $src$$Address); |
|
8705 %} |
|
8706 |
|
8707 ins_pipe(ialu_reg); |
|
8708 %} |
|
8709 |
9060 // Or Instructions |
8710 // Or Instructions |
9061 // Or Register with Register |
8711 // Or Register with Register |
9062 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr) |
8712 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr) |
9063 %{ |
8713 %{ |
9064 match(Set dst (OrI dst src)); |
8714 match(Set dst (OrI dst src)); |
9284 format %{ "andq $dst, $src\t# long" %} |
8934 format %{ "andq $dst, $src\t# long" %} |
9285 opcode(0x81, 0x4); /* Opcode 81 /4 id */ |
8935 opcode(0x81, 0x4); /* Opcode 81 /4 id */ |
9286 ins_encode(REX_mem_wide(dst), OpcSE(src), |
8936 ins_encode(REX_mem_wide(dst), OpcSE(src), |
9287 RM_opc_mem(secondary, dst), Con8or32(src)); |
8937 RM_opc_mem(secondary, dst), Con8or32(src)); |
9288 ins_pipe(ialu_mem_imm); |
8938 ins_pipe(ialu_mem_imm); |
|
8939 %} |
|
8940 |
|
8941 // BMI1 instructions |
|
8942 instruct andnL_rReg_rReg_mem(rRegL dst, rRegL src1, memory src2, immL_M1 minus_1, rFlagsReg cr) %{ |
|
8943 match(Set dst (AndL (XorL src1 minus_1) (LoadL src2))); |
|
8944 predicate(UseBMI1Instructions); |
|
8945 effect(KILL cr); |
|
8946 |
|
8947 ins_cost(125); |
|
8948 format %{ "andnq $dst, $src1, $src2" %} |
|
8949 |
|
8950 ins_encode %{ |
|
8951 __ andnq($dst$$Register, $src1$$Register, $src2$$Address); |
|
8952 %} |
|
8953 ins_pipe(ialu_reg_mem); |
|
8954 %} |
|
8955 |
|
8956 instruct andnL_rReg_rReg_rReg(rRegL dst, rRegL src1, rRegL src2, immL_M1 minus_1, rFlagsReg cr) %{ |
|
8957 match(Set dst (AndL (XorL src1 minus_1) src2)); |
|
8958 predicate(UseBMI1Instructions); |
|
8959 effect(KILL cr); |
|
8960 |
|
8961 format %{ "andnq $dst, $src1, $src2" %} |
|
8962 |
|
8963 ins_encode %{ |
|
8964 __ andnq($dst$$Register, $src1$$Register, $src2$$Register); |
|
8965 %} |
|
8966 ins_pipe(ialu_reg_mem); |
|
8967 %} |
|
8968 |
|
8969 instruct blsiL_rReg_rReg(rRegL dst, rRegL src, immL0 imm_zero, rFlagsReg cr) %{ |
|
8970 match(Set dst (AndL (SubL imm_zero src) src)); |
|
8971 predicate(UseBMI1Instructions); |
|
8972 effect(KILL cr); |
|
8973 |
|
8974 format %{ "blsiq $dst, $src" %} |
|
8975 |
|
8976 ins_encode %{ |
|
8977 __ blsiq($dst$$Register, $src$$Register); |
|
8978 %} |
|
8979 ins_pipe(ialu_reg); |
|
8980 %} |
|
8981 |
|
8982 instruct blsiL_rReg_mem(rRegL dst, memory src, immL0 imm_zero, rFlagsReg cr) %{ |
|
8983 match(Set dst (AndL (SubL imm_zero (LoadL src) ) (LoadL src) )); |
|
8984 predicate(UseBMI1Instructions); |
|
8985 effect(KILL cr); |
|
8986 |
|
8987 ins_cost(125); |
|
8988 format %{ "blsiq $dst, $src" %} |
|
8989 |
|
8990 ins_encode %{ |
|
8991 __ blsiq($dst$$Register, $src$$Address); |
|
8992 %} |
|
8993 ins_pipe(ialu_reg_mem); |
|
8994 %} |
|
8995 |
|
8996 instruct blsmskL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr) |
|
8997 %{ |
|
8998 match(Set dst (XorL (AddL (LoadL src) minus_1) (LoadL src) ) ); |
|
8999 predicate(UseBMI1Instructions); |
|
9000 effect(KILL cr); |
|
9001 |
|
9002 ins_cost(125); |
|
9003 format %{ "blsmskq $dst, $src" %} |
|
9004 |
|
9005 ins_encode %{ |
|
9006 __ blsmskq($dst$$Register, $src$$Address); |
|
9007 %} |
|
9008 ins_pipe(ialu_reg_mem); |
|
9009 %} |
|
9010 |
|
9011 instruct blsmskL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr) |
|
9012 %{ |
|
9013 match(Set dst (XorL (AddL src minus_1) src)); |
|
9014 predicate(UseBMI1Instructions); |
|
9015 effect(KILL cr); |
|
9016 |
|
9017 format %{ "blsmskq $dst, $src" %} |
|
9018 |
|
9019 ins_encode %{ |
|
9020 __ blsmskq($dst$$Register, $src$$Register); |
|
9021 %} |
|
9022 |
|
9023 ins_pipe(ialu_reg); |
|
9024 %} |
|
9025 |
|
9026 instruct blsrL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr) |
|
9027 %{ |
|
9028 match(Set dst (AndL (AddL src minus_1) src) ); |
|
9029 predicate(UseBMI1Instructions); |
|
9030 effect(KILL cr); |
|
9031 |
|
9032 format %{ "blsrq $dst, $src" %} |
|
9033 |
|
9034 ins_encode %{ |
|
9035 __ blsrq($dst$$Register, $src$$Register); |
|
9036 %} |
|
9037 |
|
9038 ins_pipe(ialu_reg); |
|
9039 %} |
|
9040 |
|
9041 instruct blsrL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr) |
|
9042 %{ |
|
9043 match(Set dst (AndL (AddL (LoadL src) minus_1) (LoadL src)) ); |
|
9044 predicate(UseBMI1Instructions); |
|
9045 effect(KILL cr); |
|
9046 |
|
9047 ins_cost(125); |
|
9048 format %{ "blsrq $dst, $src" %} |
|
9049 |
|
9050 ins_encode %{ |
|
9051 __ blsrq($dst$$Register, $src$$Address); |
|
9052 %} |
|
9053 |
|
9054 ins_pipe(ialu_reg); |
9289 %} |
9055 %} |
9290 |
9056 |
9291 // Or Instructions |
9057 // Or Instructions |
9292 // Or Register with Register |
9058 // Or Register with Register |
9293 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr) |
9059 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr) |
10611 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register); |
10377 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register); |
10612 %} |
10378 %} |
10613 ins_pipe( pipe_slow ); |
10379 ins_pipe( pipe_slow ); |
10614 %} |
10380 %} |
10615 |
10381 |
|
10382 //----------Overflow Math Instructions----------------------------------------- |
|
10383 |
|
10384 instruct overflowAddI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2) |
|
10385 %{ |
|
10386 match(Set cr (OverflowAddI op1 op2)); |
|
10387 effect(DEF cr, USE_KILL op1, USE op2); |
|
10388 |
|
10389 format %{ "addl $op1, $op2\t# overflow check int" %} |
|
10390 |
|
10391 ins_encode %{ |
|
10392 __ addl($op1$$Register, $op2$$Register); |
|
10393 %} |
|
10394 ins_pipe(ialu_reg_reg); |
|
10395 %} |
|
10396 |
|
10397 instruct overflowAddI_rReg_imm(rFlagsReg cr, rax_RegI op1, immI op2) |
|
10398 %{ |
|
10399 match(Set cr (OverflowAddI op1 op2)); |
|
10400 effect(DEF cr, USE_KILL op1, USE op2); |
|
10401 |
|
10402 format %{ "addl $op1, $op2\t# overflow check int" %} |
|
10403 |
|
10404 ins_encode %{ |
|
10405 __ addl($op1$$Register, $op2$$constant); |
|
10406 %} |
|
10407 ins_pipe(ialu_reg_reg); |
|
10408 %} |
|
10409 |
|
10410 instruct overflowAddL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2) |
|
10411 %{ |
|
10412 match(Set cr (OverflowAddL op1 op2)); |
|
10413 effect(DEF cr, USE_KILL op1, USE op2); |
|
10414 |
|
10415 format %{ "addq $op1, $op2\t# overflow check long" %} |
|
10416 ins_encode %{ |
|
10417 __ addq($op1$$Register, $op2$$Register); |
|
10418 %} |
|
10419 ins_pipe(ialu_reg_reg); |
|
10420 %} |
|
10421 |
|
10422 instruct overflowAddL_rReg_imm(rFlagsReg cr, rax_RegL op1, immL32 op2) |
|
10423 %{ |
|
10424 match(Set cr (OverflowAddL op1 op2)); |
|
10425 effect(DEF cr, USE_KILL op1, USE op2); |
|
10426 |
|
10427 format %{ "addq $op1, $op2\t# overflow check long" %} |
|
10428 ins_encode %{ |
|
10429 __ addq($op1$$Register, $op2$$constant); |
|
10430 %} |
|
10431 ins_pipe(ialu_reg_reg); |
|
10432 %} |
|
10433 |
|
10434 instruct overflowSubI_rReg(rFlagsReg cr, rRegI op1, rRegI op2) |
|
10435 %{ |
|
10436 match(Set cr (OverflowSubI op1 op2)); |
|
10437 |
|
10438 format %{ "cmpl $op1, $op2\t# overflow check int" %} |
|
10439 ins_encode %{ |
|
10440 __ cmpl($op1$$Register, $op2$$Register); |
|
10441 %} |
|
10442 ins_pipe(ialu_reg_reg); |
|
10443 %} |
|
10444 |
|
10445 instruct overflowSubI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2) |
|
10446 %{ |
|
10447 match(Set cr (OverflowSubI op1 op2)); |
|
10448 |
|
10449 format %{ "cmpl $op1, $op2\t# overflow check int" %} |
|
10450 ins_encode %{ |
|
10451 __ cmpl($op1$$Register, $op2$$constant); |
|
10452 %} |
|
10453 ins_pipe(ialu_reg_reg); |
|
10454 %} |
|
10455 |
|
10456 instruct overflowSubL_rReg(rFlagsReg cr, rRegL op1, rRegL op2) |
|
10457 %{ |
|
10458 match(Set cr (OverflowSubL op1 op2)); |
|
10459 |
|
10460 format %{ "cmpq $op1, $op2\t# overflow check long" %} |
|
10461 ins_encode %{ |
|
10462 __ cmpq($op1$$Register, $op2$$Register); |
|
10463 %} |
|
10464 ins_pipe(ialu_reg_reg); |
|
10465 %} |
|
10466 |
|
10467 instruct overflowSubL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2) |
|
10468 %{ |
|
10469 match(Set cr (OverflowSubL op1 op2)); |
|
10470 |
|
10471 format %{ "cmpq $op1, $op2\t# overflow check long" %} |
|
10472 ins_encode %{ |
|
10473 __ cmpq($op1$$Register, $op2$$constant); |
|
10474 %} |
|
10475 ins_pipe(ialu_reg_reg); |
|
10476 %} |
|
10477 |
|
10478 instruct overflowNegI_rReg(rFlagsReg cr, immI0 zero, rax_RegI op2) |
|
10479 %{ |
|
10480 match(Set cr (OverflowSubI zero op2)); |
|
10481 effect(DEF cr, USE_KILL op2); |
|
10482 |
|
10483 format %{ "negl $op2\t# overflow check int" %} |
|
10484 ins_encode %{ |
|
10485 __ negl($op2$$Register); |
|
10486 %} |
|
10487 ins_pipe(ialu_reg_reg); |
|
10488 %} |
|
10489 |
|
10490 instruct overflowNegL_rReg(rFlagsReg cr, immL0 zero, rax_RegL op2) |
|
10491 %{ |
|
10492 match(Set cr (OverflowSubL zero op2)); |
|
10493 effect(DEF cr, USE_KILL op2); |
|
10494 |
|
10495 format %{ "negq $op2\t# overflow check long" %} |
|
10496 ins_encode %{ |
|
10497 __ negq($op2$$Register); |
|
10498 %} |
|
10499 ins_pipe(ialu_reg_reg); |
|
10500 %} |
|
10501 |
|
10502 instruct overflowMulI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2) |
|
10503 %{ |
|
10504 match(Set cr (OverflowMulI op1 op2)); |
|
10505 effect(DEF cr, USE_KILL op1, USE op2); |
|
10506 |
|
10507 format %{ "imull $op1, $op2\t# overflow check int" %} |
|
10508 ins_encode %{ |
|
10509 __ imull($op1$$Register, $op2$$Register); |
|
10510 %} |
|
10511 ins_pipe(ialu_reg_reg_alu0); |
|
10512 %} |
|
10513 |
|
10514 instruct overflowMulI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2, rRegI tmp) |
|
10515 %{ |
|
10516 match(Set cr (OverflowMulI op1 op2)); |
|
10517 effect(DEF cr, TEMP tmp, USE op1, USE op2); |
|
10518 |
|
10519 format %{ "imull $tmp, $op1, $op2\t# overflow check int" %} |
|
10520 ins_encode %{ |
|
10521 __ imull($tmp$$Register, $op1$$Register, $op2$$constant); |
|
10522 %} |
|
10523 ins_pipe(ialu_reg_reg_alu0); |
|
10524 %} |
|
10525 |
|
10526 instruct overflowMulL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2) |
|
10527 %{ |
|
10528 match(Set cr (OverflowMulL op1 op2)); |
|
10529 effect(DEF cr, USE_KILL op1, USE op2); |
|
10530 |
|
10531 format %{ "imulq $op1, $op2\t# overflow check long" %} |
|
10532 ins_encode %{ |
|
10533 __ imulq($op1$$Register, $op2$$Register); |
|
10534 %} |
|
10535 ins_pipe(ialu_reg_reg_alu0); |
|
10536 %} |
|
10537 |
|
10538 instruct overflowMulL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2, rRegL tmp) |
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10539 %{ |
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10540 match(Set cr (OverflowMulL op1 op2)); |
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10541 effect(DEF cr, TEMP tmp, USE op1, USE op2); |
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10542 |
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10543 format %{ "imulq $tmp, $op1, $op2\t# overflow check long" %} |
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10544 ins_encode %{ |
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10545 __ imulq($tmp$$Register, $op1$$Register, $op2$$constant); |
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10546 %} |
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10547 ins_pipe(ialu_reg_reg_alu0); |
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10548 %} |
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10549 |
10616 |
10550 |
10617 //----------Control Flow Instructions------------------------------------------ |
10551 //----------Control Flow Instructions------------------------------------------ |
10618 // Signed compare Instructions |
10552 // Signed compare Instructions |
10619 |
10553 |
10620 // XXX more variants!! |
10554 // XXX more variants!! |
11394 %} |
11328 %} |
11395 |
11329 |
11396 // ============================================================================ |
11330 // ============================================================================ |
11397 // inlined locking and unlocking |
11331 // inlined locking and unlocking |
11398 |
11332 |
11399 instruct cmpFastLock(rFlagsReg cr, |
11333 instruct cmpFastLockRTM(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rdx_RegI scr, rRegI cx1, rRegI cx2) %{ |
11400 rRegP object, rbx_RegP box, rax_RegI tmp, rRegP scr) |
11334 predicate(Compile::current()->use_rtm()); |
11401 %{ |
11335 match(Set cr (FastLock object box)); |
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11336 effect(TEMP tmp, TEMP scr, TEMP cx1, TEMP cx2, USE_KILL box); |
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11337 ins_cost(300); |
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11338 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr,$cx1,$cx2" %} |
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11339 ins_encode %{ |
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11340 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register, |
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11341 $scr$$Register, $cx1$$Register, $cx2$$Register, |
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11342 _counters, _rtm_counters, _stack_rtm_counters, |
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11343 ((Method*)(ra_->C->method()->constant_encoding()))->method_data(), |
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11344 true, ra_->C->profile_rtm()); |
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11345 %} |
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11346 ins_pipe(pipe_slow); |
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11347 %} |
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11348 |
|
11349 instruct cmpFastLock(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rRegP scr) %{ |
|
11350 predicate(!Compile::current()->use_rtm()); |
11402 match(Set cr (FastLock object box)); |
11351 match(Set cr (FastLock object box)); |
11403 effect(TEMP tmp, TEMP scr, USE_KILL box); |
11352 effect(TEMP tmp, TEMP scr, USE_KILL box); |
11404 |
|
11405 ins_cost(300); |
11353 ins_cost(300); |
11406 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr" %} |
11354 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr" %} |
11407 ins_encode(Fast_Lock(object, box, tmp, scr)); |
11355 ins_encode %{ |
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11356 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register, |
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11357 $scr$$Register, noreg, noreg, _counters, NULL, NULL, NULL, false, false); |
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11358 %} |
11408 ins_pipe(pipe_slow); |
11359 ins_pipe(pipe_slow); |
11409 %} |
11360 %} |
11410 |
11361 |
11411 instruct cmpFastUnlock(rFlagsReg cr, |
11362 instruct cmpFastUnlock(rFlagsReg cr, rRegP object, rax_RegP box, rRegP tmp) %{ |
11412 rRegP object, rax_RegP box, rRegP tmp) |
|
11413 %{ |
|
11414 match(Set cr (FastUnlock object box)); |
11363 match(Set cr (FastUnlock object box)); |
11415 effect(TEMP tmp, USE_KILL box); |
11364 effect(TEMP tmp, USE_KILL box); |
11416 |
|
11417 ins_cost(300); |
11365 ins_cost(300); |
11418 format %{ "fastunlock $object,$box\t! kills $box,$tmp" %} |
11366 format %{ "fastunlock $object,$box\t! kills $box,$tmp" %} |
11419 ins_encode(Fast_Unlock(object, box, tmp)); |
11367 ins_encode %{ |
|
11368 __ fast_unlock($object$$Register, $box$$Register, $tmp$$Register, ra_->C->use_rtm()); |
|
11369 %} |
11420 ins_pipe(pipe_slow); |
11370 ins_pipe(pipe_slow); |
11421 %} |
11371 %} |
11422 |
11372 |
11423 |
11373 |
11424 // ============================================================================ |
11374 // ============================================================================ |