650 case lir_cond_less: acond = (is_unordered ? Assembler::f_unorderedOrLess : Assembler::f_less); break; |
643 case lir_cond_less: acond = (is_unordered ? Assembler::f_unorderedOrLess : Assembler::f_less); break; |
651 case lir_cond_greater: acond = (is_unordered ? Assembler::f_unorderedOrGreater : Assembler::f_greater); break; |
644 case lir_cond_greater: acond = (is_unordered ? Assembler::f_unorderedOrGreater : Assembler::f_greater); break; |
652 case lir_cond_lessEqual: acond = (is_unordered ? Assembler::f_unorderedOrLessOrEqual : Assembler::f_lessOrEqual); break; |
645 case lir_cond_lessEqual: acond = (is_unordered ? Assembler::f_unorderedOrLessOrEqual : Assembler::f_lessOrEqual); break; |
653 case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::f_unorderedOrGreaterOrEqual: Assembler::f_greaterOrEqual); break; |
646 case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::f_unorderedOrGreaterOrEqual: Assembler::f_greaterOrEqual); break; |
654 default : ShouldNotReachHere(); |
647 default : ShouldNotReachHere(); |
655 }; |
|
656 |
|
657 if (!VM_Version::v9_instructions_work()) { |
|
658 __ nop(); |
|
659 } |
648 } |
660 __ fb( acond, false, Assembler::pn, *(op->label())); |
649 __ fb( acond, false, Assembler::pn, *(op->label())); |
661 } else { |
650 } else { |
662 assert (op->code() == lir_branch, "just checking"); |
651 assert (op->code() == lir_branch, "just checking"); |
663 |
652 |
723 FloatRegister rsrc = op->in_opr()->as_float_reg(); |
712 FloatRegister rsrc = op->in_opr()->as_float_reg(); |
724 Address addr = frame_map()->address_for_slot(dst->single_stack_ix()); |
713 Address addr = frame_map()->address_for_slot(dst->single_stack_ix()); |
725 Label L; |
714 Label L; |
726 // result must be 0 if value is NaN; test by comparing value to itself |
715 // result must be 0 if value is NaN; test by comparing value to itself |
727 __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, rsrc, rsrc); |
716 __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, rsrc, rsrc); |
728 if (!VM_Version::v9_instructions_work()) { |
|
729 __ nop(); |
|
730 } |
|
731 __ fb(Assembler::f_unordered, true, Assembler::pn, L); |
717 __ fb(Assembler::f_unordered, true, Assembler::pn, L); |
732 __ delayed()->st(G0, addr); // annuled if contents of rsrc is not NaN |
718 __ delayed()->st(G0, addr); // annuled if contents of rsrc is not NaN |
733 __ ftoi(FloatRegisterImpl::S, rsrc, rsrc); |
719 __ ftoi(FloatRegisterImpl::S, rsrc, rsrc); |
734 // move integer result from float register to int register |
720 // move integer result from float register to int register |
735 __ stf(FloatRegisterImpl::S, rsrc, addr.base(), addr.disp()); |
721 __ stf(FloatRegisterImpl::S, rsrc, addr.base(), addr.disp()); |
1907 Register res = dest->as_register(); |
1893 Register res = dest->as_register(); |
1908 Register rreg = right->as_register(); |
1894 Register rreg = right->as_register(); |
1909 switch (code) { |
1895 switch (code) { |
1910 case lir_add: __ add (lreg, rreg, res); break; |
1896 case lir_add: __ add (lreg, rreg, res); break; |
1911 case lir_sub: __ sub (lreg, rreg, res); break; |
1897 case lir_sub: __ sub (lreg, rreg, res); break; |
1912 case lir_mul: __ mult (lreg, rreg, res); break; |
1898 case lir_mul: __ mulx (lreg, rreg, res); break; |
1913 default: ShouldNotReachHere(); |
1899 default: ShouldNotReachHere(); |
1914 } |
1900 } |
1915 } |
1901 } |
1916 } else { |
1902 } else { |
1917 assert (right->is_constant(), "must be constant"); |
1903 assert (right->is_constant(), "must be constant"); |
1922 int simm13 = right->as_constant_ptr()->as_jint(); |
1908 int simm13 = right->as_constant_ptr()->as_jint(); |
1923 |
1909 |
1924 switch (code) { |
1910 switch (code) { |
1925 case lir_add: __ add (lreg, simm13, res); break; |
1911 case lir_add: __ add (lreg, simm13, res); break; |
1926 case lir_sub: __ sub (lreg, simm13, res); break; |
1912 case lir_sub: __ sub (lreg, simm13, res); break; |
1927 case lir_mul: __ mult (lreg, simm13, res); break; |
1913 case lir_mul: __ mulx (lreg, simm13, res); break; |
1928 default: ShouldNotReachHere(); |
1914 default: ShouldNotReachHere(); |
1929 } |
1915 } |
1930 } else { |
1916 } else { |
1931 Register lreg = left->as_pointer_register(); |
1917 Register lreg = left->as_pointer_register(); |
1932 Register res = dest->as_register_lo(); |
1918 Register res = dest->as_register_lo(); |
1934 assert(Assembler::is_simm13(con), "must be simm13"); |
1920 assert(Assembler::is_simm13(con), "must be simm13"); |
1935 |
1921 |
1936 switch (code) { |
1922 switch (code) { |
1937 case lir_add: __ add (lreg, (int)con, res); break; |
1923 case lir_add: __ add (lreg, (int)con, res); break; |
1938 case lir_sub: __ sub (lreg, (int)con, res); break; |
1924 case lir_sub: __ sub (lreg, (int)con, res); break; |
1939 case lir_mul: __ mult (lreg, (int)con, res); break; |
1925 case lir_mul: __ mulx (lreg, (int)con, res); break; |
1940 default: ShouldNotReachHere(); |
1926 default: ShouldNotReachHere(); |
1941 } |
1927 } |
1942 } |
1928 } |
1943 } |
1929 } |
1944 } |
1930 } |
3232 int null_check_offset = -1; |
3218 int null_check_offset = -1; |
3233 |
3219 |
3234 Register base = mem_addr->base()->as_register(); |
3220 Register base = mem_addr->base()->as_register(); |
3235 if (src->is_register() && dest->is_address()) { |
3221 if (src->is_register() && dest->is_address()) { |
3236 // G4 is high half, G5 is low half |
3222 // G4 is high half, G5 is low half |
3237 if (VM_Version::v9_instructions_work()) { |
3223 // clear the top bits of G5, and scale up G4 |
3238 // clear the top bits of G5, and scale up G4 |
3224 __ srl (src->as_register_lo(), 0, G5); |
3239 __ srl (src->as_register_lo(), 0, G5); |
3225 __ sllx(src->as_register_hi(), 32, G4); |
3240 __ sllx(src->as_register_hi(), 32, G4); |
3226 // combine the two halves into the 64 bits of G4 |
3241 // combine the two halves into the 64 bits of G4 |
3227 __ or3(G4, G5, G4); |
3242 __ or3(G4, G5, G4); |
3228 null_check_offset = __ offset(); |
3243 null_check_offset = __ offset(); |
3229 if (idx == noreg) { |
3244 if (idx == noreg) { |
3230 __ stx(G4, base, disp); |
3245 __ stx(G4, base, disp); |
|
3246 } else { |
|
3247 __ stx(G4, base, idx); |
|
3248 } |
|
3249 } else { |
3231 } else { |
3250 __ mov (src->as_register_hi(), G4); |
3232 __ stx(G4, base, idx); |
3251 __ mov (src->as_register_lo(), G5); |
|
3252 null_check_offset = __ offset(); |
|
3253 if (idx == noreg) { |
|
3254 __ std(G4, base, disp); |
|
3255 } else { |
|
3256 __ std(G4, base, idx); |
|
3257 } |
|
3258 } |
3233 } |
3259 } else if (src->is_address() && dest->is_register()) { |
3234 } else if (src->is_address() && dest->is_register()) { |
3260 null_check_offset = __ offset(); |
3235 null_check_offset = __ offset(); |
3261 if (VM_Version::v9_instructions_work()) { |
3236 if (idx == noreg) { |
3262 if (idx == noreg) { |
3237 __ ldx(base, disp, G5); |
3263 __ ldx(base, disp, G5); |
|
3264 } else { |
|
3265 __ ldx(base, idx, G5); |
|
3266 } |
|
3267 __ srax(G5, 32, dest->as_register_hi()); // fetch the high half into hi |
|
3268 __ mov (G5, dest->as_register_lo()); // copy low half into lo |
|
3269 } else { |
3238 } else { |
3270 if (idx == noreg) { |
3239 __ ldx(base, idx, G5); |
3271 __ ldd(base, disp, G4); |
3240 } |
3272 } else { |
3241 __ srax(G5, 32, dest->as_register_hi()); // fetch the high half into hi |
3273 __ ldd(base, idx, G4); |
3242 __ mov (G5, dest->as_register_lo()); // copy low half into lo |
3274 } |
|
3275 // G4 is high half, G5 is low half |
|
3276 __ mov (G4, dest->as_register_hi()); |
|
3277 __ mov (G5, dest->as_register_lo()); |
|
3278 } |
|
3279 } else { |
3243 } else { |
3280 Unimplemented(); |
3244 Unimplemented(); |
3281 } |
3245 } |
3282 if (info != NULL) { |
3246 if (info != NULL) { |
3283 add_debug_info_for_null_check(null_check_offset, info); |
3247 add_debug_info_for_null_check(null_check_offset, info); |