Mercurial > jdk8-mips64-public > hotspot / file comparison
comparison: src/cpu/sparc/vm/vm_version_sparc.cpp
src/cpu/sparc/vm/vm_version_sparc.cpp
- changeset 8729
- 402618d5afc9
- parent 8645
- a9bd2ebd8bcc
- child 8730
- 4b7ea2e3f901
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| 8728:8119c543f2af | 8729:402618d5afc9 |
|---|---|
| 257 (!has_hardware_fsmuld() ? ", no-fsmuld" : "")); | 257 (!has_hardware_fsmuld() ? ", no-fsmuld" : "")); |
| 258 | 258 |
| 259 // buf is started with ", " or is empty | 259 // buf is started with ", " or is empty |
| 260 _features_str = strdup(strlen(buf) > 2 ? buf + 2 : buf); | 260 _features_str = strdup(strlen(buf) > 2 ? buf + 2 : buf); |
| 261 | 261 |
| 262 // There are three 64-bit SPARC families that do not overlap, e.g., | |
| 263 // both is_ultra3() and is_sparc64() cannot be true at the same time. | |
| 264 // Within these families, there can be more than one chip, e.g., | |
| 265 // is_T4() and is_T7() machines are also is_niagara(). | |
| 266 if (is_ultra3()) { | |
| 267 assert(_L1_data_cache_line_size == 0, "overlap with Ultra3 family"); | |
| 268 // Ref: UltraSPARC III Cu Processor | |
| 269 _L1_data_cache_line_size = 64; | |
| 270 } | |
| 271 if (is_niagara()) { | |
| 272 assert(_L1_data_cache_line_size == 0, "overlap with niagara family"); | |
| 273 // All Niagara's are sun4v's, but not all sun4v's are Niagaras, e.g., | |
| 274 // Fujitsu SPARC64 is sun4v, but we don't want it in this block. | |
| 275 // | |
| 276 // Ref: UltraSPARC T1 Supplement to the UltraSPARC Architecture 2005 | |
| 277 // Appendix F.1.3.1 Cacheable Accesses | |
| 278 // -> 16-byte L1 cache line size | |
| 279 // | |
| 280 // Ref: UltraSPARC T2: A Highly-Threaded, Power-Efficient, SPARC SOC | |
| 281 // Section III: SPARC Processor Core | |
| 282 // -> 16-byte L1 cache line size | |
| 283 // | |
| 284 // Ref: Oracle's SPARC T4-1, SPARC T4-2, SPARC T4-4, and SPARC T4-1B Server Architecture | |
| 285 // Section SPARC T4 Processor Cache Architecture | |
| 286 // -> 32-byte L1 cache line size (no longer see that info on this ref) | |
| 287 // | |
| 288 // XXX - still need a T7 reference here | |
| 289 // | |
| 290 if (is_T7()) { // T7 or newer | |
| 291 _L1_data_cache_line_size = 64; | |
| 292 } else if (is_T4()) { // T4 or newer (until T7) | |
| 293 _L1_data_cache_line_size = 32; | |
| 294 } else { // T1 or newer (until T4) | |
| 295 _L1_data_cache_line_size = 16; | |
| 296 } | |
| 297 } | |
| 298 if (is_sparc64()) { | |
| 299 guarantee(_L1_data_cache_line_size == 0, "overlap with SPARC64 family"); | |
| 300 // Ref: Fujitsu SPARC64 VII Processor | |
| 301 // Section 4 Cache System | |
| 302 _L1_data_cache_line_size = 64; | |
| 303 } | |
| 304 | |
| 262 // UseVIS is set to the smallest of what hardware supports and what | 305 // UseVIS is set to the smallest of what hardware supports and what |
| 263 // the command line requires. I.e., you cannot set UseVIS to 3 on | 306 // the command line requires. I.e., you cannot set UseVIS to 3 on |
| 264 // older UltraSparc which do not support it. | 307 // older UltraSparc which do not support it. |
| 265 if (UseVIS > 3) UseVIS=3; | 308 if (UseVIS > 3) UseVIS=3; |
| 266 if (UseVIS < 0) UseVIS=0; | 309 if (UseVIS < 0) UseVIS=0; |
| 362 (cache_line_size > ContendedPaddingWidth)) | 405 (cache_line_size > ContendedPaddingWidth)) |
| 363 ContendedPaddingWidth = cache_line_size; | 406 ContendedPaddingWidth = cache_line_size; |
| 364 | 407 |
| 365 #ifndef PRODUCT | 408 #ifndef PRODUCT |
| 366 if (PrintMiscellaneous && Verbose) { | 409 if (PrintMiscellaneous && Verbose) { |
| 410 tty->print_cr("L1 data cache line size: %u", L1_data_cache_line_size()); | |
| 367 tty->print_cr("L2 data cache line size: %u", L2_data_cache_line_size()); | 411 tty->print_cr("L2 data cache line size: %u", L2_data_cache_line_size()); |
| 368 tty->print("Allocation"); | 412 tty->print("Allocation"); |
| 369 if (AllocatePrefetchStyle <= 0) { | 413 if (AllocatePrefetchStyle <= 0) { |
| 370 tty->print_cr(": no prefetching"); | 414 tty->print_cr(": no prefetching"); |
| 371 } else { | 415 } else { |
