Mercurial > jdk8-mips64-public > hotspot / file comparison
comparison: src/cpu/sparc/vm/sparc.ad
src/cpu/sparc/vm/sparc.ad
- changeset 8797
- 37ba410ffd43
- parent 8427
- c3d0bd36ab28
- child 8856
- ac27a9c85bea
- child 9333
- 2fccf735a116
equal
deleted
inserted
replaced
| 8796:b1f3fbe39975 | 8797:37ba410ffd43 |
|---|---|
| 3456 op_cost(0); | 3456 op_cost(0); |
| 3457 format %{ %} | 3457 format %{ %} |
| 3458 interface(CONST_INTER); | 3458 interface(CONST_INTER); |
| 3459 %} | 3459 %} |
| 3460 | 3460 |
| 3461 // Unsigned Long Immediate: 12-bit (non-negative that fits in simm13) | |
| 3462 operand immUL12() %{ | |
| 3463 predicate((0 <= n->get_long()) && (n->get_long() == (int)n->get_long()) && Assembler::is_simm13((int)n->get_long())); | |
| 3464 match(ConL); | |
| 3465 op_cost(0); | |
| 3466 | |
| 3467 format %{ %} | |
| 3468 interface(CONST_INTER); | |
| 3469 %} | |
| 3470 | |
| 3461 // Int Immediate non-negative | 3471 // Int Immediate non-negative |
| 3462 operand immU31() | 3472 operand immU31() |
| 3463 %{ | 3473 %{ |
| 3464 predicate(n->get_int() >= 0); | 3474 predicate(n->get_int() >= 0); |
| 3465 match(ConI); | 3475 match(ConI); |
| 4078 operand flagsRegL() %{ | 4088 operand flagsRegL() %{ |
| 4079 constraint(ALLOC_IN_RC(int_flags)); | 4089 constraint(ALLOC_IN_RC(int_flags)); |
| 4080 match(RegFlags); | 4090 match(RegFlags); |
| 4081 | 4091 |
| 4082 format %{ "xcc_L" %} | 4092 format %{ "xcc_L" %} |
| 4093 interface(REG_INTER); | |
| 4094 %} | |
| 4095 | |
| 4096 // Condition Code Register, unsigned long comparisons. | |
| 4097 operand flagsRegUL() %{ | |
| 4098 constraint(ALLOC_IN_RC(int_flags)); | |
| 4099 match(RegFlags); | |
| 4100 | |
| 4101 format %{ "xcc_UL" %} | |
| 4083 interface(REG_INTER); | 4102 interface(REG_INTER); |
| 4084 %} | 4103 %} |
| 4085 | 4104 |
| 4086 // Condition Code Register, floating comparisons, unordered same as "less". | 4105 // Condition Code Register, floating comparisons, unordered same as "less". |
| 4087 operand flagsRegF() %{ | 4106 operand flagsRegF() %{ |
| 8960 opcode(Assembler::subcc_op3, Assembler::arith_op); | 8979 opcode(Assembler::subcc_op3, Assembler::arith_op); |
| 8961 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | 8980 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); |
| 8962 ins_pipe(ialu_cconly_reg_reg); | 8981 ins_pipe(ialu_cconly_reg_reg); |
| 8963 %} | 8982 %} |
| 8964 | 8983 |
| 8984 instruct compUL_iReg(flagsRegUL xcc, iRegL op1, iRegL op2) %{ | |
| 8985 match(Set xcc (CmpUL op1 op2)); | |
| 8986 effect(DEF xcc, USE op1, USE op2); | |
| 8987 | |
| 8988 size(4); | |
| 8989 format %{ "CMP $op1,$op2\t! unsigned long" %} | |
| 8990 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 8991 ins_encode(form3_rs1_rs2_rd(op1, op2, R_G0)); | |
| 8992 ins_pipe(ialu_cconly_reg_reg); | |
| 8993 %} | |
| 8994 | |
| 8965 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{ | 8995 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{ |
| 8966 match(Set icc (CmpI op1 op2)); | 8996 match(Set icc (CmpI op1 op2)); |
| 8967 effect( DEF icc, USE op1 ); | 8997 effect( DEF icc, USE op1 ); |
| 8968 | 8998 |
| 8969 size(4); | 8999 size(4); |
| 9043 | 9073 |
| 9044 size(4); | 9074 size(4); |
| 9045 format %{ "CMP $op1,$op2\t! unsigned" %} | 9075 format %{ "CMP $op1,$op2\t! unsigned" %} |
| 9046 opcode(Assembler::subcc_op3, Assembler::arith_op); | 9076 opcode(Assembler::subcc_op3, Assembler::arith_op); |
| 9047 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | 9077 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); |
| 9078 ins_pipe(ialu_cconly_reg_imm); | |
| 9079 %} | |
| 9080 | |
| 9081 instruct compUL_iReg_imm13(flagsRegUL xcc, iRegL op1, immUL12 op2) %{ | |
| 9082 match(Set xcc (CmpUL op1 op2)); | |
| 9083 effect(DEF xcc, USE op1, USE op2); | |
| 9084 | |
| 9085 size(4); | |
| 9086 format %{ "CMP $op1,$op2\t! unsigned long" %} | |
| 9087 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 9088 ins_encode(form3_rs1_simm13_rd(op1, op2, R_G0)); | |
| 9048 ins_pipe(ialu_cconly_reg_imm); | 9089 ins_pipe(ialu_cconly_reg_imm); |
| 9049 %} | 9090 %} |
| 9050 | 9091 |
| 9051 // Compare Pointers | 9092 // Compare Pointers |
| 9052 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{ | 9093 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{ |
| 9419 __ delayed()->nop(); | 9460 __ delayed()->nop(); |
| 9420 %} | 9461 %} |
| 9421 ins_pipe(cmp_br_reg_imm); | 9462 ins_pipe(cmp_br_reg_imm); |
| 9422 %} | 9463 %} |
| 9423 | 9464 |
| 9465 instruct cmpUL_reg_branch(cmpOpU cmp, iRegL op1, iRegL op2, label labl, flagsRegUL xcc) %{ | |
| 9466 match(If cmp (CmpUL op1 op2)); | |
| 9467 effect(USE labl, KILL xcc); | |
| 9468 | |
| 9469 size(12); | |
| 9470 ins_cost(BRANCH_COST); | |
| 9471 format %{ "CMP $op1,$op2\t! unsigned long\n\t" | |
| 9472 "BP$cmp $labl" %} | |
| 9473 ins_encode %{ | |
| 9474 Label* L = $labl$$label; | |
| 9475 Assembler::Predict predict_taken = | |
| 9476 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
| 9477 __ cmp($op1$$Register, $op2$$Register); | |
| 9478 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); | |
| 9479 __ delayed()->nop(); | |
| 9480 %} | |
| 9481 ins_pipe(cmp_br_reg_reg); | |
| 9482 %} | |
| 9483 | |
| 9484 instruct cmpUL_imm_branch(cmpOpU cmp, iRegL op1, immL5 op2, label labl, flagsRegUL xcc) %{ | |
| 9485 match(If cmp (CmpUL op1 op2)); | |
| 9486 effect(USE labl, KILL xcc); | |
| 9487 | |
| 9488 size(12); | |
| 9489 ins_cost(BRANCH_COST); | |
| 9490 format %{ "CMP $op1,$op2\t! unsigned long\n\t" | |
| 9491 "BP$cmp $labl" %} | |
| 9492 ins_encode %{ | |
| 9493 Label* L = $labl$$label; | |
| 9494 Assembler::Predict predict_taken = | |
| 9495 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
| 9496 __ cmp($op1$$Register, $op2$$constant); | |
| 9497 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); | |
| 9498 __ delayed()->nop(); | |
| 9499 %} | |
| 9500 ins_pipe(cmp_br_reg_imm); | |
| 9501 %} | |
| 9502 | |
| 9424 instruct cmpL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{ | 9503 instruct cmpL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{ |
| 9425 match(If cmp (CmpL op1 op2)); | 9504 match(If cmp (CmpL op1 op2)); |
| 9426 effect(USE labl, KILL xcc); | 9505 effect(USE labl, KILL xcc); |
| 9427 | 9506 |
| 9428 size(12); | 9507 size(12); |
| 9641 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %} | 9720 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %} |
| 9642 ins_encode %{ | 9721 ins_encode %{ |
| 9643 Label* L = $labl$$label; | 9722 Label* L = $labl$$label; |
| 9644 assert(__ use_cbcond(*L), "back to back cbcond"); | 9723 assert(__ use_cbcond(*L), "back to back cbcond"); |
| 9645 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L); | 9724 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L); |
| 9725 %} | |
| 9726 ins_short_branch(1); | |
| 9727 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); | |
| 9728 ins_pipe(cbcond_reg_imm); | |
| 9729 %} | |
| 9730 | |
| 9731 instruct cmpUL_reg_branch_short(cmpOpU cmp, iRegL op1, iRegL op2, label labl, flagsRegUL xcc) %{ | |
| 9732 match(If cmp (CmpUL op1 op2)); | |
| 9733 predicate(UseCBCond); | |
| 9734 effect(USE labl, KILL xcc); | |
| 9735 | |
| 9736 size(4); | |
| 9737 ins_cost(BRANCH_COST); | |
| 9738 format %{ "CXB$cmp $op1,$op2,$labl\t! unsigned long" %} | |
| 9739 ins_encode %{ | |
| 9740 Label* L = $labl$$label; | |
| 9741 assert(__ use_cbcond(*L), "back to back cbcond"); | |
| 9742 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$Register, *L); | |
| 9743 %} | |
| 9744 ins_short_branch(1); | |
| 9745 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); | |
| 9746 ins_pipe(cbcond_reg_reg); | |
| 9747 %} | |
| 9748 | |
| 9749 instruct cmpUL_imm_branch_short(cmpOpU cmp, iRegL op1, immL5 op2, label labl, flagsRegUL xcc) %{ | |
| 9750 match(If cmp (CmpUL op1 op2)); | |
| 9751 predicate(UseCBCond); | |
| 9752 effect(USE labl, KILL xcc); | |
| 9753 | |
| 9754 size(4); | |
| 9755 ins_cost(BRANCH_COST); | |
| 9756 format %{ "CXB$cmp $op1,$op2,$labl\t! unsigned long" %} | |
| 9757 ins_encode %{ | |
| 9758 Label* L = $labl$$label; | |
| 9759 assert(__ use_cbcond(*L), "back to back cbcond"); | |
| 9760 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$constant, *L); | |
| 9646 %} | 9761 %} |
| 9647 ins_short_branch(1); | 9762 ins_short_branch(1); |
| 9648 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); | 9763 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); |
| 9649 ins_pipe(cbcond_reg_imm); | 9764 ins_pipe(cbcond_reg_imm); |
| 9650 %} | 9765 %} |
| 9879 Label* L = $labl$$label; | 9994 Label* L = $labl$$label; |
| 9880 Assembler::Predict predict_taken = | 9995 Assembler::Predict predict_taken = |
| 9881 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | 9996 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; |
| 9882 | 9997 |
| 9883 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); | 9998 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); |
| 9999 __ delayed()->nop(); | |
| 10000 %} | |
| 10001 ins_avoid_back_to_back(AVOID_BEFORE); | |
| 10002 ins_pipe(br_cc); | |
| 10003 %} | |
| 10004 | |
| 10005 instruct branchConU_long(cmpOpU cmp, flagsRegUL xcc, label labl) %{ | |
| 10006 match(If cmp xcc); | |
| 10007 effect(USE labl); | |
| 10008 | |
| 10009 size(8); | |
| 10010 ins_cost(BRANCH_COST); | |
| 10011 format %{ "BP$cmp $xcc,$labl" %} | |
| 10012 ins_encode %{ | |
| 10013 Label* L = $labl$$label; | |
| 10014 Assembler::Predict predict_taken = | |
| 10015 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
| 10016 | |
| 10017 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); | |
| 9884 __ delayed()->nop(); | 10018 __ delayed()->nop(); |
| 9885 %} | 10019 %} |
| 9886 ins_avoid_back_to_back(AVOID_BEFORE); | 10020 ins_avoid_back_to_back(AVOID_BEFORE); |
| 9887 ins_pipe(br_cc); | 10021 ins_pipe(br_cc); |
| 9888 %} | 10022 %} |
