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comparison: src/cpu/mips/vm/register_mips.hpp

src/cpu/mips/vm/register_mips.hpp

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1 /*
2 * Copyright (c) 2000, 2012, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2015, 2016, Loongson Technology. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_MIPS_VM_REGISTER_MIPS_HPP
27 #define CPU_MIPS_VM_REGISTER_MIPS_HPP
28
29 #include "asm/register.hpp"
30 #include "vm_version_mips.hpp"
31
32 class VMRegImpl;
33 typedef VMRegImpl* VMReg;
34
35 // Use Register as shortcut
36 class RegisterImpl;
37 typedef RegisterImpl* Register;
38
39
40 // The implementation of integer registers for the ia32 architecture
41 inline Register as_Register(int encoding) {
42 return (Register)(intptr_t) encoding;
43 }
44
45 class RegisterImpl: public AbstractRegisterImpl {
46 public:
47 enum {
48 number_of_registers = 32
49 };
50
51 // derived registers, offsets, and addresses
52 Register successor() const { return as_Register(encoding() + 1); }
53
54 // construction
55 inline friend Register as_Register(int encoding);
56
57 VMReg as_VMReg();
58
59 // accessors
60 int encoding() const { assert(is_valid(),err_msg( "invalid register (%d)", (int)(intptr_t)this)); return (intptr_t)this; }
61 bool is_valid() const { return 0 <= (intptr_t)this && (intptr_t)this < number_of_registers; }
62 const char* name() const;
63 };
64
65
66 // The integer registers of the MIPS32 architecture
67 CONSTANT_REGISTER_DECLARATION(Register, noreg, (-1));
68
69
70 CONSTANT_REGISTER_DECLARATION(Register, i0, (0));
71 CONSTANT_REGISTER_DECLARATION(Register, i1, (1));
72 CONSTANT_REGISTER_DECLARATION(Register, i2, (2));
73 CONSTANT_REGISTER_DECLARATION(Register, i3, (3));
74 CONSTANT_REGISTER_DECLARATION(Register, i4, (4));
75 CONSTANT_REGISTER_DECLARATION(Register, i5, (5));
76 CONSTANT_REGISTER_DECLARATION(Register, i6, (6));
77 CONSTANT_REGISTER_DECLARATION(Register, i7, (7));
78 CONSTANT_REGISTER_DECLARATION(Register, i8, (8));
79 CONSTANT_REGISTER_DECLARATION(Register, i9, (9));
80 CONSTANT_REGISTER_DECLARATION(Register, i10, (10));
81 CONSTANT_REGISTER_DECLARATION(Register, i11, (11));
82 CONSTANT_REGISTER_DECLARATION(Register, i12, (12));
83 CONSTANT_REGISTER_DECLARATION(Register, i13, (13));
84 CONSTANT_REGISTER_DECLARATION(Register, i14, (14));
85 CONSTANT_REGISTER_DECLARATION(Register, i15, (15));
86 CONSTANT_REGISTER_DECLARATION(Register, i16, (16));
87 CONSTANT_REGISTER_DECLARATION(Register, i17, (17));
88 CONSTANT_REGISTER_DECLARATION(Register, i18, (18));
89 CONSTANT_REGISTER_DECLARATION(Register, i19, (19));
90 CONSTANT_REGISTER_DECLARATION(Register, i20, (20));
91 CONSTANT_REGISTER_DECLARATION(Register, i21, (21));
92 CONSTANT_REGISTER_DECLARATION(Register, i22, (22));
93 CONSTANT_REGISTER_DECLARATION(Register, i23, (23));
94 CONSTANT_REGISTER_DECLARATION(Register, i24, (24));
95 CONSTANT_REGISTER_DECLARATION(Register, i25, (25));
96 CONSTANT_REGISTER_DECLARATION(Register, i26, (26));
97 CONSTANT_REGISTER_DECLARATION(Register, i27, (27));
98 CONSTANT_REGISTER_DECLARATION(Register, i28, (28));
99 CONSTANT_REGISTER_DECLARATION(Register, i29, (29));
100 CONSTANT_REGISTER_DECLARATION(Register, i30, (30));
101 CONSTANT_REGISTER_DECLARATION(Register, i31, (31));
102
103 //o32 convention registers
104 /*CONSTANT_REGISTER_DECLARATION(Register, zero , ( 0));
105 CONSTANT_REGISTER_DECLARATION(Register, at , ( 1));
106 CONSTANT_REGISTER_DECLARATION(Register, v0 , ( 2));
107 CONSTANT_REGISTER_DECLARATION(Register, v1 , ( 3));
108 CONSTANT_REGISTER_DECLARATION(Register, a0 , ( 4));
109 CONSTANT_REGISTER_DECLARATION(Register, a1 , ( 5));
110 CONSTANT_REGISTER_DECLARATION(Register, a2 , ( 6));
111 CONSTANT_REGISTER_DECLARATION(Register, a3 , ( 7));
112 CONSTANT_REGISTER_DECLARATION(Register, t0 , ( 8));
113 CONSTANT_REGISTER_DECLARATION(Register, t1 , ( 9));
114 CONSTANT_REGISTER_DECLARATION(Register, t2 , ( 10));
115 CONSTANT_REGISTER_DECLARATION(Register, t3 , ( 11));
116 CONSTANT_REGISTER_DECLARATION(Register, t4 , ( 12));
117 CONSTANT_REGISTER_DECLARATION(Register, t5 , ( 13));
118 CONSTANT_REGISTER_DECLARATION(Register, t6 , ( 14));
119 CONSTANT_REGISTER_DECLARATION(Register, t7 , ( 15));
120 CONSTANT_REGISTER_DECLARATION(Register, s0 , ( 16));
121 CONSTANT_REGISTER_DECLARATION(Register, s1 , ( 17));
122 CONSTANT_REGISTER_DECLARATION(Register, s2 , ( 18));
123 CONSTANT_REGISTER_DECLARATION(Register, s3 , ( 19));
124 CONSTANT_REGISTER_DECLARATION(Register, s4 , ( 20));
125 CONSTANT_REGISTER_DECLARATION(Register, s5 , ( 21));
126 CONSTANT_REGISTER_DECLARATION(Register, s6 , ( 22));
127 CONSTANT_REGISTER_DECLARATION(Register, s7 , ( 23));
128 CONSTANT_REGISTER_DECLARATION(Register, t8 , ( 24));
129 CONSTANT_REGISTER_DECLARATION(Register, t9 , ( 25));
130 CONSTANT_REGISTER_DECLARATION(Register, k0 , ( 26));
131 CONSTANT_REGISTER_DECLARATION(Register, k1 , ( 27));
132 CONSTANT_REGISTER_DECLARATION(Register, gp , ( 28));
133 CONSTANT_REGISTER_DECLARATION(Register, sp , ( 29));
134 CONSTANT_REGISTER_DECLARATION(Register, fp , ( 30));
135 CONSTANT_REGISTER_DECLARATION(Register, s8 , ( 30));
136 CONSTANT_REGISTER_DECLARATION(Register, ra , ( 31));*/
137
138 #ifndef DONT_USE_REGISTER_DEFINES
139 #define NOREG ((Register)(noreg_RegisterEnumValue))
140
141 #define I0 ((Register)(i0_RegisterEnumValue))
142 #define I1 ((Register)(i1_RegisterEnumValue))
143 #define I2 ((Register)(i2_RegisterEnumValue))
144 #define I3 ((Register)(i3_RegisterEnumValue))
145 #define I4 ((Register)(i4_RegisterEnumValue))
146 #define I5 ((Register)(i5_RegisterEnumValue))
147 #define I6 ((Register)(i6_RegisterEnumValue))
148 #define I7 ((Register)(i7_RegisterEnumValue))
149 #define I8 ((Register)(i8_RegisterEnumValue))
150 #define I9 ((Register)(i9_RegisterEnumValue))
151 #define I10 ((Register)(i10_RegisterEnumValue))
152 #define I11 ((Register)(i11_RegisterEnumValue))
153 #define I12 ((Register)(i12_RegisterEnumValue))
154 #define I13 ((Register)(i13_RegisterEnumValue))
155 #define I14 ((Register)(i14_RegisterEnumValue))
156 #define I15 ((Register)(i15_RegisterEnumValue))
157 #define I16 ((Register)(i16_RegisterEnumValue))
158 #define I17 ((Register)(i17_RegisterEnumValue))
159 #define I18 ((Register)(i18_RegisterEnumValue))
160 #define I19 ((Register)(i19_RegisterEnumValue))
161 #define I20 ((Register)(i20_RegisterEnumValue))
162 #define I21 ((Register)(i21_RegisterEnumValue))
163 #define I22 ((Register)(i22_RegisterEnumValue))
164 #define I23 ((Register)(i23_RegisterEnumValue))
165 #define I24 ((Register)(i24_RegisterEnumValue))
166 #define I25 ((Register)(i25_RegisterEnumValue))
167 #define I26 ((Register)(i26_RegisterEnumValue))
168 #define I27 ((Register)(i27_RegisterEnumValue))
169 #define I28 ((Register)(i28_RegisterEnumValue))
170 #define I29 ((Register)(i29_RegisterEnumValue))
171 #define I30 ((Register)(i30_RegisterEnumValue))
172 #define I31 ((Register)(i31_RegisterEnumValue))
173
174 #ifndef _LP64
175
176 #define R0 ((Register)(i0_RegisterEnumValue))
177 #define AT ((Register)(i1_RegisterEnumValue))
178 #define V0 ((Register)(i2_RegisterEnumValue))
179 #define V1 ((Register)(i3_RegisterEnumValue))
180 #define A0 ((Register)(i4_RegisterEnumValue))
181 #define A1 ((Register)(i5_RegisterEnumValue))
182 #define A2 ((Register)(i6_RegisterEnumValue))
183 #define A3 ((Register)(i7_RegisterEnumValue))
184 #define T0 ((Register)(i8_RegisterEnumValue))
185 #define T1 ((Register)(i9_RegisterEnumValue))
186 #define T2 ((Register)(i10_RegisterEnumValue))
187 #define T3 ((Register)(i11_RegisterEnumValue))
188 #define T4 ((Register)(i12_RegisterEnumValue))
189 #define T5 ((Register)(i13_RegisterEnumValue))
190 #define T6 ((Register)(i14_RegisterEnumValue))
191 #define T7 ((Register)(i15_RegisterEnumValue))
192 #define S0 ((Register)(i16_RegisterEnumValue))
193 #define S1 ((Register)(i17_RegisterEnumValue))
194 #define S2 ((Register)(i18_RegisterEnumValue))
195 #define S3 ((Register)(i19_RegisterEnumValue))
196 #define S4 ((Register)(i20_RegisterEnumValue))
197 #define S5 ((Register)(i21_RegisterEnumValue))
198 #define S6 ((Register)(i22_RegisterEnumValue))
199 #define S7 ((Register)(i23_RegisterEnumValue))
200 #define T8 ((Register)(i24_RegisterEnumValue))
201 #define T9 ((Register)(i25_RegisterEnumValue))
202 #define K0 ((Register)(i26_RegisterEnumValue))
203 #define K1 ((Register)(i27_RegisterEnumValue))
204 #define GP ((Register)(i28_RegisterEnumValue))
205 #define SP ((Register)(i29_RegisterEnumValue))
206 #define FP ((Register)(i30_RegisterEnumValue))
207 #define S8 ((Register)(i30_RegisterEnumValue))
208 #define RA ((Register)(i31_RegisterEnumValue))
209
210 #else
211
212 #define R0 ((Register)(i0_RegisterEnumValue))
213 #define AT ((Register)(i1_RegisterEnumValue))
214 #define V0 ((Register)(i2_RegisterEnumValue))
215 #define V1 ((Register)(i3_RegisterEnumValue))
216 #define A0 ((Register)(i4_RegisterEnumValue))
217 #define A1 ((Register)(i5_RegisterEnumValue))
218 #define A2 ((Register)(i6_RegisterEnumValue))
219 #define A3 ((Register)(i7_RegisterEnumValue))
220 #define A4 ((Register)(i8_RegisterEnumValue))
221 #define A5 ((Register)(i9_RegisterEnumValue))
222 #define A6 ((Register)(i10_RegisterEnumValue))
223 #define A7 ((Register)(i11_RegisterEnumValue))
224 #define T0 ((Register)(i12_RegisterEnumValue))
225 #define T1 ((Register)(i13_RegisterEnumValue))
226 #define T2 ((Register)(i14_RegisterEnumValue))
227 #define T3 ((Register)(i15_RegisterEnumValue))
228 #define S0 ((Register)(i16_RegisterEnumValue))
229 #define S1 ((Register)(i17_RegisterEnumValue))
230 #define S2 ((Register)(i18_RegisterEnumValue))
231 #define S3 ((Register)(i19_RegisterEnumValue))
232 #define S4 ((Register)(i20_RegisterEnumValue))
233 #define S5 ((Register)(i21_RegisterEnumValue))
234 #define S6 ((Register)(i22_RegisterEnumValue))
235 #define S7 ((Register)(i23_RegisterEnumValue))
236 #define T8 ((Register)(i24_RegisterEnumValue))
237 #define T9 ((Register)(i25_RegisterEnumValue))
238 #define K0 ((Register)(i26_RegisterEnumValue))
239 #define K1 ((Register)(i27_RegisterEnumValue))
240 #define GP ((Register)(i28_RegisterEnumValue))
241 #define SP ((Register)(i29_RegisterEnumValue))
242 #define FP ((Register)(i30_RegisterEnumValue))
243 #define S8 ((Register)(i30_RegisterEnumValue))
244 #define RA ((Register)(i31_RegisterEnumValue))
245 /*
246 #define TA0 ((Register)(i8_RegisterEnumValue))
247 #define TA1 ((Register)(i9_RegisterEnumValue))
248 #define TA2 ((Register)(i10_RegisterEnumValue))
249 #define TA3 ((Register)(i11_RegisterEnumValue))
250 #define T4 ((Register)(i12_RegisterEnumValue))
251 #define T5 ((Register)(i13_RegisterEnumValue))
252 #define T6 ((Register)(i14_RegisterEnumValue))
253 #define T7 ((Register)(i15_RegisterEnumValue))
254 */
255 #define c_rarg0 T0
256 #define c_rarg1 T1
257 #define Rmethod S3
258 #define Rsender S4
259 #define Rnext S1
260
261 #define RT0 T0
262 #define RT1 T1
263 #define RT2 T2
264 #define RT3 T3
265 #define RT4 T8
266 #define RT5 T9
267 #endif //_LP64
268
269
270 //for interpreter frame
271 // bytecode pointer register
272 #define BCP S0
273 // local variable pointer register
274 #define LVP S7
275 // temperary callee saved register, we use this register to save the register maybe blowed cross call_VM
276 // be sure to save and restore its value in call_stub
277 #define TSR S2
278
279 /* 2013/7/10 Jin: OPT_SAFEPOINT not supported yet */
280 #define OPT_SAFEPOINT 1
281
282 #define OPT_THREAD 1
283
284 #define TREG S6
285
286 #define S5_heapbase S5
287
288 #define mh_SP_save SP
289
290 #define FSR V0
291 #define SSR V1
292 #define FSF F0
293 #define SSF F1
294 #define FTF F14
295 #define STF F15
296
297 #define AFT F30
298
299 #define RECEIVER T0
300 #define IC_Klass T1
301
302 #define SHIFT_count T3
303
304 #endif // DONT_USE_REGISTER_DEFINES
305
306 // Use FloatRegister as shortcut
307 class FloatRegisterImpl;
308 typedef FloatRegisterImpl* FloatRegister;
309
310 inline FloatRegister as_FloatRegister(int encoding) {
311 return (FloatRegister)(intptr_t) encoding;
312 }
313
314 // The implementation of floating point registers for the ia32 architecture
315 class FloatRegisterImpl: public AbstractRegisterImpl {
316 public:
317 enum {
318 float_arg_base = 12,
319 number_of_registers = 32
320 };
321
322 // construction
323 inline friend FloatRegister as_FloatRegister(int encoding);
324
325 VMReg as_VMReg();
326
327 // derived registers, offsets, and addresses
328 FloatRegister successor() const { return as_FloatRegister(encoding() + 1); }
329
330 // accessors
331 int encoding() const { assert(is_valid(), "invalid register"); return (intptr_t)this; }
332 bool is_valid() const { return 0 <= (intptr_t)this && (intptr_t)this < number_of_registers; }
333 const char* name() const;
334
335 };
336
337 CONSTANT_REGISTER_DECLARATION(FloatRegister, fnoreg , (-1));
338
339 CONSTANT_REGISTER_DECLARATION(FloatRegister, f0 , ( 0));
340 CONSTANT_REGISTER_DECLARATION(FloatRegister, f1 , ( 1));
341 CONSTANT_REGISTER_DECLARATION(FloatRegister, f2 , ( 2));
342 CONSTANT_REGISTER_DECLARATION(FloatRegister, f3 , ( 3));
343 CONSTANT_REGISTER_DECLARATION(FloatRegister, f4 , ( 4));
344 CONSTANT_REGISTER_DECLARATION(FloatRegister, f5 , ( 5));
345 CONSTANT_REGISTER_DECLARATION(FloatRegister, f6 , ( 6));
346 CONSTANT_REGISTER_DECLARATION(FloatRegister, f7 , ( 7));
347 CONSTANT_REGISTER_DECLARATION(FloatRegister, f8 , ( 8));
348 CONSTANT_REGISTER_DECLARATION(FloatRegister, f9 , ( 9));
349 CONSTANT_REGISTER_DECLARATION(FloatRegister, f10 , (10));
350 CONSTANT_REGISTER_DECLARATION(FloatRegister, f11 , (11));
351 CONSTANT_REGISTER_DECLARATION(FloatRegister, f12 , (12));
352 CONSTANT_REGISTER_DECLARATION(FloatRegister, f13 , (13));
353 CONSTANT_REGISTER_DECLARATION(FloatRegister, f14 , (14));
354 CONSTANT_REGISTER_DECLARATION(FloatRegister, f15 , (15));
355 CONSTANT_REGISTER_DECLARATION(FloatRegister, f16 , (16));
356 CONSTANT_REGISTER_DECLARATION(FloatRegister, f17 , (17));
357 CONSTANT_REGISTER_DECLARATION(FloatRegister, f18 , (18));
358 CONSTANT_REGISTER_DECLARATION(FloatRegister, f19 , (19));
359 CONSTANT_REGISTER_DECLARATION(FloatRegister, f20 , (20));
360 CONSTANT_REGISTER_DECLARATION(FloatRegister, f21 , (21));
361 CONSTANT_REGISTER_DECLARATION(FloatRegister, f22 , (22));
362 CONSTANT_REGISTER_DECLARATION(FloatRegister, f23 , (23));
363 CONSTANT_REGISTER_DECLARATION(FloatRegister, f24 , (24));
364 CONSTANT_REGISTER_DECLARATION(FloatRegister, f25 , (25));
365 CONSTANT_REGISTER_DECLARATION(FloatRegister, f26 , (26));
366 CONSTANT_REGISTER_DECLARATION(FloatRegister, f27 , (27));
367 CONSTANT_REGISTER_DECLARATION(FloatRegister, f28 , (28));
368 CONSTANT_REGISTER_DECLARATION(FloatRegister, f29 , (29));
369 CONSTANT_REGISTER_DECLARATION(FloatRegister, f30 , (30));
370 CONSTANT_REGISTER_DECLARATION(FloatRegister, f31 , (31));
371
372 #ifndef DONT_USE_REGISTER_DEFINES
373 #define FNOREG ((FloatRegister)(fnoreg_FloatRegisterEnumValue))
374 #define F0 ((FloatRegister)( f0_FloatRegisterEnumValue))
375 #define F1 ((FloatRegister)( f1_FloatRegisterEnumValue))
376 #define F2 ((FloatRegister)( f2_FloatRegisterEnumValue))
377 #define F3 ((FloatRegister)( f3_FloatRegisterEnumValue))
378 #define F4 ((FloatRegister)( f4_FloatRegisterEnumValue))
379 #define F5 ((FloatRegister)( f5_FloatRegisterEnumValue))
380 #define F6 ((FloatRegister)( f6_FloatRegisterEnumValue))
381 #define F7 ((FloatRegister)( f7_FloatRegisterEnumValue))
382 #define F8 ((FloatRegister)( f8_FloatRegisterEnumValue))
383 #define F9 ((FloatRegister)( f9_FloatRegisterEnumValue))
384 #define F10 ((FloatRegister)( f10_FloatRegisterEnumValue))
385 #define F11 ((FloatRegister)( f11_FloatRegisterEnumValue))
386 #define F12 ((FloatRegister)( f12_FloatRegisterEnumValue))
387 #define F13 ((FloatRegister)( f13_FloatRegisterEnumValue))
388 #define F14 ((FloatRegister)( f14_FloatRegisterEnumValue))
389 #define F15 ((FloatRegister)( f15_FloatRegisterEnumValue))
390 #define F16 ((FloatRegister)( f16_FloatRegisterEnumValue))
391 #define F17 ((FloatRegister)( f17_FloatRegisterEnumValue))
392 #define F18 ((FloatRegister)( f18_FloatRegisterEnumValue))
393 #define F19 ((FloatRegister)( f19_FloatRegisterEnumValue))
394 #define F20 ((FloatRegister)( f20_FloatRegisterEnumValue))
395 #define F21 ((FloatRegister)( f21_FloatRegisterEnumValue))
396 #define F22 ((FloatRegister)( f22_FloatRegisterEnumValue))
397 #define F23 ((FloatRegister)( f23_FloatRegisterEnumValue))
398 #define F24 ((FloatRegister)( f24_FloatRegisterEnumValue))
399 #define F25 ((FloatRegister)( f25_FloatRegisterEnumValue))
400 #define F26 ((FloatRegister)( f26_FloatRegisterEnumValue))
401 #define F27 ((FloatRegister)( f27_FloatRegisterEnumValue))
402 #define F28 ((FloatRegister)( f28_FloatRegisterEnumValue))
403 #define F29 ((FloatRegister)( f29_FloatRegisterEnumValue))
404 #define F30 ((FloatRegister)( f30_FloatRegisterEnumValue))
405 #define F31 ((FloatRegister)( f31_FloatRegisterEnumValue))
406 #endif // DONT_USE_REGISTER_DEFINES
407
408
409 const int MIPS_ARGS_IN_REGS_NUM = 4;
410
411 // Need to know the total number of registers of all sorts for SharedInfo.
412 // Define a class that exports it.
413 class ConcreteRegisterImpl : public AbstractRegisterImpl {
414 public:
415 enum {
416 // A big enough number for C2: all the registers plus flags
417 // This number must be large enough to cover REG_COUNT (defined by c2) registers.
418 // There is no requirement that any ordering here matches any ordering c2 gives
419 // it's optoregs.
420 number_of_registers = (RegisterImpl::number_of_registers + FloatRegisterImpl::number_of_registers)
421 LP64_ONLY( * 2)
422 };
423
424 static const int max_gpr;
425 static const int max_fpr;
426
427
428 };
429 #endif //CPU_MIPS_VM_REGISTER_MIPS_HPP

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