3738 scale($scale); |
3738 scale($scale); |
3739 disp($off); |
3739 disp($off); |
3740 %} |
3740 %} |
3741 %} |
3741 %} |
3742 |
3742 |
|
3743 // Indirect Memory Plus Positive Index Register Plus Offset Operand |
|
3744 operand indPosIndexOffset(any_RegP reg, immL32 off, rRegI idx) |
|
3745 %{ |
|
3746 constraint(ALLOC_IN_RC(ptr_reg)); |
|
3747 predicate(n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0); |
|
3748 match(AddP (AddP reg (ConvI2L idx)) off); |
|
3749 |
|
3750 op_cost(10); |
|
3751 format %{"[$reg + $off + $idx]" %} |
|
3752 interface(MEMORY_INTER) %{ |
|
3753 base($reg); |
|
3754 index($idx); |
|
3755 scale(0x0); |
|
3756 disp($off); |
|
3757 %} |
|
3758 %} |
|
3759 |
3743 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand |
3760 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand |
3744 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale) |
3761 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale) |
3745 %{ |
3762 %{ |
3746 constraint(ALLOC_IN_RC(ptr_reg)); |
3763 constraint(ALLOC_IN_RC(ptr_reg)); |
3747 predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0); |
3764 predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0); |
3885 format %{"[$reg + $off + $lreg << $scale]" %} |
3902 format %{"[$reg + $off + $lreg << $scale]" %} |
3886 interface(MEMORY_INTER) %{ |
3903 interface(MEMORY_INTER) %{ |
3887 base($reg); |
3904 base($reg); |
3888 index($lreg); |
3905 index($lreg); |
3889 scale($scale); |
3906 scale($scale); |
|
3907 disp($off); |
|
3908 %} |
|
3909 %} |
|
3910 |
|
3911 // Indirect Memory Times Plus Positive Index Register Plus Offset Operand |
|
3912 operand indPosIndexOffsetNarrow(rRegN reg, immL32 off, rRegI idx) |
|
3913 %{ |
|
3914 constraint(ALLOC_IN_RC(ptr_reg)); |
|
3915 predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0); |
|
3916 match(AddP (AddP (DecodeN reg) (ConvI2L idx)) off); |
|
3917 |
|
3918 op_cost(10); |
|
3919 format %{"[$reg + $off + $idx]" %} |
|
3920 interface(MEMORY_INTER) %{ |
|
3921 base($reg); |
|
3922 index($idx); |
|
3923 scale(0x0); |
3890 disp($off); |
3924 disp($off); |
3891 %} |
3925 %} |
3892 %} |
3926 %} |
3893 |
3927 |
3894 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand |
3928 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand |
4080 // instructions for every form of operand when the instruction accepts |
4114 // instructions for every form of operand when the instruction accepts |
4081 // multiple operand types with the same basic encoding and format. The classic |
4115 // multiple operand types with the same basic encoding and format. The classic |
4082 // case of this is memory operands. |
4116 // case of this is memory operands. |
4083 |
4117 |
4084 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex, |
4118 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex, |
4085 indIndexScale, indIndexScaleOffset, indPosIndexScaleOffset, |
4119 indIndexScale, indIndexScaleOffset, indPosIndexOffset, indPosIndexScaleOffset, |
4086 indCompressedOopOffset, |
4120 indCompressedOopOffset, |
4087 indirectNarrow, indOffset8Narrow, indOffset32Narrow, |
4121 indirectNarrow, indOffset8Narrow, indOffset32Narrow, |
4088 indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow, |
4122 indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow, |
4089 indIndexScaleOffsetNarrow, indPosIndexScaleOffsetNarrow); |
4123 indIndexScaleOffsetNarrow, indPosIndexOffsetNarrow, indPosIndexScaleOffsetNarrow); |
4090 |
4124 |
4091 //----------PIPELINE----------------------------------------------------------- |
4125 //----------PIPELINE----------------------------------------------------------- |
4092 // Rules which define the behavior of the target architectures pipeline. |
4126 // Rules which define the behavior of the target architectures pipeline. |
4093 pipeline %{ |
4127 pipeline %{ |
4094 |
4128 |
5118 opcode(0x8D); |
5152 opcode(0x8D); |
5119 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
5153 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
5120 ins_pipe(ialu_reg_reg_fat); |
5154 ins_pipe(ialu_reg_reg_fat); |
5121 %} |
5155 %} |
5122 |
5156 |
|
5157 instruct leaPPosIdxOff(rRegP dst, indPosIndexOffset mem) |
|
5158 %{ |
|
5159 match(Set dst mem); |
|
5160 |
|
5161 ins_cost(110); |
|
5162 format %{ "leaq $dst, $mem\t# ptr posidxoff" %} |
|
5163 opcode(0x8D); |
|
5164 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
5165 ins_pipe(ialu_reg_reg_fat); |
|
5166 %} |
|
5167 |
5123 instruct leaPPosIdxScaleOff(rRegP dst, indPosIndexScaleOffset mem) |
5168 instruct leaPPosIdxScaleOff(rRegP dst, indPosIndexScaleOffset mem) |
5124 %{ |
5169 %{ |
5125 match(Set dst mem); |
5170 match(Set dst mem); |
5126 |
5171 |
5127 ins_cost(110); |
5172 ins_cost(110); |
5197 predicate(Universe::narrow_oop_shift() == 0); |
5242 predicate(Universe::narrow_oop_shift() == 0); |
5198 match(Set dst mem); |
5243 match(Set dst mem); |
5199 |
5244 |
5200 ins_cost(110); |
5245 ins_cost(110); |
5201 format %{ "leaq $dst, $mem\t# ptr idxscaleoffnarrow" %} |
5246 format %{ "leaq $dst, $mem\t# ptr idxscaleoffnarrow" %} |
|
5247 opcode(0x8D); |
|
5248 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
5249 ins_pipe(ialu_reg_reg_fat); |
|
5250 %} |
|
5251 |
|
5252 instruct leaPPosIdxOffNarrow(rRegP dst, indPosIndexOffsetNarrow mem) |
|
5253 %{ |
|
5254 predicate(Universe::narrow_oop_shift() == 0); |
|
5255 match(Set dst mem); |
|
5256 |
|
5257 ins_cost(110); |
|
5258 format %{ "leaq $dst, $mem\t# ptr posidxoffnarrow" %} |
5202 opcode(0x8D); |
5259 opcode(0x8D); |
5203 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
5260 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
5204 ins_pipe(ialu_reg_reg_fat); |
5261 ins_pipe(ialu_reg_reg_fat); |
5205 %} |
5262 %} |
5206 |
5263 |