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src/cpu/sparc/vm/assembler_sparc.hpp@f8c9417e3571 (annotated)

src/cpu/sparc/vm/assembler_sparc.hpp

Tue, 14 Jun 2011 14:41:33 -0700

author

never

date

Tue, 14 Jun 2011 14:41:33 -0700

changeset 2954

f8c9417e3571

parent 2950

cba7b5c2d53f

child 3001

faa472957b38

permissions

-rw-r--r--

7052219: JSR 292: Crash in ~BufferBlob::MethodHandles adapters
Reviewed-by: twisti, kvn, jrose

duke@435	1	/*
phh@2423	2	* Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved.
duke@435	3	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
duke@435	4	*
duke@435	5	* This code is free software; you can redistribute it and/or modify it
duke@435	6	* under the terms of the GNU General Public License version 2 only, as
duke@435	7	* published by the Free Software Foundation.
duke@435	8	*
duke@435	9	* This code is distributed in the hope that it will be useful, but WITHOUT
duke@435	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
duke@435	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
duke@435	12	* version 2 for more details (a copy is included in the LICENSE file that
duke@435	13	* accompanied this code).
duke@435	14	*
duke@435	15	* You should have received a copy of the GNU General Public License version
duke@435	16	* 2 along with this work; if not, write to the Free Software Foundation,
duke@435	17	* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
duke@435	18	*
trims@1907	19	* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
trims@1907	20	* or visit www.oracle.com if you need additional information or have any
trims@1907	21	* questions.
duke@435	22	*
duke@435	23	*/
duke@435	24
stefank@2314	25	#ifndef CPU_SPARC_VM_ASSEMBLER_SPARC_HPP
stefank@2314	26	#define CPU_SPARC_VM_ASSEMBLER_SPARC_HPP
stefank@2314	27
duke@435	28	class BiasedLockingCounters;
duke@435	29
duke@435	30	// <sys/trap.h> promises that the system will not use traps 16-31
duke@435	31	#define ST_RESERVED_FOR_USER_0 0x10
duke@435	32
duke@435	33	/* Written: David Ungar 4/19/97 */
duke@435	34
duke@435	35	// Contains all the definitions needed for sparc assembly code generation.
duke@435	36
duke@435	37	// Register aliases for parts of the system:
duke@435	38
duke@435	39	// 64 bit values can be kept in g1-g5, o1-o5 and o7 and all 64 bits are safe
duke@435	40	// across context switches in V8+ ABI. Of course, there are no 64 bit regs
duke@435	41	// in V8 ABI. All 64 bits are preserved in V9 ABI for all registers.
duke@435	42
duke@435	43	// g2-g4 are scratch registers called "application globals". Their
duke@435	44	// meaning is reserved to the "compilation system"--which means us!
duke@435	45	// They are are not supposed to be touched by ordinary C code, although
duke@435	46	// highly-optimized C code might steal them for temps. They are safe
duke@435	47	// across thread switches, and the ABI requires that they be safe
duke@435	48	// across function calls.
duke@435	49	//
duke@435	50	// g1 and g3 are touched by more modules. V8 allows g1 to be clobbered
duke@435	51	// across func calls, and V8+ also allows g5 to be clobbered across
duke@435	52	// func calls. Also, g1 and g5 can get touched while doing shared
duke@435	53	// library loading.
duke@435	54	//
duke@435	55	// We must not touch g7 (it is the thread-self register) and g6 is
duke@435	56	// reserved for certain tools. g0, of course, is always zero.
duke@435	57	//
duke@435	58	// (Sources: SunSoft Compilers Group, thread library engineers.)
duke@435	59
duke@435	60	// %%%% The interpreter should be revisited to reduce global scratch regs.
duke@435	61
duke@435	62	// This global always holds the current JavaThread pointer:
duke@435	63
duke@435	64	REGISTER_DECLARATION(Register, G2_thread , G2);
coleenp@548	65	REGISTER_DECLARATION(Register, G6_heapbase , G6);
duke@435	66
duke@435	67	// The following globals are part of the Java calling convention:
duke@435	68
duke@435	69	REGISTER_DECLARATION(Register, G5_method , G5);
duke@435	70	REGISTER_DECLARATION(Register, G5_megamorphic_method , G5_method);
duke@435	71	REGISTER_DECLARATION(Register, G5_inline_cache_reg , G5_method);
duke@435	72
duke@435	73	// The following globals are used for the new C1 & interpreter calling convention:
duke@435	74	REGISTER_DECLARATION(Register, Gargs , G4); // pointing to the last argument
duke@435	75
duke@435	76	// This local is used to preserve G2_thread in the interpreter and in stubs:
duke@435	77	REGISTER_DECLARATION(Register, L7_thread_cache , L7);
duke@435	78
duke@435	79	// These globals are used as scratch registers in the interpreter:
duke@435	80
duke@435	81	REGISTER_DECLARATION(Register, Gframe_size , G1); // SAME REG as G1_scratch
duke@435	82	REGISTER_DECLARATION(Register, G1_scratch , G1); // also SAME
duke@435	83	REGISTER_DECLARATION(Register, G3_scratch , G3);
duke@435	84	REGISTER_DECLARATION(Register, G4_scratch , G4);
duke@435	85
duke@435	86	// These globals are used as short-lived scratch registers in the compiler:
duke@435	87
duke@435	88	REGISTER_DECLARATION(Register, Gtemp , G5);
duke@435	89
jrose@1145	90	// JSR 292 fixed register usages:
jrose@1145	91	REGISTER_DECLARATION(Register, G5_method_type , G5);
jrose@1145	92	REGISTER_DECLARATION(Register, G3_method_handle , G3);
twisti@1919	93	REGISTER_DECLARATION(Register, L7_mh_SP_save , L7);
jrose@1145	94
duke@435	95	// The compiler requires that G5_megamorphic_method is G5_inline_cache_klass,
duke@435	96	// because a single patchable "set" instruction (NativeMovConstReg,
duke@435	97	// or NativeMovConstPatching for compiler1) instruction
duke@435	98	// serves to set up either quantity, depending on whether the compiled
duke@435	99	// call site is an inline cache or is megamorphic. See the function
duke@435	100	// CompiledIC::set_to_megamorphic.
duke@435	101	//
jrose@1145	102	// If a inline cache targets an interpreted method, then the
jrose@1145	103	// G5 register will be used twice during the call. First,
jrose@1145	104	// the call site will be patched to load a compiledICHolder
jrose@1145	105	// into G5. (This is an ordered pair of ic_klass, method.)
jrose@1145	106	// The c2i adapter will first check the ic_klass, then load
jrose@1145	107	// G5_method with the method part of the pair just before
jrose@1145	108	// jumping into the interpreter.
duke@435	109	//
duke@435	110	// Note that G5_method is only the method-self for the interpreter,
duke@435	111	// and is logically unrelated to G5_megamorphic_method.
duke@435	112	//
duke@435	113	// Invariants on G2_thread (the JavaThread pointer):
duke@435	114	// - it should not be used for any other purpose anywhere
duke@435	115	// - it must be re-initialized by StubRoutines::call_stub()
duke@435	116	// - it must be preserved around every use of call_VM
duke@435	117
duke@435	118	// We can consider using g2/g3/g4 to cache more values than the
duke@435	119	// JavaThread, such as the card-marking base or perhaps pointers into
duke@435	120	// Eden. It's something of a waste to use them as scratch temporaries,
duke@435	121	// since they are not supposed to be volatile. (Of course, if we find
duke@435	122	// that Java doesn't benefit from application globals, then we can just
duke@435	123	// use them as ordinary temporaries.)
duke@435	124	//
duke@435	125	// Since g1 and g5 (and/or g6) are the volatile (caller-save) registers,
duke@435	126	// it makes sense to use them routinely for procedure linkage,
duke@435	127	// whenever the On registers are not applicable. Examples: G5_method,
duke@435	128	// G5_inline_cache_klass, and a double handful of miscellaneous compiler
duke@435	129	// stubs. This means that compiler stubs, etc., should be kept to a
duke@435	130	// maximum of two or three G-register arguments.
duke@435	131
duke@435	132
duke@435	133	// stub frames
duke@435	134
duke@435	135	REGISTER_DECLARATION(Register, Lentry_args , L0); // pointer to args passed to callee (interpreter) not stub itself
duke@435	136
duke@435	137	// Interpreter frames
duke@435	138
duke@435	139	#ifdef CC_INTERP
duke@435	140	REGISTER_DECLARATION(Register, Lstate , L0); // interpreter state object pointer
duke@435	141	REGISTER_DECLARATION(Register, L1_scratch , L1); // scratch
duke@435	142	REGISTER_DECLARATION(Register, Lmirror , L1); // mirror (for native methods only)
duke@435	143	REGISTER_DECLARATION(Register, L2_scratch , L2);
duke@435	144	REGISTER_DECLARATION(Register, L3_scratch , L3);
duke@435	145	REGISTER_DECLARATION(Register, L4_scratch , L4);
duke@435	146	REGISTER_DECLARATION(Register, Lscratch , L5); // C1 uses
duke@435	147	REGISTER_DECLARATION(Register, Lscratch2 , L6); // C1 uses
duke@435	148	REGISTER_DECLARATION(Register, L7_scratch , L7); // constant pool cache
duke@435	149	REGISTER_DECLARATION(Register, O5_savedSP , O5);
duke@435	150	REGISTER_DECLARATION(Register, I5_savedSP , I5); // Saved SP before bumping for locals. This is simply
duke@435	151	// a copy SP, so in 64-bit it's a biased value. The bias
duke@435	152	// is added and removed as needed in the frame code.
duke@435	153	// Interface to signature handler
duke@435	154	REGISTER_DECLARATION(Register, Llocals , L7); // pointer to locals for signature handler
duke@435	155	REGISTER_DECLARATION(Register, Lmethod , L6); // methodOop when calling signature handler
duke@435	156
duke@435	157	#else
duke@435	158	REGISTER_DECLARATION(Register, Lesp , L0); // expression stack pointer
duke@435	159	REGISTER_DECLARATION(Register, Lbcp , L1); // pointer to next bytecode
duke@435	160	REGISTER_DECLARATION(Register, Lmethod , L2);
duke@435	161	REGISTER_DECLARATION(Register, Llocals , L3);
duke@435	162	REGISTER_DECLARATION(Register, Largs , L3); // pointer to locals for signature handler
duke@435	163	// must match Llocals in asm interpreter
duke@435	164	REGISTER_DECLARATION(Register, Lmonitors , L4);
duke@435	165	REGISTER_DECLARATION(Register, Lbyte_code , L5);
duke@435	166	// When calling out from the interpreter we record SP so that we can remove any extra stack
duke@435	167	// space allocated during adapter transitions. This register is only live from the point
duke@435	168	// of the call until we return.
duke@435	169	REGISTER_DECLARATION(Register, Llast_SP , L5);
duke@435	170	REGISTER_DECLARATION(Register, Lscratch , L5);
duke@435	171	REGISTER_DECLARATION(Register, Lscratch2 , L6);
duke@435	172	REGISTER_DECLARATION(Register, LcpoolCache , L6); // constant pool cache
duke@435	173
duke@435	174	REGISTER_DECLARATION(Register, O5_savedSP , O5);
duke@435	175	REGISTER_DECLARATION(Register, I5_savedSP , I5); // Saved SP before bumping for locals. This is simply
duke@435	176	// a copy SP, so in 64-bit it's a biased value. The bias
duke@435	177	// is added and removed as needed in the frame code.
duke@435	178	REGISTER_DECLARATION(Register, IdispatchTables , I4); // Base address of the bytecode dispatch tables
duke@435	179	REGISTER_DECLARATION(Register, IdispatchAddress , I3); // Register which saves the dispatch address for each bytecode
duke@435	180	REGISTER_DECLARATION(Register, ImethodDataPtr , I2); // Pointer to the current method data
duke@435	181	#endif /* CC_INTERP */
duke@435	182
duke@435	183	// NOTE: Lscratch2 and LcpoolCache point to the same registers in
duke@435	184	// the interpreter code. If Lscratch2 needs to be used for some
duke@435	185	// purpose than LcpoolCache should be restore after that for
duke@435	186	// the interpreter to work right
duke@435	187	// (These assignments must be compatible with L7_thread_cache; see above.)
duke@435	188
duke@435	189	// Since Lbcp points into the middle of the method object,
duke@435	190	// it is temporarily converted into a "bcx" during GC.
duke@435	191
duke@435	192	// Exception processing
duke@435	193	// These registers are passed into exception handlers.
duke@435	194	// All exception handlers require the exception object being thrown.
duke@435	195	// In addition, an nmethod's exception handler must be passed
duke@435	196	// the address of the call site within the nmethod, to allow
duke@435	197	// proper selection of the applicable catch block.
duke@435	198	// (Interpreter frames use their own bcp() for this purpose.)
duke@435	199	//
duke@435	200	// The Oissuing_pc value is not always needed. When jumping to a
duke@435	201	// handler that is known to be interpreted, the Oissuing_pc value can be
duke@435	202	// omitted. An actual catch block in compiled code receives (from its
duke@435	203	// nmethod's exception handler) the thrown exception in the Oexception,
duke@435	204	// but it doesn't need the Oissuing_pc.
duke@435	205	//
duke@435	206	// If an exception handler (either interpreted or compiled)
duke@435	207	// discovers there is no applicable catch block, it updates
duke@435	208	// the Oissuing_pc to the continuation PC of its own caller,
duke@435	209	// pops back to that caller's stack frame, and executes that
duke@435	210	// caller's exception handler. Obviously, this process will
duke@435	211	// iterate until the control stack is popped back to a method
duke@435	212	// containing an applicable catch block. A key invariant is
duke@435	213	// that the Oissuing_pc value is always a value local to
duke@435	214	// the method whose exception handler is currently executing.
duke@435	215	//
duke@435	216	// Note: The issuing PC value is __not__ a raw return address (I7 value).
duke@435	217	// It is a "return pc", the address __following__ the call.
duke@435	218	// Raw return addresses are converted to issuing PCs by frame::pc(),
duke@435	219	// or by stubs. Issuing PCs can be used directly with PC range tables.
duke@435	220	//
duke@435	221	REGISTER_DECLARATION(Register, Oexception , O0); // exception being thrown
duke@435	222	REGISTER_DECLARATION(Register, Oissuing_pc , O1); // where the exception is coming from
duke@435	223
duke@435	224
duke@435	225	// These must occur after the declarations above
duke@435	226	#ifndef DONT_USE_REGISTER_DEFINES
duke@435	227
duke@435	228	#define Gthread AS_REGISTER(Register, Gthread)
duke@435	229	#define Gmethod AS_REGISTER(Register, Gmethod)
duke@435	230	#define Gmegamorphic_method AS_REGISTER(Register, Gmegamorphic_method)
duke@435	231	#define Ginline_cache_reg AS_REGISTER(Register, Ginline_cache_reg)
duke@435	232	#define Gargs AS_REGISTER(Register, Gargs)
duke@435	233	#define Lthread_cache AS_REGISTER(Register, Lthread_cache)
duke@435	234	#define Gframe_size AS_REGISTER(Register, Gframe_size)
duke@435	235	#define Gtemp AS_REGISTER(Register, Gtemp)
duke@435	236
duke@435	237	#ifdef CC_INTERP
duke@435	238	#define Lstate AS_REGISTER(Register, Lstate)
duke@435	239	#define Lesp AS_REGISTER(Register, Lesp)
duke@435	240	#define L1_scratch AS_REGISTER(Register, L1_scratch)
duke@435	241	#define Lmirror AS_REGISTER(Register, Lmirror)
duke@435	242	#define L2_scratch AS_REGISTER(Register, L2_scratch)
duke@435	243	#define L3_scratch AS_REGISTER(Register, L3_scratch)
duke@435	244	#define L4_scratch AS_REGISTER(Register, L4_scratch)
duke@435	245	#define Lscratch AS_REGISTER(Register, Lscratch)
duke@435	246	#define Lscratch2 AS_REGISTER(Register, Lscratch2)
duke@435	247	#define L7_scratch AS_REGISTER(Register, L7_scratch)
duke@435	248	#define Ostate AS_REGISTER(Register, Ostate)
duke@435	249	#else
duke@435	250	#define Lesp AS_REGISTER(Register, Lesp)
duke@435	251	#define Lbcp AS_REGISTER(Register, Lbcp)
duke@435	252	#define Lmethod AS_REGISTER(Register, Lmethod)
duke@435	253	#define Llocals AS_REGISTER(Register, Llocals)
duke@435	254	#define Lmonitors AS_REGISTER(Register, Lmonitors)
duke@435	255	#define Lbyte_code AS_REGISTER(Register, Lbyte_code)
duke@435	256	#define Lscratch AS_REGISTER(Register, Lscratch)
duke@435	257	#define Lscratch2 AS_REGISTER(Register, Lscratch2)
duke@435	258	#define LcpoolCache AS_REGISTER(Register, LcpoolCache)
duke@435	259	#endif /* ! CC_INTERP */
duke@435	260
duke@435	261	#define Lentry_args AS_REGISTER(Register, Lentry_args)
duke@435	262	#define I5_savedSP AS_REGISTER(Register, I5_savedSP)
duke@435	263	#define O5_savedSP AS_REGISTER(Register, O5_savedSP)
duke@435	264	#define IdispatchAddress AS_REGISTER(Register, IdispatchAddress)
duke@435	265	#define ImethodDataPtr AS_REGISTER(Register, ImethodDataPtr)
duke@435	266	#define IdispatchTables AS_REGISTER(Register, IdispatchTables)
duke@435	267
duke@435	268	#define Oexception AS_REGISTER(Register, Oexception)
duke@435	269	#define Oissuing_pc AS_REGISTER(Register, Oissuing_pc)
duke@435	270
duke@435	271
duke@435	272	#endif
duke@435	273
duke@435	274	// Address is an abstraction used to represent a memory location.
duke@435	275	//
duke@435	276	// Note: A register location is represented via a Register, not
duke@435	277	// via an address for efficiency & simplicity reasons.
duke@435	278
duke@435	279	class Address VALUE_OBJ_CLASS_SPEC {
duke@435	280	private:
twisti@1162	281	Register _base; // Base register.
twisti@1162	282	RegisterOrConstant _index_or_disp; // Index register or constant displacement.
twisti@1162	283	RelocationHolder _rspec;
twisti@1162	284
twisti@1162	285	public:
twisti@1162	286	Address() : _base(noreg), _index_or_disp(noreg) {}
twisti@1162	287
twisti@1162	288	Address(Register base, RegisterOrConstant index_or_disp)
twisti@1162	289	: _base(base),
twisti@1162	290	_index_or_disp(index_or_disp) {
twisti@1162	291	}
twisti@1162	292
twisti@1162	293	Address(Register base, Register index)
twisti@1162	294	: _base(base),
twisti@1162	295	_index_or_disp(index) {
twisti@1162	296	}
twisti@1162	297
twisti@1162	298	Address(Register base, int disp)
twisti@1162	299	: _base(base),
twisti@1162	300	_index_or_disp(disp) {
twisti@1162	301	}
twisti@1162	302
twisti@1162	303	#ifdef ASSERT
twisti@1162	304	// ByteSize is only a class when ASSERT is defined, otherwise it's an int.
twisti@1162	305	Address(Register base, ByteSize disp)
twisti@1162	306	: _base(base),
twisti@1162	307	_index_or_disp(in_bytes(disp)) {
twisti@1162	308	}
duke@435	309	#endif
twisti@1162	310
twisti@1162	311	// accessors
never@2950	312	Register base() const { return _base; }
never@2950	313	Register index() const { return _index_or_disp.as_register(); }
never@2950	314	int disp() const { return _index_or_disp.as_constant(); }
never@2950	315
never@2950	316	bool has_index() const { return _index_or_disp.is_register(); }
never@2950	317	bool has_disp() const { return _index_or_disp.is_constant(); }
never@2950	318
never@2950	319	bool uses(Register reg) const { return base() == reg || (has_index() && index() == reg); }
twisti@1162	320
twisti@1162	321	const relocInfo::relocType rtype() { return _rspec.type(); }
twisti@1162	322	const RelocationHolder& rspec() { return _rspec; }
twisti@1162	323
twisti@1162	324	RelocationHolder rspec(int offset) const {
twisti@1162	325	return offset == 0 ? _rspec : _rspec.plus(offset);
twisti@1162	326	}
twisti@1162	327
twisti@1162	328	inline bool is_simm13(int offset = 0); // check disp+offset for overflow
twisti@1162	329
twisti@1162	330	Address plus_disp(int plusdisp) const { // bump disp by a small amount
twisti@1162	331	assert(_index_or_disp.is_constant(), "must have a displacement");
twisti@1162	332	Address a(base(), disp() + plusdisp);
twisti@1162	333	return a;
twisti@1162	334	}
never@2950	335	bool is_same_address(Address a) const {
never@2950	336	// disregard _rspec
never@2950	337	return base() == a.base() && (has_index() ? index() == a.index() : disp() == a.disp());
never@2950	338	}
twisti@1162	339
twisti@1162	340	Address after_save() const {
twisti@1162	341	Address a = (*this);
twisti@1162	342	a._base = a._base->after_save();
twisti@1162	343	return a;
twisti@1162	344	}
twisti@1162	345
twisti@1162	346	Address after_restore() const {
twisti@1162	347	Address a = (*this);
twisti@1162	348	a._base = a._base->after_restore();
twisti@1162	349	return a;
twisti@1162	350	}
twisti@1162	351
twisti@1162	352	// Convert the raw encoding form into the form expected by the
twisti@1162	353	// constructor for Address.
twisti@1162	354	static Address make_raw(int base, int index, int scale, int disp, bool disp_is_oop);
twisti@1162	355
twisti@1162	356	friend class Assembler;
twisti@1162	357	};
twisti@1162	358
twisti@1162	359
twisti@1162	360	class AddressLiteral VALUE_OBJ_CLASS_SPEC {
twisti@1162	361	private:
twisti@1162	362	address _address;
twisti@1162	363	RelocationHolder _rspec;
twisti@1162	364
twisti@1162	365	RelocationHolder rspec_from_rtype(relocInfo::relocType rtype, address addr) {
twisti@1162	366	switch (rtype) {
duke@435	367	case relocInfo::external_word_type:
twisti@1162	368	return external_word_Relocation::spec(addr);
duke@435	369	case relocInfo::internal_word_type:
twisti@1162	370	return internal_word_Relocation::spec(addr);
duke@435	371	#ifdef _LP64
duke@435	372	case relocInfo::opt_virtual_call_type:
duke@435	373	return opt_virtual_call_Relocation::spec();
duke@435	374	case relocInfo::static_call_type:
duke@435	375	return static_call_Relocation::spec();
duke@435	376	case relocInfo::runtime_call_type:
duke@435	377	return runtime_call_Relocation::spec();
duke@435	378	#endif
duke@435	379	case relocInfo::none:
duke@435	380	return RelocationHolder();
duke@435	381	default:
duke@435	382	ShouldNotReachHere();
duke@435	383	return RelocationHolder();
duke@435	384	}
duke@435	385	}
duke@435	386
twisti@1162	387	protected:
twisti@1162	388	// creation
twisti@1162	389	AddressLiteral() : _address(NULL), _rspec(NULL) {}
twisti@1162	390
duke@435	391	public:
twisti@1162	392	AddressLiteral(address addr, RelocationHolder const& rspec)
twisti@1162	393	: _address(addr),
twisti@1162	394	_rspec(rspec) {}
twisti@1162	395
twisti@1162	396	// Some constructors to avoid casting at the call site.
twisti@1162	397	AddressLiteral(jobject obj, RelocationHolder const& rspec)
twisti@1162	398	: _address((address) obj),
twisti@1162	399	_rspec(rspec) {}
twisti@1162	400
twisti@1162	401	AddressLiteral(intptr_t value, RelocationHolder const& rspec)
twisti@1162	402	: _address((address) value),
twisti@1162	403	_rspec(rspec) {}
twisti@1162	404
twisti@1162	405	AddressLiteral(address addr, relocInfo::relocType rtype = relocInfo::none)
twisti@1162	406	: _address((address) addr),
twisti@1162	407	_rspec(rspec_from_rtype(rtype, (address) addr)) {}
twisti@1162	408
twisti@1162	409	// Some constructors to avoid casting at the call site.
twisti@1162	410	AddressLiteral(address* addr, relocInfo::relocType rtype = relocInfo::none)
twisti@1162	411	: _address((address) addr),
twisti@1162	412	_rspec(rspec_from_rtype(rtype, (address) addr)) {}
twisti@1162	413
twisti@1162	414	AddressLiteral(bool* addr, relocInfo::relocType rtype = relocInfo::none)
twisti@1162	415	: _address((address) addr),
twisti@1162	416	_rspec(rspec_from_rtype(rtype, (address) addr)) {}
twisti@1162	417
twisti@1162	418	AddressLiteral(const bool* addr, relocInfo::relocType rtype = relocInfo::none)
twisti@1162	419	: _address((address) addr),
twisti@1162	420	_rspec(rspec_from_rtype(rtype, (address) addr)) {}
twisti@1162	421
twisti@1162	422	AddressLiteral(signed char* addr, relocInfo::relocType rtype = relocInfo::none)
twisti@1162	423	: _address((address) addr),
twisti@1162	424	_rspec(rspec_from_rtype(rtype, (address) addr)) {}
twisti@1162	425
twisti@1162	426	AddressLiteral(int* addr, relocInfo::relocType rtype = relocInfo::none)
twisti@1162	427	: _address((address) addr),
twisti@1162	428	_rspec(rspec_from_rtype(rtype, (address) addr)) {}
twisti@1162	429
twisti@1162	430	AddressLiteral(intptr_t addr, relocInfo::relocType rtype = relocInfo::none)
twisti@1162	431	: _address((address) addr),
twisti@1162	432	_rspec(rspec_from_rtype(rtype, (address) addr)) {}
twisti@1162	433
duke@435	434	#ifdef _LP64
twisti@1162	435	// 32-bit complains about a multiple declaration for int*.
twisti@1162	436	AddressLiteral(intptr_t* addr, relocInfo::relocType rtype = relocInfo::none)
twisti@1162	437	: _address((address) addr),
twisti@1162	438	_rspec(rspec_from_rtype(rtype, (address) addr)) {}
duke@435	439	#endif
twisti@1162	440
twisti@1162	441	AddressLiteral(oop addr, relocInfo::relocType rtype = relocInfo::none)
twisti@1162	442	: _address((address) addr),
twisti@1162	443	_rspec(rspec_from_rtype(rtype, (address) addr)) {}
twisti@1162	444
never@2950	445	AddressLiteral(oop* addr, relocInfo::relocType rtype = relocInfo::none)
never@2950	446	: _address((address) addr),
never@2950	447	_rspec(rspec_from_rtype(rtype, (address) addr)) {}
never@2950	448
twisti@1162	449	AddressLiteral(float* addr, relocInfo::relocType rtype = relocInfo::none)
twisti@1162	450	: _address((address) addr),
twisti@1162	451	_rspec(rspec_from_rtype(rtype, (address) addr)) {}
twisti@1162	452
twisti@1162	453	AddressLiteral(double* addr, relocInfo::relocType rtype = relocInfo::none)
twisti@1162	454	: _address((address) addr),
twisti@1162	455	_rspec(rspec_from_rtype(rtype, (address) addr)) {}
twisti@1162	456
twisti@1162	457	intptr_t value() const { return (intptr_t) _address; }
twisti@1162	458	int low10() const;
twisti@1162	459
twisti@1162	460	const relocInfo::relocType rtype() const { return _rspec.type(); }
twisti@1162	461	const RelocationHolder& rspec() const { return _rspec; }
twisti@1162	462
twisti@1162	463	RelocationHolder rspec(int offset) const {
duke@435	464	return offset == 0 ? _rspec : _rspec.plus(offset);
duke@435	465	}
duke@435	466	};
duke@435	467
never@2950	468	// Convenience classes
never@2950	469	class ExternalAddress: public AddressLiteral {
never@2950	470	private:
never@2950	471	static relocInfo::relocType reloc_for_target(address target) {
never@2950	472	// Sometimes ExternalAddress is used for values which aren't
never@2950	473	// exactly addresses, like the card table base.
never@2950	474	// external_word_type can't be used for values in the first page
never@2950	475	// so just skip the reloc in that case.
never@2950	476	return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none;
never@2950	477	}
never@2950	478
never@2950	479	public:
never@2950	480	ExternalAddress(address target) : AddressLiteral(target, reloc_for_target( target)) {}
never@2950	481	ExternalAddress(oop* target) : AddressLiteral(target, reloc_for_target((address) target)) {}
never@2950	482	};
duke@435	483
duke@435	484	inline Address RegisterImpl::address_in_saved_window() const {
twisti@1162	485	return (Address(SP, (sp_offset_in_saved_window() * wordSize) + STACK_BIAS));
duke@435	486	}
duke@435	487
duke@435	488
duke@435	489
duke@435	490	// Argument is an abstraction used to represent an outgoing
duke@435	491	// actual argument or an incoming formal parameter, whether
duke@435	492	// it resides in memory or in a register, in a manner consistent
duke@435	493	// with the SPARC Application Binary Interface, or ABI. This is
duke@435	494	// often referred to as the native or C calling convention.
duke@435	495
duke@435	496	class Argument VALUE_OBJ_CLASS_SPEC {
duke@435	497	private:
duke@435	498	int _number;
duke@435	499	bool _is_in;
duke@435	500
duke@435	501	public:
duke@435	502	#ifdef _LP64
duke@435	503	enum {
duke@435	504	n_register_parameters = 6, // only 6 registers may contain integer parameters
duke@435	505	n_float_register_parameters = 16 // Can have up to 16 floating registers
duke@435	506	};
duke@435	507	#else
duke@435	508	enum {
duke@435	509	n_register_parameters = 6 // only 6 registers may contain integer parameters
duke@435	510	};
duke@435	511	#endif
duke@435	512
duke@435	513	// creation
duke@435	514	Argument(int number, bool is_in) : _number(number), _is_in(is_in) {}
duke@435	515
duke@435	516	int number() const { return _number; }
duke@435	517	bool is_in() const { return _is_in; }
duke@435	518	bool is_out() const { return !is_in(); }
duke@435	519
duke@435	520	Argument successor() const { return Argument(number() + 1, is_in()); }
duke@435	521	Argument as_in() const { return Argument(number(), true ); }
duke@435	522	Argument as_out() const { return Argument(number(), false); }
duke@435	523
duke@435	524	// locating register-based arguments:
duke@435	525	bool is_register() const { return _number < n_register_parameters; }
duke@435	526
duke@435	527	#ifdef _LP64
duke@435	528	// locating Floating Point register-based arguments:
duke@435	529	bool is_float_register() const { return _number < n_float_register_parameters; }
duke@435	530
duke@435	531	FloatRegister as_float_register() const {
duke@435	532	assert(is_float_register(), "must be a register argument");
duke@435	533	return as_FloatRegister(( number() *2 ) + 1);
duke@435	534	}
duke@435	535	FloatRegister as_double_register() const {
duke@435	536	assert(is_float_register(), "must be a register argument");
duke@435	537	return as_FloatRegister(( number() *2 ));
duke@435	538	}
duke@435	539	#endif
duke@435	540
duke@435	541	Register as_register() const {
duke@435	542	assert(is_register(), "must be a register argument");
duke@435	543	return is_in() ? as_iRegister(number()) : as_oRegister(number());
duke@435	544	}
duke@435	545
duke@435	546	// locating memory-based arguments
duke@435	547	Address as_address() const {
duke@435	548	assert(!is_register(), "must be a memory argument");
duke@435	549	return address_in_frame();
duke@435	550	}
duke@435	551
duke@435	552	// When applied to a register-based argument, give the corresponding address
duke@435	553	// into the 6-word area "into which callee may store register arguments"
duke@435	554	// (This is a different place than the corresponding register-save area location.)
twisti@1162	555	Address address_in_frame() const;
duke@435	556
duke@435	557	// debugging
duke@435	558	const char* name() const;
duke@435	559
duke@435	560	friend class Assembler;
duke@435	561	};
duke@435	562
duke@435	563
duke@435	564	// The SPARC Assembler: Pure assembler doing NO optimizations on the instruction
duke@435	565	// level; i.e., what you write
duke@435	566	// is what you get. The Assembler is generating code into a CodeBuffer.
duke@435	567
duke@435	568	class Assembler : public AbstractAssembler {
duke@435	569	protected:
duke@435	570
duke@435	571	static void print_instruction(int inst);
duke@435	572	static int patched_branch(int dest_pos, int inst, int inst_pos);
duke@435	573	static int branch_destination(int inst, int pos);
duke@435	574
duke@435	575
duke@435	576	friend class AbstractAssembler;
twisti@1162	577	friend class AddressLiteral;
duke@435	578
duke@435	579	// code patchers need various routines like inv_wdisp()
duke@435	580	friend class NativeInstruction;
duke@435	581	friend class NativeGeneralJump;
duke@435	582	friend class Relocation;
duke@435	583	friend class Label;
duke@435	584
duke@435	585	public:
duke@435	586	// op carries format info; see page 62 & 267
duke@435	587
duke@435	588	enum ops {
duke@435	589	call_op = 1, // fmt 1
duke@435	590	branch_op = 0, // also sethi (fmt2)
duke@435	591	arith_op = 2, // fmt 3, arith & misc
duke@435	592	ldst_op = 3 // fmt 3, load/store
duke@435	593	};
duke@435	594
duke@435	595	enum op2s {
duke@435	596	bpr_op2 = 3,
duke@435	597	fb_op2 = 6,
duke@435	598	fbp_op2 = 5,
duke@435	599	br_op2 = 2,
duke@435	600	bp_op2 = 1,
duke@435	601	cb_op2 = 7, // V8
duke@435	602	sethi_op2 = 4
duke@435	603	};
duke@435	604
duke@435	605	enum op3s {
duke@435	606	// selected op3s
duke@435	607	add_op3 = 0x00,
duke@435	608	and_op3 = 0x01,
duke@435	609	or_op3 = 0x02,
duke@435	610	xor_op3 = 0x03,
duke@435	611	sub_op3 = 0x04,
duke@435	612	andn_op3 = 0x05,
duke@435	613	orn_op3 = 0x06,
duke@435	614	xnor_op3 = 0x07,
duke@435	615	addc_op3 = 0x08,
duke@435	616	mulx_op3 = 0x09,
duke@435	617	umul_op3 = 0x0a,
duke@435	618	smul_op3 = 0x0b,
duke@435	619	subc_op3 = 0x0c,
duke@435	620	udivx_op3 = 0x0d,
duke@435	621	udiv_op3 = 0x0e,
duke@435	622	sdiv_op3 = 0x0f,
duke@435	623
duke@435	624	addcc_op3 = 0x10,
duke@435	625	andcc_op3 = 0x11,
duke@435	626	orcc_op3 = 0x12,
duke@435	627	xorcc_op3 = 0x13,
duke@435	628	subcc_op3 = 0x14,
duke@435	629	andncc_op3 = 0x15,
duke@435	630	orncc_op3 = 0x16,
duke@435	631	xnorcc_op3 = 0x17,
duke@435	632	addccc_op3 = 0x18,
duke@435	633	umulcc_op3 = 0x1a,
duke@435	634	smulcc_op3 = 0x1b,
duke@435	635	subccc_op3 = 0x1c,
duke@435	636	udivcc_op3 = 0x1e,
duke@435	637	sdivcc_op3 = 0x1f,
duke@435	638
duke@435	639	taddcc_op3 = 0x20,
duke@435	640	tsubcc_op3 = 0x21,
duke@435	641	taddcctv_op3 = 0x22,
duke@435	642	tsubcctv_op3 = 0x23,
duke@435	643	mulscc_op3 = 0x24,
duke@435	644	sll_op3 = 0x25,
duke@435	645	sllx_op3 = 0x25,
duke@435	646	srl_op3 = 0x26,
duke@435	647	srlx_op3 = 0x26,
duke@435	648	sra_op3 = 0x27,
duke@435	649	srax_op3 = 0x27,
duke@435	650	rdreg_op3 = 0x28,
duke@435	651	membar_op3 = 0x28,
duke@435	652
duke@435	653	flushw_op3 = 0x2b,
duke@435	654	movcc_op3 = 0x2c,
duke@435	655	sdivx_op3 = 0x2d,
duke@435	656	popc_op3 = 0x2e,
duke@435	657	movr_op3 = 0x2f,
duke@435	658
duke@435	659	sir_op3 = 0x30,
duke@435	660	wrreg_op3 = 0x30,
duke@435	661	saved_op3 = 0x31,
duke@435	662
duke@435	663	fpop1_op3 = 0x34,
duke@435	664	fpop2_op3 = 0x35,
duke@435	665	impdep1_op3 = 0x36,
duke@435	666	impdep2_op3 = 0x37,
duke@435	667	jmpl_op3 = 0x38,
duke@435	668	rett_op3 = 0x39,
duke@435	669	trap_op3 = 0x3a,
duke@435	670	flush_op3 = 0x3b,
duke@435	671	save_op3 = 0x3c,
duke@435	672	restore_op3 = 0x3d,
duke@435	673	done_op3 = 0x3e,
duke@435	674	retry_op3 = 0x3e,
duke@435	675
duke@435	676	lduw_op3 = 0x00,
duke@435	677	ldub_op3 = 0x01,
duke@435	678	lduh_op3 = 0x02,
duke@435	679	ldd_op3 = 0x03,
duke@435	680	stw_op3 = 0x04,
duke@435	681	stb_op3 = 0x05,
duke@435	682	sth_op3 = 0x06,
duke@435	683	std_op3 = 0x07,
duke@435	684	ldsw_op3 = 0x08,
duke@435	685	ldsb_op3 = 0x09,
duke@435	686	ldsh_op3 = 0x0a,
duke@435	687	ldx_op3 = 0x0b,
duke@435	688
duke@435	689	ldstub_op3 = 0x0d,
duke@435	690	stx_op3 = 0x0e,
duke@435	691	swap_op3 = 0x0f,
duke@435	692
duke@435	693	stwa_op3 = 0x14,
duke@435	694	stxa_op3 = 0x1e,
duke@435	695
duke@435	696	ldf_op3 = 0x20,
duke@435	697	ldfsr_op3 = 0x21,
duke@435	698	ldqf_op3 = 0x22,
duke@435	699	lddf_op3 = 0x23,
duke@435	700	stf_op3 = 0x24,
duke@435	701	stfsr_op3 = 0x25,
duke@435	702	stqf_op3 = 0x26,
duke@435	703	stdf_op3 = 0x27,
duke@435	704
duke@435	705	prefetch_op3 = 0x2d,
duke@435	706
duke@435	707
duke@435	708	ldc_op3 = 0x30,
duke@435	709	ldcsr_op3 = 0x31,
duke@435	710	lddc_op3 = 0x33,
duke@435	711	stc_op3 = 0x34,
duke@435	712	stcsr_op3 = 0x35,
duke@435	713	stdcq_op3 = 0x36,
duke@435	714	stdc_op3 = 0x37,
duke@435	715
duke@435	716	casa_op3 = 0x3c,
duke@435	717	casxa_op3 = 0x3e,
duke@435	718
duke@435	719	alt_bit_op3 = 0x10,
duke@435	720	cc_bit_op3 = 0x10
duke@435	721	};
duke@435	722
duke@435	723	enum opfs {
duke@435	724	// selected opfs
duke@435	725	fmovs_opf = 0x01,
duke@435	726	fmovd_opf = 0x02,
duke@435	727
duke@435	728	fnegs_opf = 0x05,
duke@435	729	fnegd_opf = 0x06,
duke@435	730
duke@435	731	fadds_opf = 0x41,
duke@435	732	faddd_opf = 0x42,
duke@435	733	fsubs_opf = 0x45,
duke@435	734	fsubd_opf = 0x46,
duke@435	735
duke@435	736	fmuls_opf = 0x49,
duke@435	737	fmuld_opf = 0x4a,
duke@435	738	fdivs_opf = 0x4d,
duke@435	739	fdivd_opf = 0x4e,
duke@435	740
duke@435	741	fcmps_opf = 0x51,
duke@435	742	fcmpd_opf = 0x52,
duke@435	743
duke@435	744	fstox_opf = 0x81,
duke@435	745	fdtox_opf = 0x82,
duke@435	746	fxtos_opf = 0x84,
duke@435	747	fxtod_opf = 0x88,
duke@435	748	fitos_opf = 0xc4,
duke@435	749	fdtos_opf = 0xc6,
duke@435	750	fitod_opf = 0xc8,
duke@435	751	fstod_opf = 0xc9,
duke@435	752	fstoi_opf = 0xd1,
duke@435	753	fdtoi_opf = 0xd2
duke@435	754	};
duke@435	755
duke@435	756	enum RCondition { rc_z = 1, rc_lez = 2, rc_lz = 3, rc_nz = 5, rc_gz = 6, rc_gez = 7 };
duke@435	757
duke@435	758	enum Condition {
duke@435	759	// for FBfcc & FBPfcc instruction
duke@435	760	f_never = 0,
duke@435	761	f_notEqual = 1,
duke@435	762	f_notZero = 1,
duke@435	763	f_lessOrGreater = 2,
duke@435	764	f_unorderedOrLess = 3,
duke@435	765	f_less = 4,
duke@435	766	f_unorderedOrGreater = 5,
duke@435	767	f_greater = 6,
duke@435	768	f_unordered = 7,
duke@435	769	f_always = 8,
duke@435	770	f_equal = 9,
duke@435	771	f_zero = 9,
duke@435	772	f_unorderedOrEqual = 10,
duke@435	773	f_greaterOrEqual = 11,
duke@435	774	f_unorderedOrGreaterOrEqual = 12,
duke@435	775	f_lessOrEqual = 13,
duke@435	776	f_unorderedOrLessOrEqual = 14,
duke@435	777	f_ordered = 15,
duke@435	778
duke@435	779	// V8 coproc, pp 123 v8 manual
duke@435	780
duke@435	781	cp_always = 8,
duke@435	782	cp_never = 0,
duke@435	783	cp_3 = 7,
duke@435	784	cp_2 = 6,
duke@435	785	cp_2or3 = 5,
duke@435	786	cp_1 = 4,
duke@435	787	cp_1or3 = 3,
duke@435	788	cp_1or2 = 2,
duke@435	789	cp_1or2or3 = 1,
duke@435	790	cp_0 = 9,
duke@435	791	cp_0or3 = 10,
duke@435	792	cp_0or2 = 11,
duke@435	793	cp_0or2or3 = 12,
duke@435	794	cp_0or1 = 13,
duke@435	795	cp_0or1or3 = 14,
duke@435	796	cp_0or1or2 = 15,
duke@435	797
duke@435	798
duke@435	799	// for integers
duke@435	800
duke@435	801	never = 0,
duke@435	802	equal = 1,
duke@435	803	zero = 1,
duke@435	804	lessEqual = 2,
duke@435	805	less = 3,
duke@435	806	lessEqualUnsigned = 4,
duke@435	807	lessUnsigned = 5,
duke@435	808	carrySet = 5,
duke@435	809	negative = 6,
duke@435	810	overflowSet = 7,
duke@435	811	always = 8,
duke@435	812	notEqual = 9,
duke@435	813	notZero = 9,
duke@435	814	greater = 10,
duke@435	815	greaterEqual = 11,
duke@435	816	greaterUnsigned = 12,
duke@435	817	greaterEqualUnsigned = 13,
duke@435	818	carryClear = 13,
duke@435	819	positive = 14,
duke@435	820	overflowClear = 15
duke@435	821	};
duke@435	822
duke@435	823	enum CC {
duke@435	824	icc = 0, xcc = 2,
duke@435	825	// ptr_cc is the correct condition code for a pointer or intptr_t:
duke@435	826	ptr_cc = NOT_LP64(icc) LP64_ONLY(xcc),
duke@435	827	fcc0 = 0, fcc1 = 1, fcc2 = 2, fcc3 = 3
duke@435	828	};
duke@435	829
duke@435	830	enum PrefetchFcn {
duke@435	831	severalReads = 0, oneRead = 1, severalWritesAndPossiblyReads = 2, oneWrite = 3, page = 4
duke@435	832	};
duke@435	833
duke@435	834	public:
duke@435	835	// Helper functions for groups of instructions
duke@435	836
duke@435	837	enum Predict { pt = 1, pn = 0 }; // pt = predict taken
duke@435	838
duke@435	839	enum Membar_mask_bits { // page 184, v9
duke@435	840	StoreStore = 1 << 3,
duke@435	841	LoadStore = 1 << 2,
duke@435	842	StoreLoad = 1 << 1,
duke@435	843	LoadLoad = 1 << 0,
duke@435	844
duke@435	845	Sync = 1 << 6,
duke@435	846	MemIssue = 1 << 5,
duke@435	847	Lookaside = 1 << 4
duke@435	848	};
duke@435	849
duke@435	850	// test if x is within signed immediate range for nbits
iveresov@2441	851	static bool is_simm(intptr_t x, int nbits) { return -( intptr_t(1) << nbits-1 ) <= x && x < ( intptr_t(1) << nbits-1 ); }
duke@435	852
duke@435	853	// test if -4096 <= x <= 4095
iveresov@2441	854	static bool is_simm13(intptr_t x) { return is_simm(x, 13); }
iveresov@2441	855
iveresov@2441	856	static bool is_in_wdisp_range(address a, address b, int nbits) {
iveresov@2441	857	intptr_t d = intptr_t(b) - intptr_t(a);
iveresov@2441	858	return is_simm(d, nbits + 2);
iveresov@2441	859	}
duke@435	860
iveresov@2203	861	// test if label is in simm16 range in words (wdisp16).
iveresov@2203	862	bool is_in_wdisp16_range(Label& L) {
iveresov@2441	863	return is_in_wdisp_range(target(L), pc(), 16);
iveresov@2441	864	}
iveresov@2441	865	// test if the distance between two addresses fits in simm30 range in words
iveresov@2441	866	static bool is_in_wdisp30_range(address a, address b) {
iveresov@2441	867	return is_in_wdisp_range(a, b, 30);
iveresov@2203	868	}
iveresov@2203	869
duke@435	870	enum ASIs { // page 72, v9
duke@435	871	ASI_PRIMARY = 0x80,
duke@435	872	ASI_PRIMARY_LITTLE = 0x88
duke@435	873	// add more from book as needed
duke@435	874	};
duke@435	875
duke@435	876	protected:
duke@435	877	// helpers
duke@435	878
duke@435	879	// x is supposed to fit in a field "nbits" wide
duke@435	880	// and be sign-extended. Check the range.
duke@435	881
duke@435	882	static void assert_signed_range(intptr_t x, int nbits) {
never@2950	883	assert(nbits == 32 || (-(1 << nbits-1) <= x && x < ( 1 << nbits-1)),
never@2950	884	err_msg("value out of range: x=" INTPTR_FORMAT ", nbits=%d", x, nbits));
duke@435	885	}
duke@435	886
duke@435	887	static void assert_signed_word_disp_range(intptr_t x, int nbits) {
duke@435	888	assert( (x & 3) == 0, "not word aligned");
duke@435	889	assert_signed_range(x, nbits + 2);
duke@435	890	}
duke@435	891
duke@435	892	static void assert_unsigned_const(int x, int nbits) {
duke@435	893	assert( juint(x) < juint(1 << nbits), "unsigned constant out of range");
duke@435	894	}
duke@435	895
duke@435	896	// fields: note bits numbered from LSB = 0,
duke@435	897	// fields known by inclusive bit range
duke@435	898
duke@435	899	static int fmask(juint hi_bit, juint lo_bit) {
duke@435	900	assert( hi_bit >= lo_bit && 0 <= lo_bit && hi_bit < 32, "bad bits");
duke@435	901	return (1 << ( hi_bit-lo_bit + 1 )) - 1;
duke@435	902	}
duke@435	903
duke@435	904	// inverse of u_field
duke@435	905
duke@435	906	static int inv_u_field(int x, int hi_bit, int lo_bit) {
duke@435	907	juint r = juint(x) >> lo_bit;
duke@435	908	r &= fmask( hi_bit, lo_bit);
duke@435	909	return int(r);
duke@435	910	}
duke@435	911
duke@435	912
duke@435	913	// signed version: extract from field and sign-extend
duke@435	914
duke@435	915	static int inv_s_field(int x, int hi_bit, int lo_bit) {
duke@435	916	int sign_shift = 31 - hi_bit;
duke@435	917	return inv_u_field( ((x << sign_shift) >> sign_shift), hi_bit, lo_bit);
duke@435	918	}
duke@435	919
duke@435	920	// given a field that ranges from hi_bit to lo_bit (inclusive,
duke@435	921	// LSB = 0), and an unsigned value for the field,
duke@435	922	// shift it into the field
duke@435	923
duke@435	924	#ifdef ASSERT
duke@435	925	static int u_field(int x, int hi_bit, int lo_bit) {
duke@435	926	assert( ( x & ~fmask(hi_bit, lo_bit)) == 0,
duke@435	927	"value out of range");
duke@435	928	int r = x << lo_bit;
duke@435	929	assert( inv_u_field(r, hi_bit, lo_bit) == x, "just checking");
duke@435	930	return r;
duke@435	931	}
duke@435	932	#else
duke@435	933	// make sure this is inlined as it will reduce code size significantly
duke@435	934	#define u_field(x, hi_bit, lo_bit) ((x) << (lo_bit))
duke@435	935	#endif
duke@435	936
duke@435	937	static int inv_op( int x ) { return inv_u_field(x, 31, 30); }
duke@435	938	static int inv_op2( int x ) { return inv_u_field(x, 24, 22); }
duke@435	939	static int inv_op3( int x ) { return inv_u_field(x, 24, 19); }
duke@435	940	static int inv_cond( int x ){ return inv_u_field(x, 28, 25); }
duke@435	941
duke@435	942	static bool inv_immed( int x ) { return (x & Assembler::immed(true)) != 0; }
duke@435	943
duke@435	944	static Register inv_rd( int x ) { return as_Register(inv_u_field(x, 29, 25)); }
duke@435	945	static Register inv_rs1( int x ) { return as_Register(inv_u_field(x, 18, 14)); }
duke@435	946	static Register inv_rs2( int x ) { return as_Register(inv_u_field(x, 4, 0)); }
duke@435	947
duke@435	948	static int op( int x) { return u_field(x, 31, 30); }
duke@435	949	static int rd( Register r) { return u_field(r->encoding(), 29, 25); }
duke@435	950	static int fcn( int x) { return u_field(x, 29, 25); }
duke@435	951	static int op3( int x) { return u_field(x, 24, 19); }
duke@435	952	static int rs1( Register r) { return u_field(r->encoding(), 18, 14); }
duke@435	953	static int rs2( Register r) { return u_field(r->encoding(), 4, 0); }
duke@435	954	static int annul( bool a) { return u_field(a ? 1 : 0, 29, 29); }
duke@435	955	static int cond( int x) { return u_field(x, 28, 25); }
duke@435	956	static int cond_mov( int x) { return u_field(x, 17, 14); }
duke@435	957	static int rcond( RCondition x) { return u_field(x, 12, 10); }
duke@435	958	static int op2( int x) { return u_field(x, 24, 22); }
duke@435	959	static int predict( bool p) { return u_field(p ? 1 : 0, 19, 19); }
duke@435	960	static int branchcc( CC fcca) { return u_field(fcca, 21, 20); }
duke@435	961	static int cmpcc( CC fcca) { return u_field(fcca, 26, 25); }
duke@435	962	static int imm_asi( int x) { return u_field(x, 12, 5); }
duke@435	963	static int immed( bool i) { return u_field(i ? 1 : 0, 13, 13); }
duke@435	964	static int opf_low6( int w) { return u_field(w, 10, 5); }
duke@435	965	static int opf_low5( int w) { return u_field(w, 9, 5); }
duke@435	966	static int trapcc( CC cc) { return u_field(cc, 12, 11); }
duke@435	967	static int sx( int i) { return u_field(i, 12, 12); } // shift x=1 means 64-bit
duke@435	968	static int opf( int x) { return u_field(x, 13, 5); }
duke@435	969
duke@435	970	static int opf_cc( CC c, bool useFloat ) { return u_field((useFloat ? 0 : 4) + c, 13, 11); }
duke@435	971	static int mov_cc( CC c, bool useFloat ) { return u_field(useFloat ? 0 : 1, 18, 18) | u_field(c, 12, 11); }
duke@435	972
duke@435	973	static int fd( FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 29, 25); };
duke@435	974	static int fs1(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 18, 14); };
duke@435	975	static int fs2(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 4, 0); };
duke@435	976
duke@435	977	// some float instructions use this encoding on the op3 field
duke@435	978	static int alt_op3(int op, FloatRegisterImpl::Width w) {
duke@435	979	int r;
duke@435	980	switch(w) {
duke@435	981	case FloatRegisterImpl::S: r = op + 0; break;
duke@435	982	case FloatRegisterImpl::D: r = op + 3; break;
duke@435	983	case FloatRegisterImpl::Q: r = op + 2; break;
duke@435	984	default: ShouldNotReachHere(); break;
duke@435	985	}
duke@435	986	return op3(r);
duke@435	987	}
duke@435	988
duke@435	989
duke@435	990	// compute inverse of simm
duke@435	991	static int inv_simm(int x, int nbits) {
duke@435	992	return (int)(x << (32 - nbits)) >> (32 - nbits);
duke@435	993	}
duke@435	994
duke@435	995	static int inv_simm13( int x ) { return inv_simm(x, 13); }
duke@435	996
duke@435	997	// signed immediate, in low bits, nbits long
duke@435	998	static int simm(int x, int nbits) {
duke@435	999	assert_signed_range(x, nbits);
duke@435	1000	return x & (( 1 << nbits ) - 1);
duke@435	1001	}
duke@435	1002
duke@435	1003	// compute inverse of wdisp16
duke@435	1004	static intptr_t inv_wdisp16(int x, intptr_t pos) {
duke@435	1005	int lo = x & (( 1 << 14 ) - 1);
duke@435	1006	int hi = (x >> 20) & 3;
duke@435	1007	if (hi >= 2) hi |= ~1;
duke@435	1008	return (((hi << 14) | lo) << 2) + pos;
duke@435	1009	}
duke@435	1010
duke@435	1011	// word offset, 14 bits at LSend, 2 bits at B21, B20
duke@435	1012	static int wdisp16(intptr_t x, intptr_t off) {
duke@435	1013	intptr_t xx = x - off;
duke@435	1014	assert_signed_word_disp_range(xx, 16);
duke@435	1015	int r = (xx >> 2) & ((1 << 14) - 1)
duke@435	1016	| ( ( (xx>>(2+14)) & 3 ) << 20 );
duke@435	1017	assert( inv_wdisp16(r, off) == x, "inverse is not inverse");
duke@435	1018	return r;
duke@435	1019	}
duke@435	1020
duke@435	1021
duke@435	1022	// word displacement in low-order nbits bits
duke@435	1023
duke@435	1024	static intptr_t inv_wdisp( int x, intptr_t pos, int nbits ) {
duke@435	1025	int pre_sign_extend = x & (( 1 << nbits ) - 1);
duke@435	1026	int r = pre_sign_extend >= ( 1 << (nbits-1) )
duke@435	1027	? pre_sign_extend | ~(( 1 << nbits ) - 1)
duke@435	1028	: pre_sign_extend;
duke@435	1029	return (r << 2) + pos;
duke@435	1030	}
duke@435	1031
duke@435	1032	static int wdisp( intptr_t x, intptr_t off, int nbits ) {
duke@435	1033	intptr_t xx = x - off;
duke@435	1034	assert_signed_word_disp_range(xx, nbits);
duke@435	1035	int r = (xx >> 2) & (( 1 << nbits ) - 1);
duke@435	1036	assert( inv_wdisp( r, off, nbits ) == x, "inverse not inverse");
duke@435	1037	return r;
duke@435	1038	}
duke@435	1039
duke@435	1040
duke@435	1041	// Extract the top 32 bits in a 64 bit word
duke@435	1042	static int32_t hi32( int64_t x ) {
duke@435	1043	int32_t r = int32_t( (uint64_t)x >> 32 );
duke@435	1044	return r;
duke@435	1045	}
duke@435	1046
duke@435	1047	// given a sethi instruction, extract the constant, left-justified
duke@435	1048	static int inv_hi22( int x ) {
duke@435	1049	return x << 10;
duke@435	1050	}
duke@435	1051
duke@435	1052	// create an imm22 field, given a 32-bit left-justified constant
duke@435	1053	static int hi22( int x ) {
duke@435	1054	int r = int( juint(x) >> 10 );
duke@435	1055	assert( (r & ~((1 << 22) - 1)) == 0, "just checkin'");
duke@435	1056	return r;
duke@435	1057	}
duke@435	1058
duke@435	1059	// create a low10 __value__ (not a field) for a given a 32-bit constant
duke@435	1060	static int low10( int x ) {
duke@435	1061	return x & ((1 << 10) - 1);
duke@435	1062	}
duke@435	1063
duke@435	1064	// instruction only in v9
duke@435	1065	static void v9_only() { assert( VM_Version::v9_instructions_work(), "This instruction only works on SPARC V9"); }
duke@435	1066
duke@435	1067	// instruction only in v8
duke@435	1068	static void v8_only() { assert( VM_Version::v8_instructions_work(), "This instruction only works on SPARC V8"); }
duke@435	1069
duke@435	1070	// instruction deprecated in v9
duke@435	1071	static void v9_dep() { } // do nothing for now
duke@435	1072
duke@435	1073	// some float instructions only exist for single prec. on v8
duke@435	1074	static void v8_s_only(FloatRegisterImpl::Width w) { if (w != FloatRegisterImpl::S) v9_only(); }
duke@435	1075
duke@435	1076	// v8 has no CC field
duke@435	1077	static void v8_no_cc(CC cc) { if (cc) v9_only(); }
duke@435	1078
duke@435	1079	protected:
duke@435	1080	// Simple delay-slot scheme:
duke@435	1081	// In order to check the programmer, the assembler keeps track of deley slots.
duke@435	1082	// It forbids CTIs in delay slots (conservative, but should be OK).
duke@435	1083	// Also, when putting an instruction into a delay slot, you must say
duke@435	1084	// asm->delayed()->add(...), in order to check that you don't omit
duke@435	1085	// delay-slot instructions.
duke@435	1086	// To implement this, we use a simple FSA
duke@435	1087
duke@435	1088	#ifdef ASSERT
duke@435	1089	#define CHECK_DELAY
duke@435	1090	#endif
duke@435	1091	#ifdef CHECK_DELAY
duke@435	1092	enum Delay_state { no_delay, at_delay_slot, filling_delay_slot } delay_state;
duke@435	1093	#endif
duke@435	1094
duke@435	1095	public:
duke@435	1096	// Tells assembler next instruction must NOT be in delay slot.
duke@435	1097	// Use at start of multinstruction macros.
duke@435	1098	void assert_not_delayed() {
duke@435	1099	// This is a separate overloading to avoid creation of string constants
duke@435	1100	// in non-asserted code--with some compilers this pollutes the object code.
duke@435	1101	#ifdef CHECK_DELAY
duke@435	1102	assert_not_delayed("next instruction should not be a delay slot");
duke@435	1103	#endif
duke@435	1104	}
duke@435	1105	void assert_not_delayed(const char* msg) {
duke@435	1106	#ifdef CHECK_DELAY
jcoomes@1845	1107	assert(delay_state == no_delay, msg);
duke@435	1108	#endif
duke@435	1109	}
duke@435	1110
duke@435	1111	protected:
duke@435	1112	// Delay slot helpers
duke@435	1113	// cti is called when emitting control-transfer instruction,
duke@435	1114	// BEFORE doing the emitting.
duke@435	1115	// Only effective when assertion-checking is enabled.
duke@435	1116	void cti() {
duke@435	1117	#ifdef CHECK_DELAY
duke@435	1118	assert_not_delayed("cti should not be in delay slot");
duke@435	1119	#endif
duke@435	1120	}
duke@435	1121
duke@435	1122	// called when emitting cti with a delay slot, AFTER emitting
duke@435	1123	void has_delay_slot() {
duke@435	1124	#ifdef CHECK_DELAY
duke@435	1125	assert_not_delayed("just checking");
duke@435	1126	delay_state = at_delay_slot;
duke@435	1127	#endif
duke@435	1128	}
duke@435	1129
duke@435	1130	public:
duke@435	1131	// Tells assembler you know that next instruction is delayed
duke@435	1132	Assembler* delayed() {
duke@435	1133	#ifdef CHECK_DELAY
duke@435	1134	assert ( delay_state == at_delay_slot, "delayed instruction is not in delay slot");
duke@435	1135	delay_state = filling_delay_slot;
duke@435	1136	#endif
duke@435	1137	return this;
duke@435	1138	}
duke@435	1139
duke@435	1140	void flush() {
duke@435	1141	#ifdef CHECK_DELAY
duke@435	1142	assert ( delay_state == no_delay, "ending code with a delay slot");
duke@435	1143	#endif
duke@435	1144	AbstractAssembler::flush();
duke@435	1145	}
duke@435	1146
duke@435	1147	inline void emit_long(int); // shadows AbstractAssembler::emit_long
duke@435	1148	inline void emit_data(int x) { emit_long(x); }
duke@435	1149	inline void emit_data(int, RelocationHolder const&);
duke@435	1150	inline void emit_data(int, relocInfo::relocType rtype);
duke@435	1151	// helper for above fcns
duke@435	1152	inline void check_delay();
duke@435	1153
duke@435	1154
duke@435	1155	public:
duke@435	1156	// instructions, refer to page numbers in the SPARC Architecture Manual, V9
duke@435	1157
duke@435	1158	// pp 135 (addc was addx in v8)
duke@435	1159
twisti@1162	1160	inline void add(Register s1, Register s2, Register d );
twisti@1162	1161	inline void add(Register s1, int simm13a, Register d, relocInfo::relocType rtype = relocInfo::none);
twisti@1162	1162	inline void add(Register s1, int simm13a, Register d, RelocationHolder const& rspec);
twisti@1162	1163	inline void add(Register s1, RegisterOrConstant s2, Register d, int offset = 0);
jrose@2266	1164	inline void add(const Address& a, Register d, int offset = 0);
duke@435	1165
duke@435	1166	void addcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(add_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
duke@435	1167	void addcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(add_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1168	void addc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 ) | rs1(s1) | rs2(s2) ); }
duke@435	1169	void addc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1170	void addccc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
duke@435	1171	void addccc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1172
duke@435	1173	// pp 136
duke@435	1174
duke@435	1175	inline void bpr( RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt = relocInfo::none );
duke@435	1176	inline void bpr( RCondition c, bool a, Predict p, Register s1, Label& L);
duke@435	1177
duke@435	1178	protected: // use MacroAssembler::br instead
duke@435	1179
duke@435	1180	// pp 138
duke@435	1181
duke@435	1182	inline void fb( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
duke@435	1183	inline void fb( Condition c, bool a, Label& L );
duke@435	1184
duke@435	1185	// pp 141
duke@435	1186
duke@435	1187	inline void fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
duke@435	1188	inline void fbp( Condition c, bool a, CC cc, Predict p, Label& L );
duke@435	1189
duke@435	1190	public:
duke@435	1191
duke@435	1192	// pp 144
duke@435	1193
duke@435	1194	inline void br( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
duke@435	1195	inline void br( Condition c, bool a, Label& L );
duke@435	1196
duke@435	1197	// pp 146
duke@435	1198
duke@435	1199	inline void bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
duke@435	1200	inline void bp( Condition c, bool a, CC cc, Predict p, Label& L );
duke@435	1201
duke@435	1202	// pp 121 (V8)
duke@435	1203
duke@435	1204	inline void cb( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
duke@435	1205	inline void cb( Condition c, bool a, Label& L );
duke@435	1206
duke@435	1207	// pp 149
duke@435	1208
duke@435	1209	inline void call( address d, relocInfo::relocType rt = relocInfo::runtime_call_type );
duke@435	1210	inline void call( Label& L, relocInfo::relocType rt = relocInfo::runtime_call_type );
duke@435	1211
duke@435	1212	// pp 150
duke@435	1213
duke@435	1214	// These instructions compare the contents of s2 with the contents of
duke@435	1215	// memory at address in s1. If the values are equal, the contents of memory
duke@435	1216	// at address s1 is swapped with the data in d. If the values are not equal,
duke@435	1217	// the the contents of memory at s1 is loaded into d, without the swap.
duke@435	1218
duke@435	1219	void casa( Register s1, Register s2, Register d, int ia = -1 ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(casa_op3 ) | rs1(s1) | (ia == -1 ? immed(true) : imm_asi(ia)) | rs2(s2)); }
duke@435	1220	void casxa( Register s1, Register s2, Register d, int ia = -1 ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(casxa_op3) | rs1(s1) | (ia == -1 ? immed(true) : imm_asi(ia)) | rs2(s2)); }
duke@435	1221
duke@435	1222	// pp 152
duke@435	1223
duke@435	1224	void udiv( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3 ) | rs1(s1) | rs2(s2)); }
duke@435	1225	void udiv( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1226	void sdiv( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sdiv_op3 ) | rs1(s1) | rs2(s2)); }
duke@435	1227	void sdiv( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sdiv_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1228	void udivcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); }
duke@435	1229	void udivcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1230	void sdivcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); }
duke@435	1231	void sdivcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1232
duke@435	1233	// pp 155
duke@435	1234
duke@435	1235	void done() { v9_only(); cti(); emit_long( op(arith_op) | fcn(0) | op3(done_op3) ); }
duke@435	1236	void retry() { v9_only(); cti(); emit_long( op(arith_op) | fcn(1) | op3(retry_op3) ); }
duke@435	1237
duke@435	1238	// pp 156
duke@435	1239
duke@435	1240	void fadd( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x40 + w) | fs2(s2, w)); }
duke@435	1241	void fsub( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x44 + w) | fs2(s2, w)); }
duke@435	1242
duke@435	1243	// pp 157
duke@435	1244
duke@435	1245	void fcmp( FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { v8_no_cc(cc); emit_long( op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x50 + w) | fs2(s2, w)); }
duke@435	1246	void fcmpe( FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { v8_no_cc(cc); emit_long( op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x54 + w) | fs2(s2, w)); }
duke@435	1247
duke@435	1248	// pp 159
duke@435	1249
duke@435	1250	void ftox( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only(); emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x80 + w) | fs2(s, w)); }
duke@435	1251	void ftoi( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0xd0 + w) | fs2(s, w)); }
duke@435	1252
duke@435	1253	// pp 160
duke@435	1254
duke@435	1255	void ftof( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s, FloatRegister d ) { emit_long( op(arith_op) | fd(d, dw) | op3(fpop1_op3) | opf(0xc0 + sw + dw*4) | fs2(s, sw)); }
duke@435	1256
duke@435	1257	// pp 161
duke@435	1258
duke@435	1259	void fxtof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only(); emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x80 + w*4) | fs2(s, w)); }
duke@435	1260	void fitof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0xc0 + w*4) | fs2(s, w)); }
duke@435	1261
duke@435	1262	// pp 162
duke@435	1263
duke@435	1264	void fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v8_s_only(w); emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x00 + w) | fs2(s, w)); }
duke@435	1265
duke@435	1266	void fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v8_s_only(w); emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x04 + w) | fs2(s, w)); }
duke@435	1267
duke@435	1268	// page 144 sparc v8 architecture (double prec works on v8 if the source and destination registers are the same). fnegs is the only instruction available
duke@435	1269	// on v8 to do negation of single, double and quad precision floats.
duke@435	1270
duke@435	1271	void fneg( FloatRegisterImpl::Width w, FloatRegister sd ) { if (VM_Version::v9_instructions_work()) emit_long( op(arith_op) | fd(sd, w) | op3(fpop1_op3) | opf(0x04 + w) | fs2(sd, w)); else emit_long( op(arith_op) | fd(sd, w) | op3(fpop1_op3) | opf(0x05) | fs2(sd, w)); }
duke@435	1272
duke@435	1273	void fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v8_s_only(w); emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x08 + w) | fs2(s, w)); }
duke@435	1274
duke@435	1275	// page 144 sparc v8 architecture (double prec works on v8 if the source and destination registers are the same). fabss is the only instruction available
duke@435	1276	// on v8 to do abs operation on single/double/quad precision floats.
duke@435	1277
duke@435	1278	void fabs( FloatRegisterImpl::Width w, FloatRegister sd ) { if (VM_Version::v9_instructions_work()) emit_long( op(arith_op) | fd(sd, w) | op3(fpop1_op3) | opf(0x08 + w) | fs2(sd, w)); else emit_long( op(arith_op) | fd(sd, w) | op3(fpop1_op3) | opf(0x09) | fs2(sd, w)); }
duke@435	1279
duke@435	1280	// pp 163
duke@435	1281
duke@435	1282	void fmul( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x48 + w) | fs2(s2, w)); }
duke@435	1283	void fmul( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_long( op(arith_op) | fd(d, dw) | op3(fpop1_op3) | fs1(s1, sw) | opf(0x60 + sw + dw*4) | fs2(s2, sw)); }
duke@435	1284	void fdiv( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x4c + w) | fs2(s2, w)); }
duke@435	1285
duke@435	1286	// pp 164
duke@435	1287
duke@435	1288	void fsqrt( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x28 + w) | fs2(s, w)); }
duke@435	1289
duke@435	1290	// pp 165
duke@435	1291
duke@435	1292	inline void flush( Register s1, Register s2 );
duke@435	1293	inline void flush( Register s1, int simm13a);
duke@435	1294
duke@435	1295	// pp 167
duke@435	1296
duke@435	1297	void flushw() { v9_only(); emit_long( op(arith_op) | op3(flushw_op3) ); }
duke@435	1298
duke@435	1299	// pp 168
duke@435	1300
duke@435	1301	void illtrap( int const22a) { if (const22a != 0) v9_only(); emit_long( op(branch_op) | u_field(const22a, 21, 0) ); }
duke@435	1302	// v8 unimp == illtrap(0)
duke@435	1303
duke@435	1304	// pp 169
duke@435	1305
duke@435	1306	void impdep1( int id1, int const19a ) { v9_only(); emit_long( op(arith_op) | fcn(id1) | op3(impdep1_op3) | u_field(const19a, 18, 0)); }
duke@435	1307	void impdep2( int id1, int const19a ) { v9_only(); emit_long( op(arith_op) | fcn(id1) | op3(impdep2_op3) | u_field(const19a, 18, 0)); }
duke@435	1308
duke@435	1309	// pp 149 (v8)
duke@435	1310
duke@435	1311	void cpop1( int opc, int cr1, int cr2, int crd ) { v8_only(); emit_long( op(arith_op) | fcn(crd) | op3(impdep1_op3) | u_field(cr1, 18, 14) | opf(opc) | u_field(cr2, 4, 0)); }
duke@435	1312	void cpop2( int opc, int cr1, int cr2, int crd ) { v8_only(); emit_long( op(arith_op) | fcn(crd) | op3(impdep2_op3) | u_field(cr1, 18, 14) | opf(opc) | u_field(cr2, 4, 0)); }
duke@435	1313
duke@435	1314	// pp 170
duke@435	1315
duke@435	1316	void jmpl( Register s1, Register s2, Register d );
duke@435	1317	void jmpl( Register s1, int simm13a, Register d, RelocationHolder const& rspec = RelocationHolder() );
duke@435	1318
duke@435	1319	// 171
duke@435	1320
twisti@1441	1321	inline void ldf(FloatRegisterImpl::Width w, Register s1, RegisterOrConstant s2, FloatRegister d);
twisti@1162	1322	inline void ldf(FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d);
twisti@1162	1323	inline void ldf(FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d, RelocationHolder const& rspec = RelocationHolder());
twisti@1162	1324
twisti@1162	1325	inline void ldf(FloatRegisterImpl::Width w, const Address& a, FloatRegister d, int offset = 0);
duke@435	1326
duke@435	1327
duke@435	1328	inline void ldfsr( Register s1, Register s2 );
duke@435	1329	inline void ldfsr( Register s1, int simm13a);
duke@435	1330	inline void ldxfsr( Register s1, Register s2 );
duke@435	1331	inline void ldxfsr( Register s1, int simm13a);
duke@435	1332
duke@435	1333	// pp 94 (v8)
duke@435	1334
duke@435	1335	inline void ldc( Register s1, Register s2, int crd );
duke@435	1336	inline void ldc( Register s1, int simm13a, int crd);
duke@435	1337	inline void lddc( Register s1, Register s2, int crd );
duke@435	1338	inline void lddc( Register s1, int simm13a, int crd);
duke@435	1339	inline void ldcsr( Register s1, Register s2, int crd );
duke@435	1340	inline void ldcsr( Register s1, int simm13a, int crd);
duke@435	1341
duke@435	1342
duke@435	1343	// 173
duke@435	1344
duke@435	1345	void ldfa( FloatRegisterImpl::Width w, Register s1, Register s2, int ia, FloatRegister d ) { v9_only(); emit_long( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
duke@435	1346	void ldfa( FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d ) { v9_only(); emit_long( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1347
duke@435	1348	// pp 175, lduw is ld on v8
duke@435	1349
duke@435	1350	inline void ldsb( Register s1, Register s2, Register d );
duke@435	1351	inline void ldsb( Register s1, int simm13a, Register d);
duke@435	1352	inline void ldsh( Register s1, Register s2, Register d );
duke@435	1353	inline void ldsh( Register s1, int simm13a, Register d);
duke@435	1354	inline void ldsw( Register s1, Register s2, Register d );
duke@435	1355	inline void ldsw( Register s1, int simm13a, Register d);
duke@435	1356	inline void ldub( Register s1, Register s2, Register d );
duke@435	1357	inline void ldub( Register s1, int simm13a, Register d);
duke@435	1358	inline void lduh( Register s1, Register s2, Register d );
duke@435	1359	inline void lduh( Register s1, int simm13a, Register d);
duke@435	1360	inline void lduw( Register s1, Register s2, Register d );
duke@435	1361	inline void lduw( Register s1, int simm13a, Register d);
duke@435	1362	inline void ldx( Register s1, Register s2, Register d );
duke@435	1363	inline void ldx( Register s1, int simm13a, Register d);
duke@435	1364	inline void ld( Register s1, Register s2, Register d );
duke@435	1365	inline void ld( Register s1, int simm13a, Register d);
duke@435	1366	inline void ldd( Register s1, Register s2, Register d );
duke@435	1367	inline void ldd( Register s1, int simm13a, Register d);
duke@435	1368
twisti@1162	1369	#ifdef ASSERT
twisti@1162	1370	// ByteSize is only a class when ASSERT is defined, otherwise it's an int.
twisti@1162	1371	inline void ld( Register s1, ByteSize simm13a, Register d);
twisti@1162	1372	#endif
twisti@1162	1373
twisti@1162	1374	inline void ldsb(const Address& a, Register d, int offset = 0);
twisti@1162	1375	inline void ldsh(const Address& a, Register d, int offset = 0);
twisti@1162	1376	inline void ldsw(const Address& a, Register d, int offset = 0);
twisti@1162	1377	inline void ldub(const Address& a, Register d, int offset = 0);
twisti@1162	1378	inline void lduh(const Address& a, Register d, int offset = 0);
twisti@1162	1379	inline void lduw(const Address& a, Register d, int offset = 0);
twisti@1162	1380	inline void ldx( const Address& a, Register d, int offset = 0);
twisti@1162	1381	inline void ld( const Address& a, Register d, int offset = 0);
twisti@1162	1382	inline void ldd( const Address& a, Register d, int offset = 0);
duke@435	1383
jrose@1100	1384	inline void ldub( Register s1, RegisterOrConstant s2, Register d );
jrose@1100	1385	inline void ldsb( Register s1, RegisterOrConstant s2, Register d );
jrose@1100	1386	inline void lduh( Register s1, RegisterOrConstant s2, Register d );
jrose@1100	1387	inline void ldsh( Register s1, RegisterOrConstant s2, Register d );
jrose@1100	1388	inline void lduw( Register s1, RegisterOrConstant s2, Register d );
jrose@1100	1389	inline void ldsw( Register s1, RegisterOrConstant s2, Register d );
jrose@1100	1390	inline void ldx( Register s1, RegisterOrConstant s2, Register d );
jrose@1100	1391	inline void ld( Register s1, RegisterOrConstant s2, Register d );
jrose@1100	1392	inline void ldd( Register s1, RegisterOrConstant s2, Register d );
jrose@1057	1393
duke@435	1394	// pp 177
duke@435	1395
duke@435	1396	void ldsba( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
duke@435	1397	void ldsba( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1398	void ldsha( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
duke@435	1399	void ldsha( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1400	void ldswa( Register s1, Register s2, int ia, Register d ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
duke@435	1401	void ldswa( Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1402	void lduba( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
duke@435	1403	void lduba( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1404	void lduha( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
duke@435	1405	void lduha( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1406	void lduwa( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
duke@435	1407	void lduwa( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1408	void ldxa( Register s1, Register s2, int ia, Register d ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(ldx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
duke@435	1409	void ldxa( Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(ldx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1410	void ldda( Register s1, Register s2, int ia, Register d ) { v9_dep(); emit_long( op(ldst_op) | rd(d) | op3(ldd_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
duke@435	1411	void ldda( Register s1, int simm13a, Register d ) { v9_dep(); emit_long( op(ldst_op) | rd(d) | op3(ldd_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1412
duke@435	1413	// pp 179
duke@435	1414
duke@435	1415	inline void ldstub( Register s1, Register s2, Register d );
duke@435	1416	inline void ldstub( Register s1, int simm13a, Register d);
duke@435	1417
duke@435	1418	// pp 180
duke@435	1419
duke@435	1420	void ldstuba( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldstub_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
duke@435	1421	void ldstuba( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldstub_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1422
duke@435	1423	// pp 181
duke@435	1424
twisti@1858	1425	void and3( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 ) | rs1(s1) | rs2(s2) ); }
twisti@1858	1426	void and3( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1427	void andcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
duke@435	1428	void andcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1429	void andn( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 ) | rs1(s1) | rs2(s2) ); }
duke@435	1430	void andn( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@1858	1431	void andn( Register s1, RegisterOrConstant s2, Register d);
duke@435	1432	void andncc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
duke@435	1433	void andncc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@1858	1434	void or3( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 ) | rs1(s1) | rs2(s2) ); }
twisti@1858	1435	void or3( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1436	void orcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
duke@435	1437	void orcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1438	void orn( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | rs2(s2) ); }
duke@435	1439	void orn( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1440	void orncc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
duke@435	1441	void orncc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@1858	1442	void xor3( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 ) | rs1(s1) | rs2(s2) ); }
twisti@1858	1443	void xor3( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1444	void xorcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
duke@435	1445	void xorcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1446	void xnor( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3 ) | rs1(s1) | rs2(s2) ); }
duke@435	1447	void xnor( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1448	void xnorcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
duke@435	1449	void xnorcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1450
duke@435	1451	// pp 183
duke@435	1452
duke@435	1453	void membar( Membar_mask_bits const7a ) { v9_only(); emit_long( op(arith_op) | op3(membar_op3) | rs1(O7) | immed(true) | u_field( int(const7a), 6, 0)); }
duke@435	1454
duke@435	1455	// pp 185
duke@435	1456
duke@435	1457	void fmov( FloatRegisterImpl::Width w, Condition c, bool floatCC, CC cca, FloatRegister s2, FloatRegister d ) { v9_only(); emit_long( op(arith_op) | fd(d, w) | op3(fpop2_op3) | cond_mov(c) | opf_cc(cca, floatCC) | opf_low6(w) | fs2(s2, w)); }
duke@435	1458
duke@435	1459	// pp 189
duke@435	1460
duke@435	1461	void fmov( FloatRegisterImpl::Width w, RCondition c, Register s1, FloatRegister s2, FloatRegister d ) { v9_only(); emit_long( op(arith_op) | fd(d, w) | op3(fpop2_op3) | rs1(s1) | rcond(c) | opf_low5(4 + w) | fs2(s2, w)); }
duke@435	1462
duke@435	1463	// pp 191
duke@435	1464
duke@435	1465	void movcc( Condition c, bool floatCC, CC cca, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(movcc_op3) | mov_cc(cca, floatCC) | cond_mov(c) | rs2(s2) ); }
duke@435	1466	void movcc( Condition c, bool floatCC, CC cca, int simm11a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(movcc_op3) | mov_cc(cca, floatCC) | cond_mov(c) | immed(true) | simm(simm11a, 11) ); }
duke@435	1467
duke@435	1468	// pp 195
duke@435	1469
duke@435	1470	void movr( RCondition c, Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(movr_op3) | rs1(s1) | rcond(c) | rs2(s2) ); }
duke@435	1471	void movr( RCondition c, Register s1, int simm10a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(movr_op3) | rs1(s1) | rcond(c) | immed(true) | simm(simm10a, 10) ); }
duke@435	1472
duke@435	1473	// pp 196
duke@435	1474
duke@435	1475	void mulx( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(mulx_op3 ) | rs1(s1) | rs2(s2) ); }
duke@435	1476	void mulx( Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(mulx_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1477	void sdivx( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | rs2(s2) ); }
duke@435	1478	void sdivx( Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1479	void udivx( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | rs2(s2) ); }
duke@435	1480	void udivx( Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1481
duke@435	1482	// pp 197
duke@435	1483
duke@435	1484	void umul( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(umul_op3 ) | rs1(s1) | rs2(s2) ); }
duke@435	1485	void umul( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(umul_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1486	void smul( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(smul_op3 ) | rs1(s1) | rs2(s2) ); }
duke@435	1487	void smul( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(smul_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1488	void umulcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
duke@435	1489	void umulcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1490	void smulcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
duke@435	1491	void smulcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1492
duke@435	1493	// pp 199
duke@435	1494
duke@435	1495	void mulscc( Register s1, Register s2, Register d ) { v9_dep(); emit_long( op(arith_op) | rd(d) | op3(mulscc_op3) | rs1(s1) | rs2(s2) ); }
duke@435	1496	void mulscc( Register s1, int simm13a, Register d ) { v9_dep(); emit_long( op(arith_op) | rd(d) | op3(mulscc_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1497
duke@435	1498	// pp 201
duke@435	1499
duke@435	1500	void nop() { emit_long( op(branch_op) | op2(sethi_op2) ); }
duke@435	1501
duke@435	1502
duke@435	1503	// pp 202
duke@435	1504
duke@435	1505	void popc( Register s, Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(popc_op3) | rs2(s)); }
duke@435	1506	void popc( int simm13a, Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(popc_op3) | immed(true) | simm(simm13a, 13)); }
duke@435	1507
duke@435	1508	// pp 203
duke@435	1509
duke@435	1510	void prefetch( Register s1, Register s2, PrefetchFcn f);
duke@435	1511	void prefetch( Register s1, int simm13a, PrefetchFcn f);
duke@435	1512	void prefetcha( Register s1, Register s2, int ia, PrefetchFcn f ) { v9_only(); emit_long( op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
duke@435	1513	void prefetcha( Register s1, int simm13a, PrefetchFcn f ) { v9_only(); emit_long( op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1514
duke@435	1515	inline void prefetch(const Address& a, PrefetchFcn F, int offset = 0);
duke@435	1516
duke@435	1517	// pp 208
duke@435	1518
duke@435	1519	// not implementing read privileged register
duke@435	1520
duke@435	1521	inline void rdy( Register d) { v9_dep(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(0, 18, 14)); }
duke@435	1522	inline void rdccr( Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(2, 18, 14)); }
duke@435	1523	inline void rdasi( Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(3, 18, 14)); }
duke@435	1524	inline void rdtick( Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(4, 18, 14)); } // Spoon!
duke@435	1525	inline void rdpc( Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(5, 18, 14)); }
duke@435	1526	inline void rdfprs( Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(6, 18, 14)); }
duke@435	1527
duke@435	1528	// pp 213
duke@435	1529
duke@435	1530	inline void rett( Register s1, Register s2);
duke@435	1531	inline void rett( Register s1, int simm13a, relocInfo::relocType rt = relocInfo::none);
duke@435	1532
duke@435	1533	// pp 214
duke@435	1534
duke@435	1535	void save( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(save_op3) | rs1(s1) | rs2(s2) ); }
ysr@777	1536	void save( Register s1, int simm13a, Register d ) {
ysr@777	1537	// make sure frame is at least large enough for the register save area
ysr@777	1538	assert(-simm13a >= 16 * wordSize, "frame too small");
ysr@777	1539	emit_long( op(arith_op) | rd(d) | op3(save_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) );
ysr@777	1540	}
duke@435	1541
duke@435	1542	void restore( Register s1 = G0, Register s2 = G0, Register d = G0 ) { emit_long( op(arith_op) | rd(d) | op3(restore_op3) | rs1(s1) | rs2(s2) ); }
duke@435	1543	void restore( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(restore_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1544
duke@435	1545	// pp 216
duke@435	1546
duke@435	1547	void saved() { v9_only(); emit_long( op(arith_op) | fcn(0) | op3(saved_op3)); }
duke@435	1548	void restored() { v9_only(); emit_long( op(arith_op) | fcn(1) | op3(saved_op3)); }
duke@435	1549
duke@435	1550	// pp 217
duke@435	1551
duke@435	1552	inline void sethi( int imm22a, Register d, RelocationHolder const& rspec = RelocationHolder() );
duke@435	1553	// pp 218
duke@435	1554
duke@435	1555	void sll( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(0) | rs2(s2) ); }
duke@435	1556	void sll( Register s1, int imm5a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); }
duke@435	1557	void srl( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(0) | rs2(s2) ); }
duke@435	1558	void srl( Register s1, int imm5a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); }
duke@435	1559	void sra( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(0) | rs2(s2) ); }
duke@435	1560	void sra( Register s1, int imm5a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); }
duke@435	1561
duke@435	1562	void sllx( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(1) | rs2(s2) ); }
duke@435	1563	void sllx( Register s1, int imm6a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); }
duke@435	1564	void srlx( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(1) | rs2(s2) ); }
duke@435	1565	void srlx( Register s1, int imm6a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); }
duke@435	1566	void srax( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(1) | rs2(s2) ); }
duke@435	1567	void srax( Register s1, int imm6a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); }
duke@435	1568
duke@435	1569	// pp 220
duke@435	1570
duke@435	1571	void sir( int simm13a ) { emit_long( op(arith_op) | fcn(15) | op3(sir_op3) | immed(true) | simm(simm13a, 13)); }
duke@435	1572
duke@435	1573	// pp 221
duke@435	1574
duke@435	1575	void stbar() { emit_long( op(arith_op) | op3(membar_op3) | u_field(15, 18, 14)); }
duke@435	1576
duke@435	1577	// pp 222
duke@435	1578
twisti@1441	1579	inline void stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, RegisterOrConstant s2);
twisti@1441	1580	inline void stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2);
duke@435	1581	inline void stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a);
duke@435	1582	inline void stf( FloatRegisterImpl::Width w, FloatRegister d, const Address& a, int offset = 0);
duke@435	1583
duke@435	1584	inline void stfsr( Register s1, Register s2 );
duke@435	1585	inline void stfsr( Register s1, int simm13a);
duke@435	1586	inline void stxfsr( Register s1, Register s2 );
duke@435	1587	inline void stxfsr( Register s1, int simm13a);
duke@435	1588
duke@435	1589	// pp 224
duke@435	1590
duke@435	1591	void stfa( FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2, int ia ) { v9_only(); emit_long( op(ldst_op) | fd(d, w) | alt_op3(stf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
duke@435	1592	void stfa( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a ) { v9_only(); emit_long( op(ldst_op) | fd(d, w) | alt_op3(stf_op3 | alt_bit_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1593
duke@435	1594	// p 226
duke@435	1595
duke@435	1596	inline void stb( Register d, Register s1, Register s2 );
duke@435	1597	inline void stb( Register d, Register s1, int simm13a);
duke@435	1598	inline void sth( Register d, Register s1, Register s2 );
duke@435	1599	inline void sth( Register d, Register s1, int simm13a);
duke@435	1600	inline void stw( Register d, Register s1, Register s2 );
duke@435	1601	inline void stw( Register d, Register s1, int simm13a);
duke@435	1602	inline void st( Register d, Register s1, Register s2 );
duke@435	1603	inline void st( Register d, Register s1, int simm13a);
duke@435	1604	inline void stx( Register d, Register s1, Register s2 );
duke@435	1605	inline void stx( Register d, Register s1, int simm13a);
duke@435	1606	inline void std( Register d, Register s1, Register s2 );
duke@435	1607	inline void std( Register d, Register s1, int simm13a);
duke@435	1608
twisti@1162	1609	#ifdef ASSERT
twisti@1162	1610	// ByteSize is only a class when ASSERT is defined, otherwise it's an int.
twisti@1162	1611	inline void st( Register d, Register s1, ByteSize simm13a);
twisti@1162	1612	#endif
twisti@1162	1613
duke@435	1614	inline void stb( Register d, const Address& a, int offset = 0 );
duke@435	1615	inline void sth( Register d, const Address& a, int offset = 0 );
duke@435	1616	inline void stw( Register d, const Address& a, int offset = 0 );
duke@435	1617	inline void stx( Register d, const Address& a, int offset = 0 );
duke@435	1618	inline void st( Register d, const Address& a, int offset = 0 );
duke@435	1619	inline void std( Register d, const Address& a, int offset = 0 );
duke@435	1620
jrose@1100	1621	inline void stb( Register d, Register s1, RegisterOrConstant s2 );
jrose@1100	1622	inline void sth( Register d, Register s1, RegisterOrConstant s2 );
jrose@1100	1623	inline void stw( Register d, Register s1, RegisterOrConstant s2 );
jrose@1100	1624	inline void stx( Register d, Register s1, RegisterOrConstant s2 );
jrose@1100	1625	inline void std( Register d, Register s1, RegisterOrConstant s2 );
jrose@1100	1626	inline void st( Register d, Register s1, RegisterOrConstant s2 );
jrose@1057	1627
duke@435	1628	// pp 177
duke@435	1629
duke@435	1630	void stba( Register d, Register s1, Register s2, int ia ) { emit_long( op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
duke@435	1631	void stba( Register d, Register s1, int simm13a ) { emit_long( op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1632	void stha( Register d, Register s1, Register s2, int ia ) { emit_long( op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
duke@435	1633	void stha( Register d, Register s1, int simm13a ) { emit_long( op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1634	void stwa( Register d, Register s1, Register s2, int ia ) { emit_long( op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
duke@435	1635	void stwa( Register d, Register s1, int simm13a ) { emit_long( op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1636	void stxa( Register d, Register s1, Register s2, int ia ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
duke@435	1637	void stxa( Register d, Register s1, int simm13a ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1638	void stda( Register d, Register s1, Register s2, int ia ) { emit_long( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
duke@435	1639	void stda( Register d, Register s1, int simm13a ) { emit_long( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1640
duke@435	1641	// pp 97 (v8)
duke@435	1642
duke@435	1643	inline void stc( int crd, Register s1, Register s2 );
duke@435	1644	inline void stc( int crd, Register s1, int simm13a);
duke@435	1645	inline void stdc( int crd, Register s1, Register s2 );
duke@435	1646	inline void stdc( int crd, Register s1, int simm13a);
duke@435	1647	inline void stcsr( int crd, Register s1, Register s2 );
duke@435	1648	inline void stcsr( int crd, Register s1, int simm13a);
duke@435	1649	inline void stdcq( int crd, Register s1, Register s2 );
duke@435	1650	inline void stdcq( int crd, Register s1, int simm13a);
duke@435	1651
duke@435	1652	// pp 230
duke@435	1653
duke@435	1654	void sub( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 ) | rs1(s1) | rs2(s2) ); }
duke@435	1655	void sub( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@2350	1656
twisti@2350	1657	// Note: offset is added to s2.
twisti@2350	1658	inline void sub(Register s1, RegisterOrConstant s2, Register d, int offset = 0);
twisti@2350	1659
duke@435	1660	void subcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | rs2(s2) ); }
duke@435	1661	void subcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1662	void subc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3 ) | rs1(s1) | rs2(s2) ); }
duke@435	1663	void subc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1664	void subccc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
duke@435	1665	void subccc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1666
duke@435	1667	// pp 231
duke@435	1668
duke@435	1669	inline void swap( Register s1, Register s2, Register d );
duke@435	1670	inline void swap( Register s1, int simm13a, Register d);
duke@435	1671	inline void swap( Address& a, Register d, int offset = 0 );
duke@435	1672
duke@435	1673	// pp 232
duke@435	1674
duke@435	1675	void swapa( Register s1, Register s2, int ia, Register d ) { v9_dep(); emit_long( op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
duke@435	1676	void swapa( Register s1, int simm13a, Register d ) { v9_dep(); emit_long( op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1677
duke@435	1678	// pp 234, note op in book is wrong, see pp 268
duke@435	1679
duke@435	1680	void taddcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(taddcc_op3 ) | rs1(s1) | rs2(s2) ); }
duke@435	1681	void taddcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(taddcc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1682	void taddcctv( Register s1, Register s2, Register d ) { v9_dep(); emit_long( op(arith_op) | rd(d) | op3(taddcctv_op3) | rs1(s1) | rs2(s2) ); }
duke@435	1683	void taddcctv( Register s1, int simm13a, Register d ) { v9_dep(); emit_long( op(arith_op) | rd(d) | op3(taddcctv_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1684
duke@435	1685	// pp 235
duke@435	1686
duke@435	1687	void tsubcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(tsubcc_op3 ) | rs1(s1) | rs2(s2) ); }
duke@435	1688	void tsubcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(tsubcc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1689	void tsubcctv( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(tsubcctv_op3) | rs1(s1) | rs2(s2) ); }
duke@435	1690	void tsubcctv( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(tsubcctv_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1691
duke@435	1692	// pp 237
duke@435	1693
duke@435	1694	void trap( Condition c, CC cc, Register s1, Register s2 ) { v8_no_cc(cc); emit_long( op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | rs2(s2)); }
duke@435	1695	void trap( Condition c, CC cc, Register s1, int trapa ) { v8_no_cc(cc); emit_long( op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | immed(true) | u_field(trapa, 6, 0)); }
duke@435	1696	// simple uncond. trap
duke@435	1697	void trap( int trapa ) { trap( always, icc, G0, trapa ); }
duke@435	1698
duke@435	1699	// pp 239 omit write priv register for now
duke@435	1700
duke@435	1701	inline void wry( Register d) { v9_dep(); emit_long( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(0, 29, 25)); }
duke@435	1702	inline void wrccr(Register s) { v9_only(); emit_long( op(arith_op) | rs1(s) | op3(wrreg_op3) | u_field(2, 29, 25)); }
duke@435	1703	inline void wrccr(Register s, int simm13a) { v9_only(); emit_long( op(arith_op) |
duke@435	1704	rs1(s) |
duke@435	1705	op3(wrreg_op3) |
duke@435	1706	u_field(2, 29, 25) |
duke@435	1707	u_field(1, 13, 13) |
duke@435	1708	simm(simm13a, 13)); }
duke@435	1709	inline void wrasi( Register d) { v9_only(); emit_long( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(3, 29, 25)); }
duke@435	1710	inline void wrfprs( Register d) { v9_only(); emit_long( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(6, 29, 25)); }
duke@435	1711
ysr@777	1712	// For a given register condition, return the appropriate condition code
ysr@777	1713	// Condition (the one you would use to get the same effect after "tst" on
ysr@777	1714	// the target register.)
ysr@777	1715	Assembler::Condition reg_cond_to_cc_cond(RCondition in);
ysr@777	1716
duke@435	1717
duke@435	1718	// Creation
duke@435	1719	Assembler(CodeBuffer* code) : AbstractAssembler(code) {
duke@435	1720	#ifdef CHECK_DELAY
duke@435	1721	delay_state = no_delay;
duke@435	1722	#endif
duke@435	1723	}
duke@435	1724
duke@435	1725	// Testing
duke@435	1726	#ifndef PRODUCT
duke@435	1727	void test_v9();
duke@435	1728	void test_v8_onlys();
duke@435	1729	#endif
duke@435	1730	};
duke@435	1731
duke@435	1732
duke@435	1733	class RegistersForDebugging : public StackObj {
duke@435	1734	public:
duke@435	1735	intptr_t i[8], l[8], o[8], g[8];
duke@435	1736	float f[32];
duke@435	1737	double d[32];
duke@435	1738
duke@435	1739	void print(outputStream* s);
duke@435	1740
duke@435	1741	static int i_offset(int j) { return offset_of(RegistersForDebugging, i[j]); }
duke@435	1742	static int l_offset(int j) { return offset_of(RegistersForDebugging, l[j]); }
duke@435	1743	static int o_offset(int j) { return offset_of(RegistersForDebugging, o[j]); }
duke@435	1744	static int g_offset(int j) { return offset_of(RegistersForDebugging, g[j]); }
duke@435	1745	static int f_offset(int j) { return offset_of(RegistersForDebugging, f[j]); }
duke@435	1746	static int d_offset(int j) { return offset_of(RegistersForDebugging, d[j / 2]); }
duke@435	1747
duke@435	1748	// gen asm code to save regs
duke@435	1749	static void save_registers(MacroAssembler* a);
duke@435	1750
duke@435	1751	// restore global registers in case C code disturbed them
duke@435	1752	static void restore_registers(MacroAssembler* a, Register r);
ysr@777	1753
ysr@777	1754
duke@435	1755	};
duke@435	1756
duke@435	1757
duke@435	1758	// MacroAssembler extends Assembler by a few frequently used macros.
duke@435	1759	//
duke@435	1760	// Most of the standard SPARC synthetic ops are defined here.
duke@435	1761	// Instructions for which a 'better' code sequence exists depending
duke@435	1762	// on arguments should also go in here.
duke@435	1763
duke@435	1764	#define JMP2(r1, r2) jmp(r1, r2, __FILE__, __LINE__)
duke@435	1765	#define JMP(r1, off) jmp(r1, off, __FILE__, __LINE__)
twisti@1162	1766	#define JUMP(a, temp, off) jump(a, temp, off, __FILE__, __LINE__)
twisti@1162	1767	#define JUMPL(a, temp, d, off) jumpl(a, temp, d, off, __FILE__, __LINE__)
duke@435	1768
duke@435	1769
duke@435	1770	class MacroAssembler: public Assembler {
duke@435	1771	protected:
duke@435	1772	// Support for VM calls
duke@435	1773	// This is the base routine called by the different versions of call_VM_leaf. The interpreter
duke@435	1774	// may customize this version by overriding it for its purposes (e.g., to save/restore
duke@435	1775	// additional registers when doing a VM call).
duke@435	1776	#ifdef CC_INTERP
duke@435	1777	#define VIRTUAL
duke@435	1778	#else
duke@435	1779	#define VIRTUAL virtual
duke@435	1780	#endif
duke@435	1781
duke@435	1782	VIRTUAL void call_VM_leaf_base(Register thread_cache, address entry_point, int number_of_arguments);
duke@435	1783
duke@435	1784	//
duke@435	1785	// It is imperative that all calls into the VM are handled via the call_VM macros.
duke@435	1786	// They make sure that the stack linkage is setup correctly. call_VM's correspond
duke@435	1787	// to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
duke@435	1788	//
duke@435	1789	// This is the base routine called by the different versions of call_VM. The interpreter
duke@435	1790	// may customize this version by overriding it for its purposes (e.g., to save/restore
duke@435	1791	// additional registers when doing a VM call).
duke@435	1792	//
duke@435	1793	// A non-volatile java_thread_cache register should be specified so
duke@435	1794	// that the G2_thread value can be preserved across the call.
duke@435	1795	// (If java_thread_cache is noreg, then a slow get_thread call
duke@435	1796	// will re-initialize the G2_thread.) call_VM_base returns the register that contains the
duke@435	1797	// thread.
duke@435	1798	//
duke@435	1799	// If no last_java_sp is specified (noreg) than SP will be used instead.
duke@435	1800
duke@435	1801	virtual void call_VM_base(
duke@435	1802	Register oop_result, // where an oop-result ends up if any; use noreg otherwise
duke@435	1803	Register java_thread_cache, // the thread if computed before ; use noreg otherwise
duke@435	1804	Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
duke@435	1805	address entry_point, // the entry point
duke@435	1806	int number_of_arguments, // the number of arguments (w/o thread) to pop after call
duke@435	1807	bool check_exception=true // flag which indicates if exception should be checked
duke@435	1808	);
duke@435	1809
duke@435	1810	// This routine should emit JVMTI PopFrame and ForceEarlyReturn handling code.
duke@435	1811	// The implementation is only non-empty for the InterpreterMacroAssembler,
duke@435	1812	// as only the interpreter handles and ForceEarlyReturn PopFrame requests.
duke@435	1813	virtual void check_and_handle_popframe(Register scratch_reg);
duke@435	1814	virtual void check_and_handle_earlyret(Register scratch_reg);
duke@435	1815
duke@435	1816	public:
duke@435	1817	MacroAssembler(CodeBuffer* code) : Assembler(code) {}
duke@435	1818
duke@435	1819	// Support for NULL-checks
duke@435	1820	//
duke@435	1821	// Generates code that causes a NULL OS exception if the content of reg is NULL.
duke@435	1822	// If the accessed location is M[reg + offset] and the offset is known, provide the
duke@435	1823	// offset. No explicit code generation is needed if the offset is within a certain
duke@435	1824	// range (0 <= offset <= page_size).
duke@435	1825	//
duke@435	1826	// %%%%%% Currently not done for SPARC
duke@435	1827
duke@435	1828	void null_check(Register reg, int offset = -1);
duke@435	1829	static bool needs_explicit_null_check(intptr_t offset);
duke@435	1830
duke@435	1831	// support for delayed instructions
duke@435	1832	MacroAssembler* delayed() { Assembler::delayed(); return this; }
duke@435	1833
duke@435	1834	// branches that use right instruction for v8 vs. v9
duke@435	1835	inline void br( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
duke@435	1836	inline void br( Condition c, bool a, Predict p, Label& L );
iveresov@2344	1837
duke@435	1838	inline void fb( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
duke@435	1839	inline void fb( Condition c, bool a, Predict p, Label& L );
duke@435	1840
duke@435	1841	// compares register with zero and branches (V9 and V8 instructions)
duke@435	1842	void br_zero( Condition c, bool a, Predict p, Register s1, Label& L);
duke@435	1843	// Compares a pointer register with zero and branches on (not)null.
duke@435	1844	// Does a test & branch on 32-bit systems and a register-branch on 64-bit.
duke@435	1845	void br_null ( Register s1, bool a, Predict p, Label& L );
duke@435	1846	void br_notnull( Register s1, bool a, Predict p, Label& L );
duke@435	1847
ysr@777	1848	// These versions will do the most efficient thing on v8 and v9. Perhaps
ysr@777	1849	// this is what the routine above was meant to do, but it didn't (and
ysr@777	1850	// didn't cover both target address kinds.)
ysr@777	1851	void br_on_reg_cond( RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt = relocInfo::none );
ysr@777	1852	void br_on_reg_cond( RCondition c, bool a, Predict p, Register s1, Label& L);
ysr@777	1853
duke@435	1854	inline void bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
duke@435	1855	inline void bp( Condition c, bool a, CC cc, Predict p, Label& L );
duke@435	1856
duke@435	1857	// Branch that tests xcc in LP64 and icc in !LP64
duke@435	1858	inline void brx( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
duke@435	1859	inline void brx( Condition c, bool a, Predict p, Label& L );
duke@435	1860
duke@435	1861	// unconditional short branch
duke@435	1862	inline void ba( bool a, Label& L );
duke@435	1863
duke@435	1864	// Branch that tests fp condition codes
duke@435	1865	inline void fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
duke@435	1866	inline void fbp( Condition c, bool a, CC cc, Predict p, Label& L );
duke@435	1867
duke@435	1868	// get PC the best way
duke@435	1869	inline int get_pc( Register d );
duke@435	1870
duke@435	1871	// Sparc shorthands(pp 85, V8 manual, pp 289 V9 manual)
duke@435	1872	inline void cmp( Register s1, Register s2 ) { subcc( s1, s2, G0 ); }
duke@435	1873	inline void cmp( Register s1, int simm13a ) { subcc( s1, simm13a, G0 ); }
duke@435	1874
duke@435	1875	inline void jmp( Register s1, Register s2 );
duke@435	1876	inline void jmp( Register s1, int simm13a, RelocationHolder const& rspec = RelocationHolder() );
duke@435	1877
iveresov@2441	1878	// Check if the call target is out of wdisp30 range (relative to the code cache)
iveresov@2441	1879	static inline bool is_far_target(address d);
duke@435	1880	inline void call( address d, relocInfo::relocType rt = relocInfo::runtime_call_type );
duke@435	1881	inline void call( Label& L, relocInfo::relocType rt = relocInfo::runtime_call_type );
duke@435	1882	inline void callr( Register s1, Register s2 );
duke@435	1883	inline void callr( Register s1, int simm13a, RelocationHolder const& rspec = RelocationHolder() );
duke@435	1884
duke@435	1885	// Emits nothing on V8
duke@435	1886	inline void iprefetch( address d, relocInfo::relocType rt = relocInfo::none );
duke@435	1887	inline void iprefetch( Label& L);
duke@435	1888
duke@435	1889	inline void tst( Register s ) { orcc( G0, s, G0 ); }
duke@435	1890
duke@435	1891	#ifdef PRODUCT
duke@435	1892	inline void ret( bool trace = TraceJumps ) { if (trace) {
duke@435	1893	mov(I7, O7); // traceable register
duke@435	1894	JMP(O7, 2 * BytesPerInstWord);
duke@435	1895	} else {
duke@435	1896	jmpl( I7, 2 * BytesPerInstWord, G0 );
duke@435	1897	}
duke@435	1898	}
duke@435	1899
duke@435	1900	inline void retl( bool trace = TraceJumps ) { if (trace) JMP(O7, 2 * BytesPerInstWord);
duke@435	1901	else jmpl( O7, 2 * BytesPerInstWord, G0 ); }
duke@435	1902	#else
duke@435	1903	void ret( bool trace = TraceJumps );
duke@435	1904	void retl( bool trace = TraceJumps );
duke@435	1905	#endif /* PRODUCT */
duke@435	1906
duke@435	1907	// Required platform-specific helpers for Label::patch_instructions.
duke@435	1908	// They _shadow_ the declarations in AbstractAssembler, which are undefined.
duke@435	1909	void pd_patch_instruction(address branch, address target);
duke@435	1910	#ifndef PRODUCT
duke@435	1911	static void pd_print_patched_instruction(address branch);
duke@435	1912	#endif
duke@435	1913
duke@435	1914	// sethi Macro handles optimizations and relocations
twisti@1162	1915	private:
twisti@1162	1916	void internal_sethi(const AddressLiteral& addrlit, Register d, bool ForceRelocatable);
twisti@1162	1917	public:
twisti@1162	1918	void sethi(const AddressLiteral& addrlit, Register d);
twisti@1162	1919	void patchable_sethi(const AddressLiteral& addrlit, Register d);
duke@435	1920
twisti@2399	1921	// compute the number of instructions for a sethi/set
twisti@2399	1922	static int insts_for_sethi( address a, bool worst_case = false );
twisti@2399	1923	static int worst_case_insts_for_set();
duke@435	1924
duke@435	1925	// set may be either setsw or setuw (high 32 bits may be zero or sign)
twisti@1162	1926	private:
twisti@1162	1927	void internal_set(const AddressLiteral& al, Register d, bool ForceRelocatable);
twisti@2399	1928	static int insts_for_internal_set(intptr_t value);
twisti@1162	1929	public:
twisti@1162	1930	void set(const AddressLiteral& addrlit, Register d);
twisti@1162	1931	void set(intptr_t value, Register d);
twisti@1162	1932	void set(address addr, Register d, RelocationHolder const& rspec);
twisti@2399	1933	static int insts_for_set(intptr_t value) { return insts_for_internal_set(value); }
twisti@2399	1934
twisti@1162	1935	void patchable_set(const AddressLiteral& addrlit, Register d);
twisti@1162	1936	void patchable_set(intptr_t value, Register d);
twisti@1162	1937	void set64(jlong value, Register d, Register tmp);
twisti@2399	1938	static int insts_for_set64(jlong value);
twisti@2350	1939
duke@435	1940	// sign-extend 32 to 64
duke@435	1941	inline void signx( Register s, Register d ) { sra( s, G0, d); }
duke@435	1942	inline void signx( Register d ) { sra( d, G0, d); }
duke@435	1943
duke@435	1944	inline void not1( Register s, Register d ) { xnor( s, G0, d ); }
duke@435	1945	inline void not1( Register d ) { xnor( d, G0, d ); }
duke@435	1946
duke@435	1947	inline void neg( Register s, Register d ) { sub( G0, s, d ); }
duke@435	1948	inline void neg( Register d ) { sub( G0, d, d ); }
duke@435	1949
duke@435	1950	inline void cas( Register s1, Register s2, Register d) { casa( s1, s2, d, ASI_PRIMARY); }
duke@435	1951	inline void casx( Register s1, Register s2, Register d) { casxa(s1, s2, d, ASI_PRIMARY); }
duke@435	1952	// Functions for isolating 64 bit atomic swaps for LP64
duke@435	1953	// cas_ptr will perform cas for 32 bit VM's and casx for 64 bit VM's
duke@435	1954	inline void cas_ptr( Register s1, Register s2, Register d) {
duke@435	1955	#ifdef _LP64
duke@435	1956	casx( s1, s2, d );
duke@435	1957	#else
duke@435	1958	cas( s1, s2, d );
duke@435	1959	#endif
duke@435	1960	}
duke@435	1961
duke@435	1962	// Functions for isolating 64 bit shifts for LP64
duke@435	1963	inline void sll_ptr( Register s1, Register s2, Register d );
duke@435	1964	inline void sll_ptr( Register s1, int imm6a, Register d );
jrose@1100	1965	inline void sll_ptr( Register s1, RegisterOrConstant s2, Register d );
duke@435	1966	inline void srl_ptr( Register s1, Register s2, Register d );
duke@435	1967	inline void srl_ptr( Register s1, int imm6a, Register d );
duke@435	1968
duke@435	1969	// little-endian
duke@435	1970	inline void casl( Register s1, Register s2, Register d) { casa( s1, s2, d, ASI_PRIMARY_LITTLE); }
duke@435	1971	inline void casxl( Register s1, Register s2, Register d) { casxa(s1, s2, d, ASI_PRIMARY_LITTLE); }
duke@435	1972
duke@435	1973	inline void inc( Register d, int const13 = 1 ) { add( d, const13, d); }
duke@435	1974	inline void inccc( Register d, int const13 = 1 ) { addcc( d, const13, d); }
duke@435	1975
duke@435	1976	inline void dec( Register d, int const13 = 1 ) { sub( d, const13, d); }
duke@435	1977	inline void deccc( Register d, int const13 = 1 ) { subcc( d, const13, d); }
duke@435	1978
duke@435	1979	inline void btst( Register s1, Register s2 ) { andcc( s1, s2, G0 ); }
duke@435	1980	inline void btst( int simm13a, Register s ) { andcc( s, simm13a, G0 ); }
duke@435	1981
duke@435	1982	inline void bset( Register s1, Register s2 ) { or3( s1, s2, s2 ); }
duke@435	1983	inline void bset( int simm13a, Register s ) { or3( s, simm13a, s ); }
duke@435	1984
duke@435	1985	inline void bclr( Register s1, Register s2 ) { andn( s1, s2, s2 ); }
duke@435	1986	inline void bclr( int simm13a, Register s ) { andn( s, simm13a, s ); }
duke@435	1987
duke@435	1988	inline void btog( Register s1, Register s2 ) { xor3( s1, s2, s2 ); }
duke@435	1989	inline void btog( int simm13a, Register s ) { xor3( s, simm13a, s ); }
duke@435	1990
duke@435	1991	inline void clr( Register d ) { or3( G0, G0, d ); }
duke@435	1992
duke@435	1993	inline void clrb( Register s1, Register s2);
duke@435	1994	inline void clrh( Register s1, Register s2);
duke@435	1995	inline void clr( Register s1, Register s2);
duke@435	1996	inline void clrx( Register s1, Register s2);
duke@435	1997
duke@435	1998	inline void clrb( Register s1, int simm13a);
duke@435	1999	inline void clrh( Register s1, int simm13a);
duke@435	2000	inline void clr( Register s1, int simm13a);
duke@435	2001	inline void clrx( Register s1, int simm13a);
duke@435	2002
duke@435	2003	// copy & clear upper word
duke@435	2004	inline void clruw( Register s, Register d ) { srl( s, G0, d); }
duke@435	2005	// clear upper word
duke@435	2006	inline void clruwu( Register d ) { srl( d, G0, d); }
duke@435	2007
duke@435	2008	// membar psuedo instruction. takes into account target memory model.
duke@435	2009	inline void membar( Assembler::Membar_mask_bits const7a );
duke@435	2010
duke@435	2011	// returns if membar generates anything.
duke@435	2012	inline bool membar_has_effect( Assembler::Membar_mask_bits const7a );
duke@435	2013
duke@435	2014	// mov pseudo instructions
duke@435	2015	inline void mov( Register s, Register d) {
duke@435	2016	if ( s != d ) or3( G0, s, d);
duke@435	2017	else assert_not_delayed(); // Put something useful in the delay slot!
duke@435	2018	}
duke@435	2019
duke@435	2020	inline void mov_or_nop( Register s, Register d) {
duke@435	2021	if ( s != d ) or3( G0, s, d);
duke@435	2022	else nop();
duke@435	2023	}
duke@435	2024
duke@435	2025	inline void mov( int simm13a, Register d) { or3( G0, simm13a, d); }
duke@435	2026
duke@435	2027	// address pseudos: make these names unlike instruction names to avoid confusion
duke@435	2028	inline intptr_t load_pc_address( Register reg, int bytes_to_skip );
coleenp@2035	2029	inline void load_contents(const AddressLiteral& addrlit, Register d, int offset = 0);
coleenp@2035	2030	inline void load_ptr_contents(const AddressLiteral& addrlit, Register d, int offset = 0);
coleenp@2035	2031	inline void store_contents(Register s, const AddressLiteral& addrlit, Register temp, int offset = 0);
coleenp@2035	2032	inline void store_ptr_contents(Register s, const AddressLiteral& addrlit, Register temp, int offset = 0);
coleenp@2035	2033	inline void jumpl_to(const AddressLiteral& addrlit, Register temp, Register d, int offset = 0);
coleenp@2035	2034	inline void jump_to(const AddressLiteral& addrlit, Register temp, int offset = 0);
twisti@1162	2035	inline void jump_indirect_to(Address& a, Register temp, int ld_offset = 0, int jmp_offset = 0);
duke@435	2036
duke@435	2037	// ring buffer traceable jumps
duke@435	2038
duke@435	2039	void jmp2( Register r1, Register r2, const char* file, int line );
duke@435	2040	void jmp ( Register r1, int offset, const char* file, int line );
duke@435	2041
coleenp@2035	2042	void jumpl(const AddressLiteral& addrlit, Register temp, Register d, int offset, const char* file, int line);
coleenp@2035	2043	void jump (const AddressLiteral& addrlit, Register temp, int offset, const char* file, int line);
duke@435	2044
duke@435	2045
duke@435	2046	// argument pseudos:
duke@435	2047
duke@435	2048	inline void load_argument( Argument& a, Register d );
duke@435	2049	inline void store_argument( Register s, Argument& a );
duke@435	2050	inline void store_ptr_argument( Register s, Argument& a );
duke@435	2051	inline void store_float_argument( FloatRegister s, Argument& a );
duke@435	2052	inline void store_double_argument( FloatRegister s, Argument& a );
duke@435	2053	inline void store_long_argument( Register s, Argument& a );
duke@435	2054
duke@435	2055	// handy macros:
duke@435	2056
duke@435	2057	inline void round_to( Register r, int modulus ) {
duke@435	2058	assert_not_delayed();
duke@435	2059	inc( r, modulus - 1 );
duke@435	2060	and3( r, -modulus, r );
duke@435	2061	}
duke@435	2062
duke@435	2063	// --------------------------------------------------
duke@435	2064
duke@435	2065	// Functions for isolating 64 bit loads for LP64
duke@435	2066	// ld_ptr will perform ld for 32 bit VM's and ldx for 64 bit VM's
duke@435	2067	// st_ptr will perform st for 32 bit VM's and stx for 64 bit VM's
twisti@1162	2068	inline void ld_ptr(Register s1, Register s2, Register d);
twisti@1162	2069	inline void ld_ptr(Register s1, int simm13a, Register d);
twisti@1162	2070	inline void ld_ptr(Register s1, RegisterOrConstant s2, Register d);
twisti@1162	2071	inline void ld_ptr(const Address& a, Register d, int offset = 0);
twisti@1162	2072	inline void st_ptr(Register d, Register s1, Register s2);
twisti@1162	2073	inline void st_ptr(Register d, Register s1, int simm13a);
twisti@1162	2074	inline void st_ptr(Register d, Register s1, RegisterOrConstant s2);
twisti@1162	2075	inline void st_ptr(Register d, const Address& a, int offset = 0);
twisti@1162	2076
twisti@1162	2077	#ifdef ASSERT
twisti@1162	2078	// ByteSize is only a class when ASSERT is defined, otherwise it's an int.
twisti@1162	2079	inline void ld_ptr(Register s1, ByteSize simm13a, Register d);
twisti@1162	2080	inline void st_ptr(Register d, Register s1, ByteSize simm13a);
twisti@1162	2081	#endif
duke@435	2082
twisti@1858	2083	// ld_long will perform ldd for 32 bit VM's and ldx for 64 bit VM's
twisti@1858	2084	// st_long will perform std for 32 bit VM's and stx for 64 bit VM's
twisti@1162	2085	inline void ld_long(Register s1, Register s2, Register d);
twisti@1162	2086	inline void ld_long(Register s1, int simm13a, Register d);
twisti@1162	2087	inline void ld_long(Register s1, RegisterOrConstant s2, Register d);
twisti@1162	2088	inline void ld_long(const Address& a, Register d, int offset = 0);
twisti@1162	2089	inline void st_long(Register d, Register s1, Register s2);
twisti@1162	2090	inline void st_long(Register d, Register s1, int simm13a);
twisti@1162	2091	inline void st_long(Register d, Register s1, RegisterOrConstant s2);
twisti@1162	2092	inline void st_long(Register d, const Address& a, int offset = 0);
jrose@1057	2093
jrose@1058	2094	// Helpers for address formation.
twisti@1858	2095	// - They emit only a move if s2 is a constant zero.
twisti@1858	2096	// - If dest is a constant and either s1 or s2 is a register, the temp argument is required and becomes the result.
twisti@1858	2097	// - If dest is a register and either s1 or s2 is a non-simm13 constant, the temp argument is required and used to materialize the constant.
twisti@1858	2098	RegisterOrConstant regcon_andn_ptr(RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp = noreg);
twisti@1858	2099	RegisterOrConstant regcon_inc_ptr( RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp = noreg);
twisti@1858	2100	RegisterOrConstant regcon_sll_ptr( RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp = noreg);
twisti@1858	2101
twisti@1858	2102	RegisterOrConstant ensure_simm13_or_reg(RegisterOrConstant src, Register temp) {
twisti@1858	2103	if (is_simm13(src.constant_or_zero()))
twisti@1858	2104	return src; // register or short constant
twisti@1858	2105	guarantee(temp != noreg, "constant offset overflow");
twisti@1858	2106	set(src.as_constant(), temp);
twisti@1858	2107	return temp;
jrose@1058	2108	}
jrose@1058	2109
duke@435	2110	// --------------------------------------------------
duke@435	2111
duke@435	2112	public:
duke@435	2113	// traps as per trap.h (SPARC ABI?)
duke@435	2114
duke@435	2115	void breakpoint_trap();
duke@435	2116	void breakpoint_trap(Condition c, CC cc = icc);
duke@435	2117	void flush_windows_trap();
duke@435	2118	void clean_windows_trap();
duke@435	2119	void get_psr_trap();
duke@435	2120	void set_psr_trap();
duke@435	2121
duke@435	2122	// V8/V9 flush_windows
duke@435	2123	void flush_windows();
duke@435	2124
duke@435	2125	// Support for serializing memory accesses between threads
duke@435	2126	void serialize_memory(Register thread, Register tmp1, Register tmp2);
duke@435	2127
duke@435	2128	// Stack frame creation/removal
duke@435	2129	void enter();
duke@435	2130	void leave();
duke@435	2131
duke@435	2132	// V8/V9 integer multiply
duke@435	2133	void mult(Register s1, Register s2, Register d);
duke@435	2134	void mult(Register s1, int simm13a, Register d);
duke@435	2135
duke@435	2136	// V8/V9 read and write of condition codes.
duke@435	2137	void read_ccr(Register d);
duke@435	2138	void write_ccr(Register s);
duke@435	2139
duke@435	2140	// Manipulation of C++ bools
duke@435	2141	// These are idioms to flag the need for care with accessing bools but on
duke@435	2142	// this platform we assume byte size
duke@435	2143
twisti@1162	2144	inline void stbool(Register d, const Address& a) { stb(d, a); }
twisti@1162	2145	inline void ldbool(const Address& a, Register d) { ldsb(a, d); }
duke@435	2146	inline void tstbool( Register s ) { tst(s); }
duke@435	2147	inline void movbool( bool boolconst, Register d) { mov( (int) boolconst, d); }
duke@435	2148
coleenp@548	2149	// klass oop manipulations if compressed
kvn@599	2150	void load_klass(Register src_oop, Register klass);
kvn@599	2151	void store_klass(Register klass, Register dst_oop);
coleenp@602	2152	void store_klass_gap(Register s, Register dst_oop);
coleenp@548	2153
coleenp@548	2154	// oop manipulations
twisti@1162	2155	void load_heap_oop(const Address& s, Register d);
coleenp@548	2156	void load_heap_oop(Register s1, Register s2, Register d);
coleenp@548	2157	void load_heap_oop(Register s1, int simm13a, Register d);
twisti@2201	2158	void load_heap_oop(Register s1, RegisterOrConstant s2, Register d);
coleenp@548	2159	void store_heap_oop(Register d, Register s1, Register s2);
coleenp@548	2160	void store_heap_oop(Register d, Register s1, int simm13a);
coleenp@548	2161	void store_heap_oop(Register d, const Address& a, int offset = 0);
coleenp@548	2162
coleenp@548	2163	void encode_heap_oop(Register src, Register dst);
coleenp@548	2164	void encode_heap_oop(Register r) {
coleenp@548	2165	encode_heap_oop(r, r);
coleenp@548	2166	}
coleenp@548	2167	void decode_heap_oop(Register src, Register dst);
coleenp@548	2168	void decode_heap_oop(Register r) {
coleenp@548	2169	decode_heap_oop(r, r);
coleenp@548	2170	}
coleenp@548	2171	void encode_heap_oop_not_null(Register r);
coleenp@548	2172	void decode_heap_oop_not_null(Register r);
kvn@559	2173	void encode_heap_oop_not_null(Register src, Register dst);
kvn@559	2174	void decode_heap_oop_not_null(Register src, Register dst);
coleenp@548	2175
duke@435	2176	// Support for managing the JavaThread pointer (i.e.; the reference to
duke@435	2177	// thread-local information).
duke@435	2178	void get_thread(); // load G2_thread
duke@435	2179	void verify_thread(); // verify G2_thread contents
duke@435	2180	void save_thread (const Register threache); // save to cache
duke@435	2181	void restore_thread(const Register thread_cache); // restore from cache
duke@435	2182
duke@435	2183	// Support for last Java frame (but use call_VM instead where possible)
duke@435	2184	void set_last_Java_frame(Register last_java_sp, Register last_Java_pc);
duke@435	2185	void reset_last_Java_frame(void);
duke@435	2186
duke@435	2187	// Call into the VM.
duke@435	2188	// Passes the thread pointer (in O0) as a prepended argument.
duke@435	2189	// Makes sure oop return values are visible to the GC.
duke@435	2190	void call_VM(Register oop_result, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
duke@435	2191	void call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions = true);
duke@435	2192	void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
duke@435	2193	void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
duke@435	2194
duke@435	2195	// these overloadings are not presently used on SPARC:
duke@435	2196	void call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
duke@435	2197	void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
duke@435	2198	void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
duke@435	2199	void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
duke@435	2200
duke@435	2201	void call_VM_leaf(Register thread_cache, address entry_point, int number_of_arguments = 0);
duke@435	2202	void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1);
duke@435	2203	void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2);
duke@435	2204	void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2, Register arg_3);
duke@435	2205
duke@435	2206	void get_vm_result (Register oop_result);
duke@435	2207	void get_vm_result_2(Register oop_result);
duke@435	2208
duke@435	2209	// vm result is currently getting hijacked to for oop preservation
duke@435	2210	void set_vm_result(Register oop_result);
duke@435	2211
duke@435	2212	// if call_VM_base was called with check_exceptions=false, then call
duke@435	2213	// check_and_forward_exception to handle exceptions when it is safe
duke@435	2214	void check_and_forward_exception(Register scratch_reg);
duke@435	2215
duke@435	2216	private:
duke@435	2217	// For V8
duke@435	2218	void read_ccr_trap(Register ccr_save);
duke@435	2219	void write_ccr_trap(Register ccr_save1, Register scratch1, Register scratch2);
duke@435	2220
duke@435	2221	#ifdef ASSERT
duke@435	2222	// For V8 debugging. Uses V8 instruction sequence and checks
duke@435	2223	// result with V9 insturctions rdccr and wrccr.
duke@435	2224	// Uses Gscatch and Gscatch2
duke@435	2225	void read_ccr_v8_assert(Register ccr_save);
duke@435	2226	void write_ccr_v8_assert(Register ccr_save);
duke@435	2227	#endif // ASSERT
duke@435	2228
duke@435	2229	public:
ysr@777	2230
ysr@777	2231	// Write to card table for - register is destroyed afterwards.
ysr@777	2232	void card_table_write(jbyte* byte_map_base, Register tmp, Register obj);
ysr@777	2233
ysr@777	2234	void card_write_barrier_post(Register store_addr, Register new_val, Register tmp);
ysr@777	2235
ysr@777	2236	#ifndef SERIALGC
johnc@2781	2237	// General G1 pre-barrier generator.
johnc@2781	2238	void g1_write_barrier_pre(Register obj, Register index, int offset, Register pre_val, Register tmp, bool preserve_o_regs);
johnc@2781	2239
johnc@2781	2240	// General G1 post-barrier generator
ysr@777	2241	void g1_write_barrier_post(Register store_addr, Register new_val, Register tmp);
ysr@777	2242	#endif // SERIALGC
duke@435	2243
duke@435	2244	// pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
duke@435	2245	void push_fTOS();
duke@435	2246
duke@435	2247	// pops double TOS element from CPU stack and pushes on FPU stack
duke@435	2248	void pop_fTOS();
duke@435	2249
duke@435	2250	void empty_FPU_stack();
duke@435	2251
duke@435	2252	void push_IU_state();
duke@435	2253	void pop_IU_state();
duke@435	2254
duke@435	2255	void push_FPU_state();
duke@435	2256	void pop_FPU_state();
duke@435	2257
duke@435	2258	void push_CPU_state();
duke@435	2259	void pop_CPU_state();
duke@435	2260
coleenp@548	2261	// if heap base register is used - reinit it with the correct value
coleenp@548	2262	void reinit_heapbase();
coleenp@548	2263
duke@435	2264	// Debugging
duke@435	2265	void _verify_oop(Register reg, const char * msg, const char * file, int line);
duke@435	2266	void _verify_oop_addr(Address addr, const char * msg, const char * file, int line);
duke@435	2267
duke@435	2268	#define verify_oop(reg) _verify_oop(reg, "broken oop " #reg, __FILE__, __LINE__)
duke@435	2269	#define verify_oop_addr(addr) _verify_oop_addr(addr, "broken oop addr ", __FILE__, __LINE__)
duke@435	2270
duke@435	2271	// only if +VerifyOops
duke@435	2272	void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
duke@435	2273	// only if +VerifyFPU
duke@435	2274	void stop(const char* msg); // prints msg, dumps registers and stops execution
duke@435	2275	void warn(const char* msg); // prints msg, but don't stop
duke@435	2276	void untested(const char* what = "");
twisti@2201	2277	void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, 1024, "unimplemented: %s", what); stop(b); }
duke@435	2278	void should_not_reach_here() { stop("should not reach here"); }
duke@435	2279	void print_CPU_state();
duke@435	2280
duke@435	2281	// oops in code
twisti@1162	2282	AddressLiteral allocate_oop_address(jobject obj); // allocate_index
twisti@1162	2283	AddressLiteral constant_oop_address(jobject obj); // find_index
twisti@1162	2284	inline void set_oop (jobject obj, Register d); // uses allocate_oop_address
twisti@1162	2285	inline void set_oop_constant (jobject obj, Register d); // uses constant_oop_address
jcoomes@1902	2286	inline void set_oop (const AddressLiteral& obj_addr, Register d); // same as load_address
duke@435	2287
kvn@599	2288	void set_narrow_oop( jobject obj, Register d );
kvn@599	2289
duke@435	2290	// nop padding
duke@435	2291	void align(int modulus);
duke@435	2292
duke@435	2293	// declare a safepoint
duke@435	2294	void safepoint();
duke@435	2295
duke@435	2296	// factor out part of stop into subroutine to save space
duke@435	2297	void stop_subroutine();
duke@435	2298	// factor out part of verify_oop into subroutine to save space
duke@435	2299	void verify_oop_subroutine();
duke@435	2300
duke@435	2301	// side-door communication with signalHandler in os_solaris.cpp
duke@435	2302	static address _verify_oop_implicit_branch[3];
duke@435	2303
duke@435	2304	#ifndef PRODUCT
duke@435	2305	static void test();
duke@435	2306	#endif
duke@435	2307
duke@435	2308	// convert an incoming arglist to varargs format; put the pointer in d
duke@435	2309	void set_varargs( Argument a, Register d );
duke@435	2310
duke@435	2311	int total_frame_size_in_bytes(int extraWords);
duke@435	2312
duke@435	2313	// used when extraWords known statically
never@2950	2314	void save_frame(int extraWords = 0);
duke@435	2315	void save_frame_c1(int size_in_bytes);
duke@435	2316	// make a frame, and simultaneously pass up one or two register value
duke@435	2317	// into the new register window
duke@435	2318	void save_frame_and_mov(int extraWords, Register s1, Register d1, Register s2 = Register(), Register d2 = Register());
duke@435	2319
duke@435	2320	// give no. (outgoing) params, calc # of words will need on frame
duke@435	2321	void calc_mem_param_words(Register Rparam_words, Register Rresult);
duke@435	2322
duke@435	2323	// used to calculate frame size dynamically
duke@435	2324	// result is in bytes and must be negated for save inst
duke@435	2325	void calc_frame_size(Register extraWords, Register resultReg);
duke@435	2326
duke@435	2327	// calc and also save
duke@435	2328	void calc_frame_size_and_save(Register extraWords, Register resultReg);
duke@435	2329
duke@435	2330	static void debug(char* msg, RegistersForDebugging* outWindow);
duke@435	2331
duke@435	2332	// implementations of bytecodes used by both interpreter and compiler
duke@435	2333
duke@435	2334	void lcmp( Register Ra_hi, Register Ra_low,
duke@435	2335	Register Rb_hi, Register Rb_low,
duke@435	2336	Register Rresult);
duke@435	2337
duke@435	2338	void lneg( Register Rhi, Register Rlow );
duke@435	2339
duke@435	2340	void lshl( Register Rin_high, Register Rin_low, Register Rcount,
duke@435	2341	Register Rout_high, Register Rout_low, Register Rtemp );
duke@435	2342
duke@435	2343	void lshr( Register Rin_high, Register Rin_low, Register Rcount,
duke@435	2344	Register Rout_high, Register Rout_low, Register Rtemp );
duke@435	2345
duke@435	2346	void lushr( Register Rin_high, Register Rin_low, Register Rcount,
duke@435	2347	Register Rout_high, Register Rout_low, Register Rtemp );
duke@435	2348
duke@435	2349	#ifdef _LP64
duke@435	2350	void lcmp( Register Ra, Register Rb, Register Rresult);
duke@435	2351	#endif
duke@435	2352
twisti@2565	2353	// Load and store values by size and signed-ness
twisti@2565	2354	void load_sized_value( Address src, Register dst, size_t size_in_bytes, bool is_signed);
twisti@2565	2355	void store_sized_value(Register src, Address dst, size_t size_in_bytes);
twisti@1858	2356
duke@435	2357	void float_cmp( bool is_float, int unordered_result,
duke@435	2358	FloatRegister Fa, FloatRegister Fb,
duke@435	2359	Register Rresult);
duke@435	2360
duke@435	2361	void fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d);
duke@435	2362	void fneg( FloatRegisterImpl::Width w, FloatRegister sd ) { Assembler::fneg(w, sd); }
duke@435	2363	void fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d);
duke@435	2364	void fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d);
duke@435	2365
duke@435	2366	void save_all_globals_into_locals();
duke@435	2367	void restore_globals_from_locals();
duke@435	2368
duke@435	2369	void casx_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg,
duke@435	2370	address lock_addr=0, bool use_call_vm=false);
duke@435	2371	void cas_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg,
duke@435	2372	address lock_addr=0, bool use_call_vm=false);
duke@435	2373	void casn (Register addr_reg, Register cmp_reg, Register set_reg) ;
duke@435	2374
duke@435	2375	// These set the icc condition code to equal if the lock succeeded
duke@435	2376	// and notEqual if it failed and requires a slow case
kvn@855	2377	void compiler_lock_object(Register Roop, Register Rmark, Register Rbox,
kvn@855	2378	Register Rscratch,
kvn@855	2379	BiasedLockingCounters* counters = NULL,
kvn@855	2380	bool try_bias = UseBiasedLocking);
kvn@855	2381	void compiler_unlock_object(Register Roop, Register Rmark, Register Rbox,
kvn@855	2382	Register Rscratch,
kvn@855	2383	bool try_bias = UseBiasedLocking);
duke@435	2384
duke@435	2385	// Biased locking support
duke@435	2386	// Upon entry, lock_reg must point to the lock record on the stack,
duke@435	2387	// obj_reg must contain the target object, and mark_reg must contain
duke@435	2388	// the target object's header.
duke@435	2389	// Destroys mark_reg if an attempt is made to bias an anonymously
duke@435	2390	// biased lock. In this case a failure will go either to the slow
duke@435	2391	// case or fall through with the notEqual condition code set with
duke@435	2392	// the expectation that the slow case in the runtime will be called.
duke@435	2393	// In the fall-through case where the CAS-based lock is done,
duke@435	2394	// mark_reg is not destroyed.
duke@435	2395	void biased_locking_enter(Register obj_reg, Register mark_reg, Register temp_reg,
duke@435	2396	Label& done, Label* slow_case = NULL,
duke@435	2397	BiasedLockingCounters* counters = NULL);
duke@435	2398	// Upon entry, the base register of mark_addr must contain the oop.
duke@435	2399	// Destroys temp_reg.
duke@435	2400
duke@435	2401	// If allow_delay_slot_filling is set to true, the next instruction
duke@435	2402	// emitted after this one will go in an annulled delay slot if the
duke@435	2403	// biased locking exit case failed.
duke@435	2404	void biased_locking_exit(Address mark_addr, Register temp_reg, Label& done, bool allow_delay_slot_filling = false);
duke@435	2405
duke@435	2406	// allocation
duke@435	2407	void eden_allocate(
duke@435	2408	Register obj, // result: pointer to object after successful allocation
duke@435	2409	Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
duke@435	2410	int con_size_in_bytes, // object size in bytes if known at compile time
duke@435	2411	Register t1, // temp register
duke@435	2412	Register t2, // temp register
duke@435	2413	Label& slow_case // continuation point if fast allocation fails
duke@435	2414	);
duke@435	2415	void tlab_allocate(
duke@435	2416	Register obj, // result: pointer to object after successful allocation
duke@435	2417	Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
duke@435	2418	int con_size_in_bytes, // object size in bytes if known at compile time
duke@435	2419	Register t1, // temp register
duke@435	2420	Label& slow_case // continuation point if fast allocation fails
duke@435	2421	);
duke@435	2422	void tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case);
phh@2447	2423	void incr_allocated_bytes(RegisterOrConstant size_in_bytes,
phh@2447	2424	Register t1, Register t2);
duke@435	2425
jrose@1058	2426	// interface method calling
jrose@1058	2427	void lookup_interface_method(Register recv_klass,
jrose@1058	2428	Register intf_klass,
jrose@1100	2429	RegisterOrConstant itable_index,
jrose@1058	2430	Register method_result,
jrose@1058	2431	Register temp_reg, Register temp2_reg,
jrose@1058	2432	Label& no_such_interface);
jrose@1058	2433
jrose@1079	2434	// Test sub_klass against super_klass, with fast and slow paths.
jrose@1079	2435
jrose@1079	2436	// The fast path produces a tri-state answer: yes / no / maybe-slow.
jrose@1079	2437	// One of the three labels can be NULL, meaning take the fall-through.
jrose@1079	2438	// If super_check_offset is -1, the value is loaded up from super_klass.
jrose@1079	2439	// No registers are killed, except temp_reg and temp2_reg.
jrose@1079	2440	// If super_check_offset is not -1, temp2_reg is not used and can be noreg.
jrose@1079	2441	void check_klass_subtype_fast_path(Register sub_klass,
jrose@1079	2442	Register super_klass,
jrose@1079	2443	Register temp_reg,
jrose@1079	2444	Register temp2_reg,
jrose@1079	2445	Label* L_success,
jrose@1079	2446	Label* L_failure,
jrose@1079	2447	Label* L_slow_path,
jrose@1100	2448	RegisterOrConstant super_check_offset = RegisterOrConstant(-1),
jrose@1079	2449	Register instanceof_hack = noreg);
jrose@1079	2450
jrose@1079	2451	// The rest of the type check; must be wired to a corresponding fast path.
jrose@1079	2452	// It does not repeat the fast path logic, so don't use it standalone.
jrose@1079	2453	// The temp_reg can be noreg, if no temps are available.
jrose@1079	2454	// It can also be sub_klass or super_klass, meaning it's OK to kill that one.
jrose@1079	2455	// Updates the sub's secondary super cache as necessary.
jrose@1079	2456	void check_klass_subtype_slow_path(Register sub_klass,
jrose@1079	2457	Register super_klass,
jrose@1079	2458	Register temp_reg,
jrose@1079	2459	Register temp2_reg,
jrose@1079	2460	Register temp3_reg,
jrose@1079	2461	Register temp4_reg,
jrose@1079	2462	Label* L_success,
jrose@1079	2463	Label* L_failure);
jrose@1079	2464
jrose@1079	2465	// Simplified, combined version, good for typical uses.
jrose@1079	2466	// Falls through on failure.
jrose@1079	2467	void check_klass_subtype(Register sub_klass,
jrose@1079	2468	Register super_klass,
jrose@1079	2469	Register temp_reg,
jrose@1079	2470	Register temp2_reg,
jrose@1079	2471	Label& L_success);
jrose@1079	2472
jrose@1145	2473	// method handles (JSR 292)
jrose@1145	2474	void check_method_handle_type(Register mtype_reg, Register mh_reg,
jrose@1145	2475	Register temp_reg,
jrose@1145	2476	Label& wrong_method_type);
twisti@1858	2477	void load_method_handle_vmslots(Register vmslots_reg, Register mh_reg,
twisti@1858	2478	Register temp_reg);
twisti@1858	2479	void jump_to_method_handle_entry(Register mh_reg, Register temp_reg, bool emit_delayed_nop = true);
jrose@1145	2480	// offset relative to Gargs of argument at tos[arg_slot].
jrose@1145	2481	// (arg_slot == 0 means the last argument, not the first).
jrose@1145	2482	RegisterOrConstant argument_offset(RegisterOrConstant arg_slot,
never@2950	2483	Register temp_reg,
jrose@1145	2484	int extra_slot_offset = 0);
twisti@1858	2485	// Address of Gargs and argument_offset.
twisti@1858	2486	Address argument_address(RegisterOrConstant arg_slot,
never@2950	2487	Register temp_reg,
twisti@1858	2488	int extra_slot_offset = 0);
jrose@1079	2489
duke@435	2490	// Stack overflow checking
duke@435	2491
duke@435	2492	// Note: this clobbers G3_scratch
duke@435	2493	void bang_stack_with_offset(int offset) {
duke@435	2494	// stack grows down, caller passes positive offset
duke@435	2495	assert(offset > 0, "must bang with negative offset");
duke@435	2496	set((-offset)+STACK_BIAS, G3_scratch);
duke@435	2497	st(G0, SP, G3_scratch);
duke@435	2498	}
duke@435	2499
duke@435	2500	// Writes to stack successive pages until offset reached to check for
duke@435	2501	// stack overflow + shadow pages. Clobbers tsp and scratch registers.
duke@435	2502	void bang_stack_size(Register Rsize, Register Rtsp, Register Rscratch);
duke@435	2503
jrose@1100	2504	virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr, Register tmp, int offset);
jrose@1057	2505
duke@435	2506	void verify_tlab();
duke@435	2507
duke@435	2508	Condition negate_condition(Condition cond);
duke@435	2509
duke@435	2510	// Helper functions for statistics gathering.
duke@435	2511	// Conditionally (non-atomically) increments passed counter address, preserving condition codes.
duke@435	2512	void cond_inc(Condition cond, address counter_addr, Register Rtemp1, Register Rtemp2);
duke@435	2513	// Unconditional increment.
twisti@1162	2514	void inc_counter(address counter_addr, Register Rtmp1, Register Rtmp2);
twisti@1162	2515	void inc_counter(int* counter_addr, Register Rtmp1, Register Rtmp2);
duke@435	2516
kvn@1421	2517	// Compare char[] arrays aligned to 4 bytes.
kvn@1421	2518	void char_arrays_equals(Register ary1, Register ary2,
kvn@1421	2519	Register limit, Register result,
kvn@1421	2520	Register chr1, Register chr2, Label& Ldone);
kvn@1421	2521
duke@435	2522	#undef VIRTUAL
duke@435	2523
duke@435	2524	};
duke@435	2525
duke@435	2526	/**
duke@435	2527	* class SkipIfEqual:
duke@435	2528	*
duke@435	2529	* Instantiating this class will result in assembly code being output that will
duke@435	2530	* jump around any code emitted between the creation of the instance and it's
duke@435	2531	* automatic destruction at the end of a scope block, depending on the value of
duke@435	2532	* the flag passed to the constructor, which will be checked at run-time.
duke@435	2533	*/
duke@435	2534	class SkipIfEqual : public StackObj {
duke@435	2535	private:
duke@435	2536	MacroAssembler* _masm;
duke@435	2537	Label _label;
duke@435	2538
duke@435	2539	public:
duke@435	2540	// 'temp' is a temp register that this object can use (and trash)
duke@435	2541	SkipIfEqual(MacroAssembler*, Register temp,
duke@435	2542	const bool* flag_addr, Assembler::Condition condition);
duke@435	2543	~SkipIfEqual();
duke@435	2544	};
duke@435	2545
duke@435	2546	#ifdef ASSERT
duke@435	2547	// On RISC, there's no benefit to verifying instruction boundaries.
duke@435	2548	inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
duke@435	2549	#endif
stefank@2314	2550
stefank@2314	2551	#endif // CPU_SPARC_VM_ASSEMBLER_SPARC_HPP