Wed, 07 May 2008 08:06:46 -0700
6603011: RFE: Optimize long division
Summary: Transform long division by constant into multiply
Reviewed-by: never, kvn
duke@435 | 1 | /* |
duke@435 | 2 | * Copyright 1997-2007 Sun Microsystems, Inc. All Rights Reserved. |
duke@435 | 3 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
duke@435 | 4 | * |
duke@435 | 5 | * This code is free software; you can redistribute it and/or modify it |
duke@435 | 6 | * under the terms of the GNU General Public License version 2 only, as |
duke@435 | 7 | * published by the Free Software Foundation. |
duke@435 | 8 | * |
duke@435 | 9 | * This code is distributed in the hope that it will be useful, but WITHOUT |
duke@435 | 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
duke@435 | 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
duke@435 | 12 | * version 2 for more details (a copy is included in the LICENSE file that |
duke@435 | 13 | * accompanied this code). |
duke@435 | 14 | * |
duke@435 | 15 | * You should have received a copy of the GNU General Public License version |
duke@435 | 16 | * 2 along with this work; if not, write to the Free Software Foundation, |
duke@435 | 17 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
duke@435 | 18 | * |
duke@435 | 19 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
duke@435 | 20 | * CA 95054 USA or visit www.sun.com if you need additional information or |
duke@435 | 21 | * have any questions. |
duke@435 | 22 | * |
duke@435 | 23 | */ |
duke@435 | 24 | |
duke@435 | 25 | # include "incls/_precompiled.incl" |
duke@435 | 26 | # include "incls/_nativeInst_x86.cpp.incl" |
duke@435 | 27 | |
duke@435 | 28 | void NativeInstruction::wrote(int offset) { |
duke@435 | 29 | ICache::invalidate_word(addr_at(offset)); |
duke@435 | 30 | } |
duke@435 | 31 | |
duke@435 | 32 | |
duke@435 | 33 | void NativeCall::verify() { |
duke@435 | 34 | // Make sure code pattern is actually a call imm32 instruction. |
duke@435 | 35 | int inst = ubyte_at(0); |
duke@435 | 36 | if (inst != instruction_code) { |
duke@435 | 37 | tty->print_cr("Addr: " INTPTR_FORMAT " Code: 0x%x", instruction_address(), |
duke@435 | 38 | inst); |
duke@435 | 39 | fatal("not a call disp32"); |
duke@435 | 40 | } |
duke@435 | 41 | } |
duke@435 | 42 | |
duke@435 | 43 | address NativeCall::destination() const { |
duke@435 | 44 | // Getting the destination of a call isn't safe because that call can |
duke@435 | 45 | // be getting patched while you're calling this. There's only special |
duke@435 | 46 | // places where this can be called but not automatically verifiable by |
duke@435 | 47 | // checking which locks are held. The solution is true atomic patching |
duke@435 | 48 | // on x86, nyi. |
duke@435 | 49 | return return_address() + displacement(); |
duke@435 | 50 | } |
duke@435 | 51 | |
duke@435 | 52 | void NativeCall::print() { |
duke@435 | 53 | tty->print_cr(PTR_FORMAT ": call " PTR_FORMAT, |
duke@435 | 54 | instruction_address(), destination()); |
duke@435 | 55 | } |
duke@435 | 56 | |
duke@435 | 57 | // Inserts a native call instruction at a given pc |
duke@435 | 58 | void NativeCall::insert(address code_pos, address entry) { |
duke@435 | 59 | intptr_t disp = (intptr_t)entry - ((intptr_t)code_pos + 1 + 4); |
duke@435 | 60 | #ifdef AMD64 |
duke@435 | 61 | guarantee(disp == (intptr_t)(jint)disp, "must be 32-bit offset"); |
duke@435 | 62 | #endif // AMD64 |
duke@435 | 63 | *code_pos = instruction_code; |
duke@435 | 64 | *((int32_t *)(code_pos+1)) = (int32_t) disp; |
duke@435 | 65 | ICache::invalidate_range(code_pos, instruction_size); |
duke@435 | 66 | } |
duke@435 | 67 | |
duke@435 | 68 | // MT-safe patching of a call instruction. |
duke@435 | 69 | // First patches first word of instruction to two jmp's that jmps to them |
duke@435 | 70 | // selfs (spinlock). Then patches the last byte, and then atomicly replaces |
duke@435 | 71 | // the jmp's with the first 4 byte of the new instruction. |
duke@435 | 72 | void NativeCall::replace_mt_safe(address instr_addr, address code_buffer) { |
duke@435 | 73 | assert(Patching_lock->is_locked() || |
duke@435 | 74 | SafepointSynchronize::is_at_safepoint(), "concurrent code patching"); |
duke@435 | 75 | assert (instr_addr != NULL, "illegal address for code patching"); |
duke@435 | 76 | |
duke@435 | 77 | NativeCall* n_call = nativeCall_at (instr_addr); // checking that it is a call |
duke@435 | 78 | if (os::is_MP()) { |
duke@435 | 79 | guarantee((intptr_t)instr_addr % BytesPerWord == 0, "must be aligned"); |
duke@435 | 80 | } |
duke@435 | 81 | |
duke@435 | 82 | // First patch dummy jmp in place |
duke@435 | 83 | unsigned char patch[4]; |
duke@435 | 84 | assert(sizeof(patch)==sizeof(jint), "sanity check"); |
duke@435 | 85 | patch[0] = 0xEB; // jmp rel8 |
duke@435 | 86 | patch[1] = 0xFE; // jmp to self |
duke@435 | 87 | patch[2] = 0xEB; |
duke@435 | 88 | patch[3] = 0xFE; |
duke@435 | 89 | |
duke@435 | 90 | // First patch dummy jmp in place |
duke@435 | 91 | *(jint*)instr_addr = *(jint *)patch; |
duke@435 | 92 | |
duke@435 | 93 | // Invalidate. Opteron requires a flush after every write. |
duke@435 | 94 | n_call->wrote(0); |
duke@435 | 95 | |
duke@435 | 96 | // Patch 4th byte |
duke@435 | 97 | instr_addr[4] = code_buffer[4]; |
duke@435 | 98 | |
duke@435 | 99 | n_call->wrote(4); |
duke@435 | 100 | |
duke@435 | 101 | // Patch bytes 0-3 |
duke@435 | 102 | *(jint*)instr_addr = *(jint *)code_buffer; |
duke@435 | 103 | |
duke@435 | 104 | n_call->wrote(0); |
duke@435 | 105 | |
duke@435 | 106 | #ifdef ASSERT |
duke@435 | 107 | // verify patching |
duke@435 | 108 | for ( int i = 0; i < instruction_size; i++) { |
duke@435 | 109 | address ptr = (address)((intptr_t)code_buffer + i); |
duke@435 | 110 | int a_byte = (*ptr) & 0xFF; |
duke@435 | 111 | assert(*((address)((intptr_t)instr_addr + i)) == a_byte, "mt safe patching failed"); |
duke@435 | 112 | } |
duke@435 | 113 | #endif |
duke@435 | 114 | |
duke@435 | 115 | } |
duke@435 | 116 | |
duke@435 | 117 | |
duke@435 | 118 | // Similar to replace_mt_safe, but just changes the destination. The |
duke@435 | 119 | // important thing is that free-running threads are able to execute this |
duke@435 | 120 | // call instruction at all times. If the displacement field is aligned |
duke@435 | 121 | // we can simply rely on atomicity of 32-bit writes to make sure other threads |
duke@435 | 122 | // will see no intermediate states. Otherwise, the first two bytes of the |
duke@435 | 123 | // call are guaranteed to be aligned, and can be atomically patched to a |
duke@435 | 124 | // self-loop to guard the instruction while we change the other bytes. |
duke@435 | 125 | |
duke@435 | 126 | // We cannot rely on locks here, since the free-running threads must run at |
duke@435 | 127 | // full speed. |
duke@435 | 128 | // |
duke@435 | 129 | // Used in the runtime linkage of calls; see class CompiledIC. |
duke@435 | 130 | // (Cf. 4506997 and 4479829, where threads witnessed garbage displacements.) |
duke@435 | 131 | void NativeCall::set_destination_mt_safe(address dest) { |
duke@435 | 132 | debug_only(verify()); |
duke@435 | 133 | // Make sure patching code is locked. No two threads can patch at the same |
duke@435 | 134 | // time but one may be executing this code. |
duke@435 | 135 | assert(Patching_lock->is_locked() || |
duke@435 | 136 | SafepointSynchronize::is_at_safepoint(), "concurrent code patching"); |
duke@435 | 137 | // Both C1 and C2 should now be generating code which aligns the patched address |
duke@435 | 138 | // to be within a single cache line except that C1 does not do the alignment on |
duke@435 | 139 | // uniprocessor systems. |
duke@435 | 140 | bool is_aligned = ((uintptr_t)displacement_address() + 0) / cache_line_size == |
duke@435 | 141 | ((uintptr_t)displacement_address() + 3) / cache_line_size; |
duke@435 | 142 | |
duke@435 | 143 | guarantee(!os::is_MP() || is_aligned, "destination must be aligned"); |
duke@435 | 144 | |
duke@435 | 145 | if (is_aligned) { |
duke@435 | 146 | // Simple case: The destination lies within a single cache line. |
duke@435 | 147 | set_destination(dest); |
duke@435 | 148 | } else if ((uintptr_t)instruction_address() / cache_line_size == |
duke@435 | 149 | ((uintptr_t)instruction_address()+1) / cache_line_size) { |
duke@435 | 150 | // Tricky case: The instruction prefix lies within a single cache line. |
duke@435 | 151 | intptr_t disp = dest - return_address(); |
duke@435 | 152 | #ifdef AMD64 |
duke@435 | 153 | guarantee(disp == (intptr_t)(jint)disp, "must be 32-bit offset"); |
duke@435 | 154 | #endif // AMD64 |
duke@435 | 155 | |
duke@435 | 156 | int call_opcode = instruction_address()[0]; |
duke@435 | 157 | |
duke@435 | 158 | // First patch dummy jump in place: |
duke@435 | 159 | { |
duke@435 | 160 | u_char patch_jump[2]; |
duke@435 | 161 | patch_jump[0] = 0xEB; // jmp rel8 |
duke@435 | 162 | patch_jump[1] = 0xFE; // jmp to self |
duke@435 | 163 | |
duke@435 | 164 | assert(sizeof(patch_jump)==sizeof(short), "sanity check"); |
duke@435 | 165 | *(short*)instruction_address() = *(short*)patch_jump; |
duke@435 | 166 | } |
duke@435 | 167 | // Invalidate. Opteron requires a flush after every write. |
duke@435 | 168 | wrote(0); |
duke@435 | 169 | |
duke@435 | 170 | // (Note: We assume any reader which has already started to read |
duke@435 | 171 | // the unpatched call will completely read the whole unpatched call |
duke@435 | 172 | // without seeing the next writes we are about to make.) |
duke@435 | 173 | |
duke@435 | 174 | // Next, patch the last three bytes: |
duke@435 | 175 | u_char patch_disp[5]; |
duke@435 | 176 | patch_disp[0] = call_opcode; |
duke@435 | 177 | *(int32_t*)&patch_disp[1] = (int32_t)disp; |
duke@435 | 178 | assert(sizeof(patch_disp)==instruction_size, "sanity check"); |
duke@435 | 179 | for (int i = sizeof(short); i < instruction_size; i++) |
duke@435 | 180 | instruction_address()[i] = patch_disp[i]; |
duke@435 | 181 | |
duke@435 | 182 | // Invalidate. Opteron requires a flush after every write. |
duke@435 | 183 | wrote(sizeof(short)); |
duke@435 | 184 | |
duke@435 | 185 | // (Note: We assume that any reader which reads the opcode we are |
duke@435 | 186 | // about to repatch will also read the writes we just made.) |
duke@435 | 187 | |
duke@435 | 188 | // Finally, overwrite the jump: |
duke@435 | 189 | *(short*)instruction_address() = *(short*)patch_disp; |
duke@435 | 190 | // Invalidate. Opteron requires a flush after every write. |
duke@435 | 191 | wrote(0); |
duke@435 | 192 | |
duke@435 | 193 | debug_only(verify()); |
duke@435 | 194 | guarantee(destination() == dest, "patch succeeded"); |
duke@435 | 195 | } else { |
duke@435 | 196 | // Impossible: One or the other must be atomically writable. |
duke@435 | 197 | ShouldNotReachHere(); |
duke@435 | 198 | } |
duke@435 | 199 | } |
duke@435 | 200 | |
duke@435 | 201 | |
duke@435 | 202 | void NativeMovConstReg::verify() { |
duke@435 | 203 | #ifdef AMD64 |
duke@435 | 204 | // make sure code pattern is actually a mov reg64, imm64 instruction |
duke@435 | 205 | if ((ubyte_at(0) != Assembler::REX_W && ubyte_at(0) != Assembler::REX_WB) || |
duke@435 | 206 | (ubyte_at(1) & (0xff ^ register_mask)) != 0xB8) { |
duke@435 | 207 | print(); |
duke@435 | 208 | fatal("not a REX.W[B] mov reg64, imm64"); |
duke@435 | 209 | } |
duke@435 | 210 | #else |
duke@435 | 211 | // make sure code pattern is actually a mov reg, imm32 instruction |
duke@435 | 212 | u_char test_byte = *(u_char*)instruction_address(); |
duke@435 | 213 | u_char test_byte_2 = test_byte & ( 0xff ^ register_mask); |
duke@435 | 214 | if (test_byte_2 != instruction_code) fatal("not a mov reg, imm32"); |
duke@435 | 215 | #endif // AMD64 |
duke@435 | 216 | } |
duke@435 | 217 | |
duke@435 | 218 | |
duke@435 | 219 | void NativeMovConstReg::print() { |
duke@435 | 220 | tty->print_cr(PTR_FORMAT ": mov reg, " INTPTR_FORMAT, |
duke@435 | 221 | instruction_address(), data()); |
duke@435 | 222 | } |
duke@435 | 223 | |
duke@435 | 224 | //------------------------------------------------------------------- |
duke@435 | 225 | |
duke@435 | 226 | #ifndef AMD64 |
duke@435 | 227 | |
duke@435 | 228 | void NativeMovRegMem::copy_instruction_to(address new_instruction_address) { |
duke@435 | 229 | int inst_size = instruction_size; |
duke@435 | 230 | |
duke@435 | 231 | // See if there's an instruction size prefix override. |
duke@435 | 232 | if ( *(address(this)) == instruction_operandsize_prefix && |
duke@435 | 233 | *(address(this)+1) != instruction_code_xmm_code ) { // Not SSE instr |
duke@435 | 234 | inst_size += 1; |
duke@435 | 235 | } |
duke@435 | 236 | if ( *(address(this)) == instruction_extended_prefix ) inst_size += 1; |
duke@435 | 237 | |
duke@435 | 238 | for (int i = 0; i < instruction_size; i++) { |
duke@435 | 239 | *(new_instruction_address + i) = *(address(this) + i); |
duke@435 | 240 | } |
duke@435 | 241 | } |
duke@435 | 242 | |
duke@435 | 243 | void NativeMovRegMem::verify() { |
duke@435 | 244 | // make sure code pattern is actually a mov [reg+offset], reg instruction |
duke@435 | 245 | u_char test_byte = *(u_char*)instruction_address(); |
duke@435 | 246 | if ( ! ( (test_byte == instruction_code_reg2memb) |
duke@435 | 247 | || (test_byte == instruction_code_mem2regb) |
duke@435 | 248 | || (test_byte == instruction_code_mem2regl) |
duke@435 | 249 | || (test_byte == instruction_code_reg2meml) |
duke@435 | 250 | || (test_byte == instruction_code_mem2reg_movzxb ) |
duke@435 | 251 | || (test_byte == instruction_code_mem2reg_movzxw ) |
duke@435 | 252 | || (test_byte == instruction_code_mem2reg_movsxb ) |
duke@435 | 253 | || (test_byte == instruction_code_mem2reg_movsxw ) |
duke@435 | 254 | || (test_byte == instruction_code_float_s) |
duke@435 | 255 | || (test_byte == instruction_code_float_d) |
duke@435 | 256 | || (test_byte == instruction_code_long_volatile) ) ) |
duke@435 | 257 | { |
duke@435 | 258 | u_char byte1 = ((u_char*)instruction_address())[1]; |
duke@435 | 259 | u_char byte2 = ((u_char*)instruction_address())[2]; |
duke@435 | 260 | if ((test_byte != instruction_code_xmm_ss_prefix && |
duke@435 | 261 | test_byte != instruction_code_xmm_sd_prefix && |
duke@435 | 262 | test_byte != instruction_operandsize_prefix) || |
duke@435 | 263 | byte1 != instruction_code_xmm_code || |
duke@435 | 264 | (byte2 != instruction_code_xmm_load && |
duke@435 | 265 | byte2 != instruction_code_xmm_lpd && |
duke@435 | 266 | byte2 != instruction_code_xmm_store)) { |
duke@435 | 267 | fatal ("not a mov [reg+offs], reg instruction"); |
duke@435 | 268 | } |
duke@435 | 269 | } |
duke@435 | 270 | } |
duke@435 | 271 | |
duke@435 | 272 | |
duke@435 | 273 | void NativeMovRegMem::print() { |
duke@435 | 274 | tty->print_cr("0x%x: mov reg, [reg + %x]", instruction_address(), offset()); |
duke@435 | 275 | } |
duke@435 | 276 | |
duke@435 | 277 | //------------------------------------------------------------------- |
duke@435 | 278 | |
duke@435 | 279 | void NativeLoadAddress::verify() { |
duke@435 | 280 | // make sure code pattern is actually a mov [reg+offset], reg instruction |
duke@435 | 281 | u_char test_byte = *(u_char*)instruction_address(); |
duke@435 | 282 | if ( ! (test_byte == instruction_code) ) { |
duke@435 | 283 | fatal ("not a lea reg, [reg+offs] instruction"); |
duke@435 | 284 | } |
duke@435 | 285 | } |
duke@435 | 286 | |
duke@435 | 287 | |
duke@435 | 288 | void NativeLoadAddress::print() { |
duke@435 | 289 | tty->print_cr("0x%x: lea [reg + %x], reg", instruction_address(), offset()); |
duke@435 | 290 | } |
duke@435 | 291 | |
duke@435 | 292 | #endif // !AMD64 |
duke@435 | 293 | |
duke@435 | 294 | //-------------------------------------------------------------------------------- |
duke@435 | 295 | |
duke@435 | 296 | void NativeJump::verify() { |
duke@435 | 297 | if (*(u_char*)instruction_address() != instruction_code) { |
duke@435 | 298 | fatal("not a jump instruction"); |
duke@435 | 299 | } |
duke@435 | 300 | } |
duke@435 | 301 | |
duke@435 | 302 | |
duke@435 | 303 | void NativeJump::insert(address code_pos, address entry) { |
duke@435 | 304 | intptr_t disp = (intptr_t)entry - ((intptr_t)code_pos + 1 + 4); |
duke@435 | 305 | #ifdef AMD64 |
duke@435 | 306 | guarantee(disp == (intptr_t)(int32_t)disp, "must be 32-bit offset"); |
duke@435 | 307 | #endif // AMD64 |
duke@435 | 308 | |
duke@435 | 309 | *code_pos = instruction_code; |
duke@435 | 310 | *((int32_t*)(code_pos + 1)) = (int32_t)disp; |
duke@435 | 311 | |
duke@435 | 312 | ICache::invalidate_range(code_pos, instruction_size); |
duke@435 | 313 | } |
duke@435 | 314 | |
duke@435 | 315 | void NativeJump::check_verified_entry_alignment(address entry, address verified_entry) { |
duke@435 | 316 | // Patching to not_entrant can happen while activations of the method are |
duke@435 | 317 | // in use. The patching in that instance must happen only when certain |
duke@435 | 318 | // alignment restrictions are true. These guarantees check those |
duke@435 | 319 | // conditions. |
duke@435 | 320 | #ifdef AMD64 |
duke@435 | 321 | const int linesize = 64; |
duke@435 | 322 | #else |
duke@435 | 323 | const int linesize = 32; |
duke@435 | 324 | #endif // AMD64 |
duke@435 | 325 | |
duke@435 | 326 | // Must be wordSize aligned |
duke@435 | 327 | guarantee(((uintptr_t) verified_entry & (wordSize -1)) == 0, |
duke@435 | 328 | "illegal address for code patching 2"); |
duke@435 | 329 | // First 5 bytes must be within the same cache line - 4827828 |
duke@435 | 330 | guarantee((uintptr_t) verified_entry / linesize == |
duke@435 | 331 | ((uintptr_t) verified_entry + 4) / linesize, |
duke@435 | 332 | "illegal address for code patching 3"); |
duke@435 | 333 | } |
duke@435 | 334 | |
duke@435 | 335 | |
duke@435 | 336 | // MT safe inserting of a jump over an unknown instruction sequence (used by nmethod::makeZombie) |
duke@435 | 337 | // The problem: jmp <dest> is a 5-byte instruction. Atomical write can be only with 4 bytes. |
duke@435 | 338 | // First patches the first word atomically to be a jump to itself. |
duke@435 | 339 | // Then patches the last byte and then atomically patches the first word (4-bytes), |
duke@435 | 340 | // thus inserting the desired jump |
duke@435 | 341 | // This code is mt-safe with the following conditions: entry point is 4 byte aligned, |
duke@435 | 342 | // entry point is in same cache line as unverified entry point, and the instruction being |
duke@435 | 343 | // patched is >= 5 byte (size of patch). |
duke@435 | 344 | // |
duke@435 | 345 | // In C2 the 5+ byte sized instruction is enforced by code in MachPrologNode::emit. |
duke@435 | 346 | // In C1 the restriction is enforced by CodeEmitter::method_entry |
duke@435 | 347 | // |
duke@435 | 348 | void NativeJump::patch_verified_entry(address entry, address verified_entry, address dest) { |
duke@435 | 349 | // complete jump instruction (to be inserted) is in code_buffer; |
duke@435 | 350 | unsigned char code_buffer[5]; |
duke@435 | 351 | code_buffer[0] = instruction_code; |
duke@435 | 352 | intptr_t disp = (intptr_t)dest - ((intptr_t)verified_entry + 1 + 4); |
duke@435 | 353 | #ifdef AMD64 |
duke@435 | 354 | guarantee(disp == (intptr_t)(int32_t)disp, "must be 32-bit offset"); |
duke@435 | 355 | #endif // AMD64 |
duke@435 | 356 | *(int32_t*)(code_buffer + 1) = (int32_t)disp; |
duke@435 | 357 | |
duke@435 | 358 | check_verified_entry_alignment(entry, verified_entry); |
duke@435 | 359 | |
duke@435 | 360 | // Can't call nativeJump_at() because it's asserts jump exists |
duke@435 | 361 | NativeJump* n_jump = (NativeJump*) verified_entry; |
duke@435 | 362 | |
duke@435 | 363 | //First patch dummy jmp in place |
duke@435 | 364 | |
duke@435 | 365 | unsigned char patch[4]; |
duke@435 | 366 | assert(sizeof(patch)==sizeof(int32_t), "sanity check"); |
duke@435 | 367 | patch[0] = 0xEB; // jmp rel8 |
duke@435 | 368 | patch[1] = 0xFE; // jmp to self |
duke@435 | 369 | patch[2] = 0xEB; |
duke@435 | 370 | patch[3] = 0xFE; |
duke@435 | 371 | |
duke@435 | 372 | // First patch dummy jmp in place |
duke@435 | 373 | *(int32_t*)verified_entry = *(int32_t *)patch; |
duke@435 | 374 | |
duke@435 | 375 | n_jump->wrote(0); |
duke@435 | 376 | |
duke@435 | 377 | // Patch 5th byte (from jump instruction) |
duke@435 | 378 | verified_entry[4] = code_buffer[4]; |
duke@435 | 379 | |
duke@435 | 380 | n_jump->wrote(4); |
duke@435 | 381 | |
duke@435 | 382 | // Patch bytes 0-3 (from jump instruction) |
duke@435 | 383 | *(int32_t*)verified_entry = *(int32_t *)code_buffer; |
duke@435 | 384 | // Invalidate. Opteron requires a flush after every write. |
duke@435 | 385 | n_jump->wrote(0); |
duke@435 | 386 | |
duke@435 | 387 | } |
duke@435 | 388 | |
duke@435 | 389 | void NativePopReg::insert(address code_pos, Register reg) { |
duke@435 | 390 | assert(reg->encoding() < 8, "no space for REX"); |
duke@435 | 391 | assert(NativePopReg::instruction_size == sizeof(char), "right address unit for update"); |
duke@435 | 392 | *code_pos = (u_char)(instruction_code | reg->encoding()); |
duke@435 | 393 | ICache::invalidate_range(code_pos, instruction_size); |
duke@435 | 394 | } |
duke@435 | 395 | |
duke@435 | 396 | |
duke@435 | 397 | void NativeIllegalInstruction::insert(address code_pos) { |
duke@435 | 398 | assert(NativeIllegalInstruction::instruction_size == sizeof(short), "right address unit for update"); |
duke@435 | 399 | *(short *)code_pos = instruction_code; |
duke@435 | 400 | ICache::invalidate_range(code_pos, instruction_size); |
duke@435 | 401 | } |
duke@435 | 402 | |
duke@435 | 403 | void NativeGeneralJump::verify() { |
duke@435 | 404 | assert(((NativeInstruction *)this)->is_jump() || |
duke@435 | 405 | ((NativeInstruction *)this)->is_cond_jump(), "not a general jump instruction"); |
duke@435 | 406 | } |
duke@435 | 407 | |
duke@435 | 408 | |
duke@435 | 409 | void NativeGeneralJump::insert_unconditional(address code_pos, address entry) { |
duke@435 | 410 | intptr_t disp = (intptr_t)entry - ((intptr_t)code_pos + 1 + 4); |
duke@435 | 411 | #ifdef AMD64 |
duke@435 | 412 | guarantee(disp == (intptr_t)(int32_t)disp, "must be 32-bit offset"); |
duke@435 | 413 | #endif // AMD64 |
duke@435 | 414 | |
duke@435 | 415 | *code_pos = unconditional_long_jump; |
duke@435 | 416 | *((int32_t *)(code_pos+1)) = (int32_t) disp; |
duke@435 | 417 | ICache::invalidate_range(code_pos, instruction_size); |
duke@435 | 418 | } |
duke@435 | 419 | |
duke@435 | 420 | |
duke@435 | 421 | // MT-safe patching of a long jump instruction. |
duke@435 | 422 | // First patches first word of instruction to two jmp's that jmps to them |
duke@435 | 423 | // selfs (spinlock). Then patches the last byte, and then atomicly replaces |
duke@435 | 424 | // the jmp's with the first 4 byte of the new instruction. |
duke@435 | 425 | void NativeGeneralJump::replace_mt_safe(address instr_addr, address code_buffer) { |
duke@435 | 426 | assert (instr_addr != NULL, "illegal address for code patching (4)"); |
duke@435 | 427 | NativeGeneralJump* n_jump = nativeGeneralJump_at (instr_addr); // checking that it is a jump |
duke@435 | 428 | |
duke@435 | 429 | // Temporary code |
duke@435 | 430 | unsigned char patch[4]; |
duke@435 | 431 | assert(sizeof(patch)==sizeof(int32_t), "sanity check"); |
duke@435 | 432 | patch[0] = 0xEB; // jmp rel8 |
duke@435 | 433 | patch[1] = 0xFE; // jmp to self |
duke@435 | 434 | patch[2] = 0xEB; |
duke@435 | 435 | patch[3] = 0xFE; |
duke@435 | 436 | |
duke@435 | 437 | // First patch dummy jmp in place |
duke@435 | 438 | *(int32_t*)instr_addr = *(int32_t *)patch; |
duke@435 | 439 | n_jump->wrote(0); |
duke@435 | 440 | |
duke@435 | 441 | // Patch 4th byte |
duke@435 | 442 | instr_addr[4] = code_buffer[4]; |
duke@435 | 443 | |
duke@435 | 444 | n_jump->wrote(4); |
duke@435 | 445 | |
duke@435 | 446 | // Patch bytes 0-3 |
duke@435 | 447 | *(jint*)instr_addr = *(jint *)code_buffer; |
duke@435 | 448 | |
duke@435 | 449 | n_jump->wrote(0); |
duke@435 | 450 | |
duke@435 | 451 | #ifdef ASSERT |
duke@435 | 452 | // verify patching |
duke@435 | 453 | for ( int i = 0; i < instruction_size; i++) { |
duke@435 | 454 | address ptr = (address)((intptr_t)code_buffer + i); |
duke@435 | 455 | int a_byte = (*ptr) & 0xFF; |
duke@435 | 456 | assert(*((address)((intptr_t)instr_addr + i)) == a_byte, "mt safe patching failed"); |
duke@435 | 457 | } |
duke@435 | 458 | #endif |
duke@435 | 459 | |
duke@435 | 460 | } |
duke@435 | 461 | |
duke@435 | 462 | |
duke@435 | 463 | |
duke@435 | 464 | address NativeGeneralJump::jump_destination() const { |
duke@435 | 465 | int op_code = ubyte_at(0); |
duke@435 | 466 | bool is_rel32off = (op_code == 0xE9 || op_code == 0x0F); |
duke@435 | 467 | int offset = (op_code == 0x0F) ? 2 : 1; |
duke@435 | 468 | int length = offset + ((is_rel32off) ? 4 : 1); |
duke@435 | 469 | |
duke@435 | 470 | if (is_rel32off) |
duke@435 | 471 | return addr_at(0) + length + int_at(offset); |
duke@435 | 472 | else |
duke@435 | 473 | return addr_at(0) + length + sbyte_at(offset); |
duke@435 | 474 | } |
kamg@551 | 475 | |
kamg@551 | 476 | bool NativeInstruction::is_dtrace_trap() { |
kamg@551 | 477 | return (*(int32_t*)this & 0xff) == 0xcc; |
kamg@551 | 478 | } |