Wed, 18 Sep 2013 14:34:56 -0700
8024342: PPC64 (part 111): Support for C calling conventions that require 64-bit ints.
Summary: Some platforms, as ppc and s390x/zArch require that 32-bit ints are passed as 64-bit values to C functions. This change adds support to adapt the signature and to issue proper casts to c2-compiled stubs. The functions are used in generate_native_wrapper(). Adapt signature used by the compiler as in PhaseIdealLoop::intrinsify_fill().
Reviewed-by: kvn
duke@435 | 1 | /* |
kvn@3882 | 2 | * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved. |
duke@435 | 3 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
duke@435 | 4 | * |
duke@435 | 5 | * This code is free software; you can redistribute it and/or modify it |
duke@435 | 6 | * under the terms of the GNU General Public License version 2 only, as |
duke@435 | 7 | * published by the Free Software Foundation. |
duke@435 | 8 | * |
duke@435 | 9 | * This code is distributed in the hope that it will be useful, but WITHOUT |
duke@435 | 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
duke@435 | 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
duke@435 | 12 | * version 2 for more details (a copy is included in the LICENSE file that |
duke@435 | 13 | * accompanied this code). |
duke@435 | 14 | * |
duke@435 | 15 | * You should have received a copy of the GNU General Public License version |
duke@435 | 16 | * 2 along with this work; if not, write to the Free Software Foundation, |
duke@435 | 17 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
duke@435 | 18 | * |
trims@1907 | 19 | * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
trims@1907 | 20 | * or visit www.oracle.com if you need additional information or have any |
trims@1907 | 21 | * questions. |
duke@435 | 22 | * |
duke@435 | 23 | */ |
duke@435 | 24 | |
stefank@2314 | 25 | #ifndef SHARE_VM_OPTO_MATCHER_HPP |
stefank@2314 | 26 | #define SHARE_VM_OPTO_MATCHER_HPP |
stefank@2314 | 27 | |
stefank@2314 | 28 | #include "libadt/vectset.hpp" |
stefank@2314 | 29 | #include "memory/resourceArea.hpp" |
stefank@2314 | 30 | #include "opto/node.hpp" |
stefank@2314 | 31 | #include "opto/phaseX.hpp" |
stefank@2314 | 32 | #include "opto/regmask.hpp" |
stefank@2314 | 33 | |
duke@435 | 34 | class Compile; |
duke@435 | 35 | class Node; |
duke@435 | 36 | class MachNode; |
duke@435 | 37 | class MachTypeNode; |
duke@435 | 38 | class MachOper; |
duke@435 | 39 | |
duke@435 | 40 | //---------------------------Matcher------------------------------------------- |
duke@435 | 41 | class Matcher : public PhaseTransform { |
duke@435 | 42 | friend class VMStructs; |
duke@435 | 43 | // Private arena of State objects |
duke@435 | 44 | ResourceArea _states_arena; |
duke@435 | 45 | |
duke@435 | 46 | VectorSet _visited; // Visit bits |
duke@435 | 47 | |
duke@435 | 48 | // Used to control the Label pass |
duke@435 | 49 | VectorSet _shared; // Shared Ideal Node |
duke@435 | 50 | VectorSet _dontcare; // Nothing the matcher cares about |
duke@435 | 51 | |
duke@435 | 52 | // Private methods which perform the actual matching and reduction |
duke@435 | 53 | // Walks the label tree, generating machine nodes |
duke@435 | 54 | MachNode *ReduceInst( State *s, int rule, Node *&mem); |
duke@435 | 55 | void ReduceInst_Chain_Rule( State *s, int rule, Node *&mem, MachNode *mach); |
duke@435 | 56 | uint ReduceInst_Interior(State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds); |
duke@435 | 57 | void ReduceOper( State *s, int newrule, Node *&mem, MachNode *mach ); |
duke@435 | 58 | |
duke@435 | 59 | // If this node already matched using "rule", return the MachNode for it. |
kvn@603 | 60 | MachNode* find_shared_node(Node* n, uint rule); |
duke@435 | 61 | |
duke@435 | 62 | // Convert a dense opcode number to an expanded rule number |
duke@435 | 63 | const int *_reduceOp; |
duke@435 | 64 | const int *_leftOp; |
duke@435 | 65 | const int *_rightOp; |
duke@435 | 66 | |
duke@435 | 67 | // Map dense opcode number to info on when rule is swallowed constant. |
duke@435 | 68 | const bool *_swallowed; |
duke@435 | 69 | |
duke@435 | 70 | // Map dense rule number to determine if this is an instruction chain rule |
duke@435 | 71 | const uint _begin_inst_chain_rule; |
duke@435 | 72 | const uint _end_inst_chain_rule; |
duke@435 | 73 | |
duke@435 | 74 | // We want to clone constants and possible CmpI-variants. |
duke@435 | 75 | // If we do not clone CmpI, then we can have many instances of |
duke@435 | 76 | // condition codes alive at once. This is OK on some chips and |
duke@435 | 77 | // bad on others. Hence the machine-dependent table lookup. |
duke@435 | 78 | const char *_must_clone; |
duke@435 | 79 | |
duke@435 | 80 | // Find shared Nodes, or Nodes that otherwise are Matcher roots |
duke@435 | 81 | void find_shared( Node *n ); |
duke@435 | 82 | |
duke@435 | 83 | // Debug and profile information for nodes in old space: |
duke@435 | 84 | GrowableArray<Node_Notes*>* _old_node_note_array; |
duke@435 | 85 | |
duke@435 | 86 | // Node labeling iterator for instruction selection |
duke@435 | 87 | Node *Label_Root( const Node *n, State *svec, Node *control, const Node *mem ); |
duke@435 | 88 | |
duke@435 | 89 | Node *transform( Node *dummy ); |
duke@435 | 90 | |
adlertz@5539 | 91 | Node_List _projection_list; // For Machine nodes killing many values |
duke@435 | 92 | |
kvn@603 | 93 | Node_Array _shared_nodes; |
duke@435 | 94 | |
duke@435 | 95 | debug_only(Node_Array _old2new_map;) // Map roots of ideal-trees to machine-roots |
never@657 | 96 | debug_only(Node_Array _new2old_map;) // Maps machine nodes back to ideal |
duke@435 | 97 | |
duke@435 | 98 | // Accessors for the inherited field PhaseTransform::_nodes: |
duke@435 | 99 | void grow_new_node_array(uint idx_limit) { |
duke@435 | 100 | _nodes.map(idx_limit-1, NULL); |
duke@435 | 101 | } |
duke@435 | 102 | bool has_new_node(const Node* n) const { |
duke@435 | 103 | return _nodes.at(n->_idx) != NULL; |
duke@435 | 104 | } |
duke@435 | 105 | Node* new_node(const Node* n) const { |
duke@435 | 106 | assert(has_new_node(n), "set before get"); |
duke@435 | 107 | return _nodes.at(n->_idx); |
duke@435 | 108 | } |
duke@435 | 109 | void set_new_node(const Node* n, Node *nn) { |
duke@435 | 110 | assert(!has_new_node(n), "set only once"); |
duke@435 | 111 | _nodes.map(n->_idx, nn); |
duke@435 | 112 | } |
duke@435 | 113 | |
duke@435 | 114 | #ifdef ASSERT |
duke@435 | 115 | // Make sure only new nodes are reachable from this node |
duke@435 | 116 | void verify_new_nodes_only(Node* root); |
kvn@651 | 117 | |
kvn@651 | 118 | Node* _mem_node; // Ideal memory node consumed by mach node |
duke@435 | 119 | #endif |
duke@435 | 120 | |
kvn@1164 | 121 | // Mach node for ConP #NULL |
kvn@1164 | 122 | MachNode* _mach_null; |
kvn@1164 | 123 | |
duke@435 | 124 | public: |
duke@435 | 125 | int LabelRootDepth; |
duke@435 | 126 | // Convert ideal machine register to a register mask for spill-loads |
duke@435 | 127 | static const RegMask *idealreg2regmask[]; |
twisti@1572 | 128 | RegMask *idealreg2spillmask [_last_machine_leaf]; |
twisti@1572 | 129 | RegMask *idealreg2debugmask [_last_machine_leaf]; |
twisti@1572 | 130 | RegMask *idealreg2mhdebugmask[_last_machine_leaf]; |
duke@435 | 131 | void init_spill_mask( Node *ret ); |
duke@435 | 132 | // Convert machine register number to register mask |
duke@435 | 133 | static uint mreg2regmask_max; |
duke@435 | 134 | static RegMask mreg2regmask[]; |
duke@435 | 135 | static RegMask STACK_ONLY_mask; |
duke@435 | 136 | |
kvn@1164 | 137 | MachNode* mach_null() const { return _mach_null; } |
kvn@1164 | 138 | |
duke@435 | 139 | bool is_shared( Node *n ) { return _shared.test(n->_idx) != 0; } |
duke@435 | 140 | void set_shared( Node *n ) { _shared.set(n->_idx); } |
duke@435 | 141 | bool is_visited( Node *n ) { return _visited.test(n->_idx) != 0; } |
duke@435 | 142 | void set_visited( Node *n ) { _visited.set(n->_idx); } |
duke@435 | 143 | bool is_dontcare( Node *n ) { return _dontcare.test(n->_idx) != 0; } |
duke@435 | 144 | void set_dontcare( Node *n ) { _dontcare.set(n->_idx); } |
duke@435 | 145 | |
duke@435 | 146 | // Mode bit to tell DFA and expand rules whether we are running after |
duke@435 | 147 | // (or during) register selection. Usually, the matcher runs before, |
duke@435 | 148 | // but it will also get called to generate post-allocation spill code. |
duke@435 | 149 | // In this situation, it is a deadly error to attempt to allocate more |
duke@435 | 150 | // temporary registers. |
duke@435 | 151 | bool _allocation_started; |
duke@435 | 152 | |
duke@435 | 153 | // Machine register names |
duke@435 | 154 | static const char *regName[]; |
duke@435 | 155 | // Machine register encodings |
duke@435 | 156 | static const unsigned char _regEncode[]; |
duke@435 | 157 | // Machine Node names |
duke@435 | 158 | const char **_ruleName; |
duke@435 | 159 | // Rules that are cheaper to rematerialize than to spill |
duke@435 | 160 | static const uint _begin_rematerialize; |
duke@435 | 161 | static const uint _end_rematerialize; |
duke@435 | 162 | |
duke@435 | 163 | // An array of chars, from 0 to _last_Mach_Reg. |
duke@435 | 164 | // No Save = 'N' (for register windows) |
duke@435 | 165 | // Save on Entry = 'E' |
duke@435 | 166 | // Save on Call = 'C' |
duke@435 | 167 | // Always Save = 'A' (same as SOE + SOC) |
duke@435 | 168 | const char *_register_save_policy; |
duke@435 | 169 | const char *_c_reg_save_policy; |
duke@435 | 170 | // Convert a machine register to a machine register type, so-as to |
duke@435 | 171 | // properly match spill code. |
duke@435 | 172 | const int *_register_save_type; |
duke@435 | 173 | // Maps from machine register to boolean; true if machine register can |
duke@435 | 174 | // be holding a call argument in some signature. |
duke@435 | 175 | static bool can_be_java_arg( int reg ); |
duke@435 | 176 | // Maps from machine register to boolean; true if machine register holds |
duke@435 | 177 | // a spillable argument. |
duke@435 | 178 | static bool is_spillable_arg( int reg ); |
duke@435 | 179 | |
duke@435 | 180 | // List of IfFalse or IfTrue Nodes that indicate a taken null test. |
duke@435 | 181 | // List is valid in the post-matching space. |
duke@435 | 182 | Node_List _null_check_tests; |
kvn@803 | 183 | void collect_null_checks( Node *proj, Node *orig_proj ); |
duke@435 | 184 | void validate_null_checks( ); |
duke@435 | 185 | |
adlertz@5539 | 186 | Matcher(); |
adlertz@5539 | 187 | |
adlertz@5539 | 188 | // Get a projection node at position pos |
adlertz@5539 | 189 | Node* get_projection(uint pos) { |
adlertz@5539 | 190 | return _projection_list[pos]; |
adlertz@5539 | 191 | } |
adlertz@5539 | 192 | |
adlertz@5539 | 193 | // Push a projection node onto the projection list |
adlertz@5539 | 194 | void push_projection(Node* node) { |
adlertz@5539 | 195 | _projection_list.push(node); |
adlertz@5539 | 196 | } |
adlertz@5539 | 197 | |
adlertz@5539 | 198 | Node* pop_projection() { |
adlertz@5539 | 199 | return _projection_list.pop(); |
adlertz@5539 | 200 | } |
adlertz@5539 | 201 | |
adlertz@5539 | 202 | // Number of nodes in the projection list |
adlertz@5539 | 203 | uint number_of_projections() const { |
adlertz@5539 | 204 | return _projection_list.size(); |
adlertz@5539 | 205 | } |
duke@435 | 206 | |
duke@435 | 207 | // Select instructions for entire method |
adlertz@5539 | 208 | void match(); |
adlertz@5539 | 209 | |
duke@435 | 210 | // Helper for match |
duke@435 | 211 | OptoReg::Name warp_incoming_stk_arg( VMReg reg ); |
duke@435 | 212 | |
duke@435 | 213 | // Transform, then walk. Does implicit DCE while walking. |
duke@435 | 214 | // Name changed from "transform" to avoid it being virtual. |
duke@435 | 215 | Node *xform( Node *old_space_node, int Nodes ); |
duke@435 | 216 | |
duke@435 | 217 | // Match a single Ideal Node - turn it into a 1-Node tree; Label & Reduce. |
duke@435 | 218 | MachNode *match_tree( const Node *n ); |
duke@435 | 219 | MachNode *match_sfpt( SafePointNode *sfpt ); |
duke@435 | 220 | // Helper for match_sfpt |
duke@435 | 221 | OptoReg::Name warp_outgoing_stk_arg( VMReg reg, OptoReg::Name begin_out_arg_area, OptoReg::Name &out_arg_limit_per_call ); |
duke@435 | 222 | |
duke@435 | 223 | // Initialize first stack mask and related masks. |
duke@435 | 224 | void init_first_stack_mask(); |
duke@435 | 225 | |
duke@435 | 226 | // If we should save-on-entry this register |
duke@435 | 227 | bool is_save_on_entry( int reg ); |
duke@435 | 228 | |
duke@435 | 229 | // Fixup the save-on-entry registers |
duke@435 | 230 | void Fixup_Save_On_Entry( ); |
duke@435 | 231 | |
duke@435 | 232 | // --- Frame handling --- |
duke@435 | 233 | |
duke@435 | 234 | // Register number of the stack slot corresponding to the incoming SP. |
duke@435 | 235 | // Per the Big Picture in the AD file, it is: |
duke@435 | 236 | // SharedInfo::stack0 + locks + in_preserve_stack_slots + pad2. |
duke@435 | 237 | OptoReg::Name _old_SP; |
duke@435 | 238 | |
duke@435 | 239 | // Register number of the stack slot corresponding to the highest incoming |
duke@435 | 240 | // argument on the stack. Per the Big Picture in the AD file, it is: |
duke@435 | 241 | // _old_SP + out_preserve_stack_slots + incoming argument size. |
duke@435 | 242 | OptoReg::Name _in_arg_limit; |
duke@435 | 243 | |
duke@435 | 244 | // Register number of the stack slot corresponding to the new SP. |
duke@435 | 245 | // Per the Big Picture in the AD file, it is: |
duke@435 | 246 | // _in_arg_limit + pad0 |
duke@435 | 247 | OptoReg::Name _new_SP; |
duke@435 | 248 | |
duke@435 | 249 | // Register number of the stack slot corresponding to the highest outgoing |
duke@435 | 250 | // argument on the stack. Per the Big Picture in the AD file, it is: |
duke@435 | 251 | // _new_SP + max outgoing arguments of all calls |
duke@435 | 252 | OptoReg::Name _out_arg_limit; |
duke@435 | 253 | |
duke@435 | 254 | OptoRegPair *_parm_regs; // Array of machine registers per argument |
duke@435 | 255 | RegMask *_calling_convention_mask; // Array of RegMasks per argument |
duke@435 | 256 | |
twisti@1210 | 257 | // Does matcher have a match rule for this ideal node? |
duke@435 | 258 | static const bool has_match_rule(int opcode); |
duke@435 | 259 | static const bool _hasMatchRule[_last_opcode]; |
duke@435 | 260 | |
twisti@1210 | 261 | // Does matcher have a match rule for this ideal node and is the |
twisti@1210 | 262 | // predicate (if there is one) true? |
twisti@1210 | 263 | // NOTE: If this function is used more commonly in the future, ADLC |
twisti@1210 | 264 | // should generate this one. |
twisti@1210 | 265 | static const bool match_rule_supported(int opcode); |
twisti@1210 | 266 | |
duke@435 | 267 | // Used to determine if we have fast l2f conversion |
duke@435 | 268 | // USII has it, USIII doesn't |
duke@435 | 269 | static const bool convL2FSupported(void); |
duke@435 | 270 | |
duke@435 | 271 | // Vector width in bytes |
kvn@3882 | 272 | static const int vector_width_in_bytes(BasicType bt); |
kvn@3882 | 273 | |
kvn@3882 | 274 | // Limits on vector size (number of elements). |
kvn@3882 | 275 | static const int max_vector_size(const BasicType bt); |
kvn@3882 | 276 | static const int min_vector_size(const BasicType bt); |
kvn@3882 | 277 | static const bool vector_size_supported(const BasicType bt, int size) { |
kvn@3882 | 278 | return (Matcher::max_vector_size(bt) >= size && |
kvn@3882 | 279 | Matcher::min_vector_size(bt) <= size); |
kvn@3882 | 280 | } |
duke@435 | 281 | |
duke@435 | 282 | // Vector ideal reg |
kvn@3882 | 283 | static const int vector_ideal_reg(int len); |
kvn@4134 | 284 | static const int vector_shift_count_ideal_reg(int len); |
kvn@3882 | 285 | |
kvn@3882 | 286 | // CPU supports misaligned vectors store/load. |
kvn@3882 | 287 | static const bool misaligned_vectors_ok(); |
duke@435 | 288 | |
duke@435 | 289 | // Used to determine a "low complexity" 64-bit constant. (Zero is simple.) |
duke@435 | 290 | // The standard of comparison is one (StoreL ConL) vs. two (StoreI ConI). |
duke@435 | 291 | // Depends on the details of 64-bit constant generation on the CPU. |
duke@435 | 292 | static const bool isSimpleConstant64(jlong con); |
duke@435 | 293 | |
duke@435 | 294 | // These calls are all generated by the ADLC |
duke@435 | 295 | |
duke@435 | 296 | // TRUE - grows up, FALSE - grows down (Intel) |
duke@435 | 297 | virtual bool stack_direction() const; |
duke@435 | 298 | |
duke@435 | 299 | // Java-Java calling convention |
duke@435 | 300 | // (what you use when Java calls Java) |
duke@435 | 301 | |
duke@435 | 302 | // Alignment of stack in bytes, standard Intel word alignment is 4. |
duke@435 | 303 | // Sparc probably wants at least double-word (8). |
duke@435 | 304 | static uint stack_alignment_in_bytes(); |
duke@435 | 305 | // Alignment of stack, measured in stack slots. |
duke@435 | 306 | // The size of stack slots is defined by VMRegImpl::stack_slot_size. |
duke@435 | 307 | static uint stack_alignment_in_slots() { |
duke@435 | 308 | return stack_alignment_in_bytes() / (VMRegImpl::stack_slot_size); |
duke@435 | 309 | } |
duke@435 | 310 | |
duke@435 | 311 | // Array mapping arguments to registers. Argument 0 is usually the 'this' |
duke@435 | 312 | // pointer. Registers can include stack-slots and regular registers. |
duke@435 | 313 | static void calling_convention( BasicType *, VMRegPair *, uint len, bool is_outgoing ); |
duke@435 | 314 | |
duke@435 | 315 | // Convert a sig into a calling convention register layout |
duke@435 | 316 | // and find interesting things about it. |
duke@435 | 317 | static OptoReg::Name find_receiver( bool is_outgoing ); |
duke@435 | 318 | // Return address register. On Intel it is a stack-slot. On PowerPC |
duke@435 | 319 | // it is the Link register. On Sparc it is r31? |
duke@435 | 320 | virtual OptoReg::Name return_addr() const; |
duke@435 | 321 | RegMask _return_addr_mask; |
duke@435 | 322 | // Return value register. On Intel it is EAX. On Sparc i0/o0. |
duke@435 | 323 | static OptoRegPair return_value(int ideal_reg, bool is_outgoing); |
duke@435 | 324 | static OptoRegPair c_return_value(int ideal_reg, bool is_outgoing); |
duke@435 | 325 | RegMask _return_value_mask; |
duke@435 | 326 | // Inline Cache Register |
duke@435 | 327 | static OptoReg::Name inline_cache_reg(); |
duke@435 | 328 | static int inline_cache_reg_encode(); |
duke@435 | 329 | |
duke@435 | 330 | // Register for DIVI projection of divmodI |
duke@435 | 331 | static RegMask divI_proj_mask(); |
duke@435 | 332 | // Register for MODI projection of divmodI |
duke@435 | 333 | static RegMask modI_proj_mask(); |
duke@435 | 334 | |
duke@435 | 335 | // Register for DIVL projection of divmodL |
duke@435 | 336 | static RegMask divL_proj_mask(); |
duke@435 | 337 | // Register for MODL projection of divmodL |
duke@435 | 338 | static RegMask modL_proj_mask(); |
duke@435 | 339 | |
kvn@2269 | 340 | // Use hardware DIV instruction when it is faster than |
kvn@2269 | 341 | // a code which use multiply for division by constant. |
kvn@2269 | 342 | static bool use_asm_for_ldiv_by_con( jlong divisor ); |
kvn@2269 | 343 | |
twisti@1572 | 344 | static const RegMask method_handle_invoke_SP_save_mask(); |
twisti@1572 | 345 | |
duke@435 | 346 | // Java-Interpreter calling convention |
duke@435 | 347 | // (what you use when calling between compiled-Java and Interpreted-Java |
duke@435 | 348 | |
duke@435 | 349 | // Number of callee-save + always-save registers |
duke@435 | 350 | // Ignores frame pointer and "special" registers |
duke@435 | 351 | static int number_of_saved_registers(); |
duke@435 | 352 | |
duke@435 | 353 | // The Method-klass-holder may be passed in the inline_cache_reg |
duke@435 | 354 | // and then expanded into the inline_cache_reg and a method_oop register |
duke@435 | 355 | |
duke@435 | 356 | static OptoReg::Name interpreter_method_oop_reg(); |
duke@435 | 357 | static int interpreter_method_oop_reg_encode(); |
duke@435 | 358 | |
duke@435 | 359 | static OptoReg::Name compiler_method_oop_reg(); |
duke@435 | 360 | static const RegMask &compiler_method_oop_reg_mask(); |
duke@435 | 361 | static int compiler_method_oop_reg_encode(); |
duke@435 | 362 | |
duke@435 | 363 | // Interpreter's Frame Pointer Register |
duke@435 | 364 | static OptoReg::Name interpreter_frame_pointer_reg(); |
duke@435 | 365 | |
duke@435 | 366 | // Java-Native calling convention |
duke@435 | 367 | // (what you use when intercalling between Java and C++ code) |
duke@435 | 368 | |
duke@435 | 369 | // Array mapping arguments to registers. Argument 0 is usually the 'this' |
duke@435 | 370 | // pointer. Registers can include stack-slots and regular registers. |
duke@435 | 371 | static void c_calling_convention( BasicType*, VMRegPair *, uint ); |
duke@435 | 372 | // Frame pointer. The frame pointer is kept at the base of the stack |
duke@435 | 373 | // and so is probably the stack pointer for most machines. On Intel |
duke@435 | 374 | // it is ESP. On the PowerPC it is R1. On Sparc it is SP. |
duke@435 | 375 | OptoReg::Name c_frame_pointer() const; |
duke@435 | 376 | static RegMask c_frame_ptr_mask; |
duke@435 | 377 | |
duke@435 | 378 | // !!!!! Special stuff for building ScopeDescs |
duke@435 | 379 | virtual int regnum_to_fpu_offset(int regnum); |
duke@435 | 380 | |
duke@435 | 381 | // Is this branch offset small enough to be addressed by a short branch? |
kvn@3049 | 382 | bool is_short_branch_offset(int rule, int br_size, int offset); |
duke@435 | 383 | |
duke@435 | 384 | // Optional scaling for the parameter to the ClearArray/CopyArray node. |
duke@435 | 385 | static const bool init_array_count_is_in_bytes; |
duke@435 | 386 | |
duke@435 | 387 | // Threshold small size (in bytes) for a ClearArray/CopyArray node. |
duke@435 | 388 | // Anything this size or smaller may get converted to discrete scalar stores. |
duke@435 | 389 | static const int init_array_short_size; |
duke@435 | 390 | |
kvn@3243 | 391 | // Some hardware needs 2 CMOV's for longs. |
kvn@3243 | 392 | static const int long_cmove_cost(); |
kvn@3243 | 393 | |
kvn@3243 | 394 | // Some hardware have expensive CMOV for float and double. |
kvn@3243 | 395 | static const int float_cmove_cost(); |
kvn@3243 | 396 | |
duke@435 | 397 | // Should the Matcher clone shifts on addressing modes, expecting them to |
duke@435 | 398 | // be subsumed into complex addressing expressions or compute them into |
duke@435 | 399 | // registers? True for Intel but false for most RISCs |
duke@435 | 400 | static const bool clone_shift_expressions; |
duke@435 | 401 | |
kvn@1930 | 402 | static bool narrow_oop_use_complex_address(); |
roland@4159 | 403 | static bool narrow_klass_use_complex_address(); |
kvn@1930 | 404 | |
kvn@1930 | 405 | // Generate implicit null check for narrow oops if it can fold |
kvn@1930 | 406 | // into address expression (x64). |
kvn@1930 | 407 | // |
kvn@1930 | 408 | // [R12 + narrow_oop_reg<<3 + offset] // fold into address expression |
kvn@1930 | 409 | // NullCheck narrow_oop_reg |
kvn@1930 | 410 | // |
kvn@1930 | 411 | // When narrow oops can't fold into address expression (Sparc) and |
kvn@1930 | 412 | // base is not null use decode_not_null and normal implicit null check. |
kvn@1930 | 413 | // Note, decode_not_null node can be used here since it is referenced |
kvn@1930 | 414 | // only on non null path but it requires special handling, see |
kvn@1930 | 415 | // collect_null_checks(): |
kvn@1930 | 416 | // |
kvn@1930 | 417 | // decode_not_null narrow_oop_reg, oop_reg // 'shift' and 'add base' |
kvn@1930 | 418 | // [oop_reg + offset] |
kvn@1930 | 419 | // NullCheck oop_reg |
kvn@1930 | 420 | // |
kvn@1930 | 421 | // With Zero base and when narrow oops can not fold into address |
kvn@1930 | 422 | // expression use normal implicit null check since only shift |
kvn@1930 | 423 | // is needed to decode narrow oop. |
kvn@1930 | 424 | // |
kvn@1930 | 425 | // decode narrow_oop_reg, oop_reg // only 'shift' |
kvn@1930 | 426 | // [oop_reg + offset] |
kvn@1930 | 427 | // NullCheck oop_reg |
kvn@1930 | 428 | // |
kvn@1930 | 429 | inline static bool gen_narrow_oop_implicit_null_checks() { |
kvn@1930 | 430 | return Universe::narrow_oop_use_implicit_null_checks() && |
kvn@1930 | 431 | (narrow_oop_use_complex_address() || |
kvn@1930 | 432 | Universe::narrow_oop_base() != NULL); |
kvn@1930 | 433 | } |
kvn@1930 | 434 | |
duke@435 | 435 | // Is it better to copy float constants, or load them directly from memory? |
duke@435 | 436 | // Intel can load a float constant from a direct address, requiring no |
duke@435 | 437 | // extra registers. Most RISCs will have to materialize an address into a |
duke@435 | 438 | // register first, so they may as well materialize the constant immediately. |
duke@435 | 439 | static const bool rematerialize_float_constants; |
duke@435 | 440 | |
duke@435 | 441 | // If CPU can load and store mis-aligned doubles directly then no fixup is |
duke@435 | 442 | // needed. Else we split the double into 2 integer pieces and move it |
duke@435 | 443 | // piece-by-piece. Only happens when passing doubles into C code or when |
duke@435 | 444 | // calling i2c adapters as the Java calling convention forces doubles to be |
duke@435 | 445 | // aligned. |
duke@435 | 446 | static const bool misaligned_doubles_ok; |
duke@435 | 447 | |
duke@435 | 448 | // Perform a platform dependent implicit null fixup. This is needed |
duke@435 | 449 | // on windows95 to take care of some unusual register constraints. |
duke@435 | 450 | void pd_implicit_null_fixup(MachNode *load, uint idx); |
duke@435 | 451 | |
duke@435 | 452 | // Advertise here if the CPU requires explicit rounding operations |
duke@435 | 453 | // to implement the UseStrictFP mode. |
duke@435 | 454 | static const bool strict_fp_requires_explicit_rounding; |
duke@435 | 455 | |
kvn@1709 | 456 | // Are floats conerted to double when stored to stack during deoptimization? |
kvn@1709 | 457 | static bool float_in_double(); |
duke@435 | 458 | // Do ints take an entire long register or just half? |
duke@435 | 459 | static const bool int_in_long; |
duke@435 | 460 | |
roland@2683 | 461 | // Do the processor's shift instructions only use the low 5/6 bits |
roland@2683 | 462 | // of the count for 32/64 bit ints? If not we need to do the masking |
roland@2683 | 463 | // ourselves. |
roland@2683 | 464 | static const bool need_masked_shift_count; |
roland@2683 | 465 | |
duke@435 | 466 | // This routine is run whenever a graph fails to match. |
duke@435 | 467 | // If it returns, the compiler should bailout to interpreter without error. |
duke@435 | 468 | // In non-product mode, SoftMatchFailure is false to detect non-canonical |
duke@435 | 469 | // graphs. Print a message and exit. |
duke@435 | 470 | static void soft_match_failure() { |
duke@435 | 471 | if( SoftMatchFailure ) return; |
duke@435 | 472 | else { fatal("SoftMatchFailure is not allowed except in product"); } |
duke@435 | 473 | } |
duke@435 | 474 | |
duke@435 | 475 | // Check for a following volatile memory barrier without an |
duke@435 | 476 | // intervening load and thus we don't need a barrier here. We |
duke@435 | 477 | // retain the Node to act as a compiler ordering barrier. |
duke@435 | 478 | static bool post_store_load_barrier(const Node* mb); |
duke@435 | 479 | |
duke@435 | 480 | |
duke@435 | 481 | #ifdef ASSERT |
duke@435 | 482 | void dump_old2new_map(); // machine-independent to machine-dependent |
never@657 | 483 | |
never@657 | 484 | Node* find_old_node(Node* new_node) { |
never@657 | 485 | return _new2old_map[new_node->_idx]; |
never@657 | 486 | } |
duke@435 | 487 | #endif |
duke@435 | 488 | }; |
stefank@2314 | 489 | |
stefank@2314 | 490 | #endif // SHARE_VM_OPTO_MATCHER_HPP |