Wed, 16 Feb 2011 13:30:31 -0800
7013964: openjdk LICENSE file needs rebranding
Reviewed-by: darcy, katleman, jjg
duke@435 | 1 | /* |
jrose@1934 | 2 | * Copyright (c) 1999, 2010, Oracle and/or its affiliates. All rights reserved. |
duke@435 | 3 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
duke@435 | 4 | * |
duke@435 | 5 | * This code is free software; you can redistribute it and/or modify it |
duke@435 | 6 | * under the terms of the GNU General Public License version 2 only, as |
duke@435 | 7 | * published by the Free Software Foundation. |
duke@435 | 8 | * |
duke@435 | 9 | * This code is distributed in the hope that it will be useful, but WITHOUT |
duke@435 | 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
duke@435 | 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
duke@435 | 12 | * version 2 for more details (a copy is included in the LICENSE file that |
duke@435 | 13 | * accompanied this code). |
duke@435 | 14 | * |
duke@435 | 15 | * You should have received a copy of the GNU General Public License version |
duke@435 | 16 | * 2 along with this work; if not, write to the Free Software Foundation, |
duke@435 | 17 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
duke@435 | 18 | * |
trims@1907 | 19 | * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
trims@1907 | 20 | * or visit www.oracle.com if you need additional information or have any |
trims@1907 | 21 | * questions. |
duke@435 | 22 | * |
duke@435 | 23 | */ |
duke@435 | 24 | |
stefank@2314 | 25 | #include "precompiled.hpp" |
stefank@2314 | 26 | #include "c1/c1_FrameMap.hpp" |
stefank@2314 | 27 | #include "c1/c1_LIR.hpp" |
stefank@2314 | 28 | #include "runtime/sharedRuntime.hpp" |
stefank@2314 | 29 | #include "vmreg_x86.inline.hpp" |
duke@435 | 30 | |
duke@435 | 31 | const int FrameMap::pd_c_runtime_reserved_arg_size = 0; |
duke@435 | 32 | |
duke@435 | 33 | LIR_Opr FrameMap::map_to_opr(BasicType type, VMRegPair* reg, bool) { |
duke@435 | 34 | LIR_Opr opr = LIR_OprFact::illegalOpr; |
duke@435 | 35 | VMReg r_1 = reg->first(); |
duke@435 | 36 | VMReg r_2 = reg->second(); |
duke@435 | 37 | if (r_1->is_stack()) { |
duke@435 | 38 | // Convert stack slot to an SP offset |
duke@435 | 39 | // The calling convention does not count the SharedRuntime::out_preserve_stack_slots() value |
duke@435 | 40 | // so we must add it in here. |
duke@435 | 41 | int st_off = (r_1->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size; |
duke@435 | 42 | opr = LIR_OprFact::address(new LIR_Address(rsp_opr, st_off, type)); |
duke@435 | 43 | } else if (r_1->is_Register()) { |
duke@435 | 44 | Register reg = r_1->as_Register(); |
never@739 | 45 | if (r_2->is_Register() && (type == T_LONG || type == T_DOUBLE)) { |
duke@435 | 46 | Register reg2 = r_2->as_Register(); |
never@739 | 47 | #ifdef _LP64 |
never@739 | 48 | assert(reg2 == reg, "must be same register"); |
never@739 | 49 | opr = as_long_opr(reg); |
never@739 | 50 | #else |
duke@435 | 51 | opr = as_long_opr(reg2, reg); |
never@739 | 52 | #endif // _LP64 |
never@739 | 53 | } else if (type == T_OBJECT || type == T_ARRAY) { |
duke@435 | 54 | opr = as_oop_opr(reg); |
duke@435 | 55 | } else { |
duke@435 | 56 | opr = as_opr(reg); |
duke@435 | 57 | } |
duke@435 | 58 | } else if (r_1->is_FloatRegister()) { |
duke@435 | 59 | assert(type == T_DOUBLE || type == T_FLOAT, "wrong type"); |
duke@435 | 60 | int num = r_1->as_FloatRegister()->encoding(); |
duke@435 | 61 | if (type == T_FLOAT) { |
duke@435 | 62 | opr = LIR_OprFact::single_fpu(num); |
duke@435 | 63 | } else { |
duke@435 | 64 | opr = LIR_OprFact::double_fpu(num); |
duke@435 | 65 | } |
duke@435 | 66 | } else if (r_1->is_XMMRegister()) { |
duke@435 | 67 | assert(type == T_DOUBLE || type == T_FLOAT, "wrong type"); |
duke@435 | 68 | int num = r_1->as_XMMRegister()->encoding(); |
duke@435 | 69 | if (type == T_FLOAT) { |
duke@435 | 70 | opr = LIR_OprFact::single_xmm(num); |
duke@435 | 71 | } else { |
duke@435 | 72 | opr = LIR_OprFact::double_xmm(num); |
duke@435 | 73 | } |
duke@435 | 74 | } else { |
duke@435 | 75 | ShouldNotReachHere(); |
duke@435 | 76 | } |
duke@435 | 77 | return opr; |
duke@435 | 78 | } |
duke@435 | 79 | |
duke@435 | 80 | |
duke@435 | 81 | LIR_Opr FrameMap::rsi_opr; |
duke@435 | 82 | LIR_Opr FrameMap::rdi_opr; |
duke@435 | 83 | LIR_Opr FrameMap::rbx_opr; |
duke@435 | 84 | LIR_Opr FrameMap::rax_opr; |
duke@435 | 85 | LIR_Opr FrameMap::rdx_opr; |
duke@435 | 86 | LIR_Opr FrameMap::rcx_opr; |
duke@435 | 87 | LIR_Opr FrameMap::rsp_opr; |
duke@435 | 88 | LIR_Opr FrameMap::rbp_opr; |
duke@435 | 89 | |
duke@435 | 90 | LIR_Opr FrameMap::receiver_opr; |
duke@435 | 91 | |
duke@435 | 92 | LIR_Opr FrameMap::rsi_oop_opr; |
duke@435 | 93 | LIR_Opr FrameMap::rdi_oop_opr; |
duke@435 | 94 | LIR_Opr FrameMap::rbx_oop_opr; |
duke@435 | 95 | LIR_Opr FrameMap::rax_oop_opr; |
duke@435 | 96 | LIR_Opr FrameMap::rdx_oop_opr; |
duke@435 | 97 | LIR_Opr FrameMap::rcx_oop_opr; |
duke@435 | 98 | |
never@739 | 99 | LIR_Opr FrameMap::long0_opr; |
never@739 | 100 | LIR_Opr FrameMap::long1_opr; |
duke@435 | 101 | LIR_Opr FrameMap::fpu0_float_opr; |
duke@435 | 102 | LIR_Opr FrameMap::fpu0_double_opr; |
duke@435 | 103 | LIR_Opr FrameMap::xmm0_float_opr; |
duke@435 | 104 | LIR_Opr FrameMap::xmm0_double_opr; |
duke@435 | 105 | |
never@739 | 106 | #ifdef _LP64 |
never@739 | 107 | |
never@739 | 108 | LIR_Opr FrameMap::r8_opr; |
never@739 | 109 | LIR_Opr FrameMap::r9_opr; |
never@739 | 110 | LIR_Opr FrameMap::r10_opr; |
never@739 | 111 | LIR_Opr FrameMap::r11_opr; |
never@739 | 112 | LIR_Opr FrameMap::r12_opr; |
never@739 | 113 | LIR_Opr FrameMap::r13_opr; |
never@739 | 114 | LIR_Opr FrameMap::r14_opr; |
never@739 | 115 | LIR_Opr FrameMap::r15_opr; |
never@739 | 116 | |
never@739 | 117 | // r10 and r15 can never contain oops since they aren't available to |
never@739 | 118 | // the allocator |
never@739 | 119 | LIR_Opr FrameMap::r8_oop_opr; |
never@739 | 120 | LIR_Opr FrameMap::r9_oop_opr; |
never@739 | 121 | LIR_Opr FrameMap::r11_oop_opr; |
never@739 | 122 | LIR_Opr FrameMap::r12_oop_opr; |
never@739 | 123 | LIR_Opr FrameMap::r13_oop_opr; |
never@739 | 124 | LIR_Opr FrameMap::r14_oop_opr; |
never@739 | 125 | #endif // _LP64 |
never@739 | 126 | |
duke@435 | 127 | LIR_Opr FrameMap::_caller_save_cpu_regs[] = { 0, }; |
duke@435 | 128 | LIR_Opr FrameMap::_caller_save_fpu_regs[] = { 0, }; |
duke@435 | 129 | LIR_Opr FrameMap::_caller_save_xmm_regs[] = { 0, }; |
duke@435 | 130 | |
never@739 | 131 | XMMRegister FrameMap::_xmm_regs [] = { 0, }; |
duke@435 | 132 | |
duke@435 | 133 | XMMRegister FrameMap::nr2xmmreg(int rnr) { |
duke@435 | 134 | assert(_init_done, "tables not initialized"); |
duke@435 | 135 | return _xmm_regs[rnr]; |
duke@435 | 136 | } |
duke@435 | 137 | |
duke@435 | 138 | //-------------------------------------------------------- |
duke@435 | 139 | // FrameMap |
duke@435 | 140 | //-------------------------------------------------------- |
duke@435 | 141 | |
iveresov@1939 | 142 | void FrameMap::initialize() { |
iveresov@1939 | 143 | assert(!_init_done, "once"); |
duke@435 | 144 | |
never@739 | 145 | assert(nof_cpu_regs == LP64_ONLY(16) NOT_LP64(8), "wrong number of CPU registers"); |
never@739 | 146 | map_register(0, rsi); rsi_opr = LIR_OprFact::single_cpu(0); |
never@739 | 147 | map_register(1, rdi); rdi_opr = LIR_OprFact::single_cpu(1); |
never@739 | 148 | map_register(2, rbx); rbx_opr = LIR_OprFact::single_cpu(2); |
never@739 | 149 | map_register(3, rax); rax_opr = LIR_OprFact::single_cpu(3); |
never@739 | 150 | map_register(4, rdx); rdx_opr = LIR_OprFact::single_cpu(4); |
never@739 | 151 | map_register(5, rcx); rcx_opr = LIR_OprFact::single_cpu(5); |
duke@435 | 152 | |
never@739 | 153 | #ifndef _LP64 |
never@739 | 154 | // The unallocatable registers are at the end |
never@739 | 155 | map_register(6, rsp); |
never@739 | 156 | map_register(7, rbp); |
never@739 | 157 | #else |
never@739 | 158 | map_register( 6, r8); r8_opr = LIR_OprFact::single_cpu(6); |
never@739 | 159 | map_register( 7, r9); r9_opr = LIR_OprFact::single_cpu(7); |
never@739 | 160 | map_register( 8, r11); r11_opr = LIR_OprFact::single_cpu(8); |
iveresov@2344 | 161 | map_register( 9, r13); r13_opr = LIR_OprFact::single_cpu(9); |
iveresov@2344 | 162 | map_register(10, r14); r14_opr = LIR_OprFact::single_cpu(10); |
iveresov@2344 | 163 | // r12 is allocated conditionally. With compressed oops it holds |
iveresov@2344 | 164 | // the heapbase value and is not visible to the allocator. |
iveresov@2344 | 165 | map_register(11, r12); r12_opr = LIR_OprFact::single_cpu(11); |
never@739 | 166 | // The unallocatable registers are at the end |
never@739 | 167 | map_register(12, r10); r10_opr = LIR_OprFact::single_cpu(12); |
never@739 | 168 | map_register(13, r15); r15_opr = LIR_OprFact::single_cpu(13); |
never@739 | 169 | map_register(14, rsp); |
never@739 | 170 | map_register(15, rbp); |
never@739 | 171 | #endif // _LP64 |
never@739 | 172 | |
never@739 | 173 | #ifdef _LP64 |
never@739 | 174 | long0_opr = LIR_OprFact::double_cpu(3 /*eax*/, 3 /*eax*/); |
never@739 | 175 | long1_opr = LIR_OprFact::double_cpu(2 /*ebx*/, 2 /*ebx*/); |
never@739 | 176 | #else |
never@739 | 177 | long0_opr = LIR_OprFact::double_cpu(3 /*eax*/, 4 /*edx*/); |
never@739 | 178 | long1_opr = LIR_OprFact::double_cpu(2 /*ebx*/, 5 /*ecx*/); |
never@739 | 179 | #endif // _LP64 |
duke@435 | 180 | fpu0_float_opr = LIR_OprFact::single_fpu(0); |
duke@435 | 181 | fpu0_double_opr = LIR_OprFact::double_fpu(0); |
duke@435 | 182 | xmm0_float_opr = LIR_OprFact::single_xmm(0); |
duke@435 | 183 | xmm0_double_opr = LIR_OprFact::double_xmm(0); |
duke@435 | 184 | |
duke@435 | 185 | _caller_save_cpu_regs[0] = rsi_opr; |
duke@435 | 186 | _caller_save_cpu_regs[1] = rdi_opr; |
duke@435 | 187 | _caller_save_cpu_regs[2] = rbx_opr; |
duke@435 | 188 | _caller_save_cpu_regs[3] = rax_opr; |
duke@435 | 189 | _caller_save_cpu_regs[4] = rdx_opr; |
duke@435 | 190 | _caller_save_cpu_regs[5] = rcx_opr; |
duke@435 | 191 | |
never@739 | 192 | #ifdef _LP64 |
never@739 | 193 | _caller_save_cpu_regs[6] = r8_opr; |
never@739 | 194 | _caller_save_cpu_regs[7] = r9_opr; |
never@739 | 195 | _caller_save_cpu_regs[8] = r11_opr; |
iveresov@2344 | 196 | _caller_save_cpu_regs[9] = r13_opr; |
iveresov@2344 | 197 | _caller_save_cpu_regs[10] = r14_opr; |
iveresov@2344 | 198 | _caller_save_cpu_regs[11] = r12_opr; |
never@739 | 199 | #endif // _LP64 |
never@739 | 200 | |
duke@435 | 201 | |
duke@435 | 202 | _xmm_regs[0] = xmm0; |
duke@435 | 203 | _xmm_regs[1] = xmm1; |
duke@435 | 204 | _xmm_regs[2] = xmm2; |
duke@435 | 205 | _xmm_regs[3] = xmm3; |
duke@435 | 206 | _xmm_regs[4] = xmm4; |
duke@435 | 207 | _xmm_regs[5] = xmm5; |
duke@435 | 208 | _xmm_regs[6] = xmm6; |
duke@435 | 209 | _xmm_regs[7] = xmm7; |
duke@435 | 210 | |
never@739 | 211 | #ifdef _LP64 |
never@739 | 212 | _xmm_regs[8] = xmm8; |
never@739 | 213 | _xmm_regs[9] = xmm9; |
never@739 | 214 | _xmm_regs[10] = xmm10; |
never@739 | 215 | _xmm_regs[11] = xmm11; |
never@739 | 216 | _xmm_regs[12] = xmm12; |
never@739 | 217 | _xmm_regs[13] = xmm13; |
never@739 | 218 | _xmm_regs[14] = xmm14; |
never@739 | 219 | _xmm_regs[15] = xmm15; |
never@739 | 220 | #endif // _LP64 |
never@739 | 221 | |
duke@435 | 222 | for (int i = 0; i < 8; i++) { |
duke@435 | 223 | _caller_save_fpu_regs[i] = LIR_OprFact::single_fpu(i); |
never@739 | 224 | } |
never@739 | 225 | |
never@739 | 226 | for (int i = 0; i < nof_caller_save_xmm_regs ; i++) { |
duke@435 | 227 | _caller_save_xmm_regs[i] = LIR_OprFact::single_xmm(i); |
duke@435 | 228 | } |
duke@435 | 229 | |
duke@435 | 230 | _init_done = true; |
duke@435 | 231 | |
never@739 | 232 | rsi_oop_opr = as_oop_opr(rsi); |
never@739 | 233 | rdi_oop_opr = as_oop_opr(rdi); |
never@739 | 234 | rbx_oop_opr = as_oop_opr(rbx); |
never@739 | 235 | rax_oop_opr = as_oop_opr(rax); |
never@739 | 236 | rdx_oop_opr = as_oop_opr(rdx); |
never@739 | 237 | rcx_oop_opr = as_oop_opr(rcx); |
never@739 | 238 | |
never@739 | 239 | rsp_opr = as_pointer_opr(rsp); |
never@739 | 240 | rbp_opr = as_pointer_opr(rbp); |
never@739 | 241 | |
never@739 | 242 | #ifdef _LP64 |
never@739 | 243 | r8_oop_opr = as_oop_opr(r8); |
never@739 | 244 | r9_oop_opr = as_oop_opr(r9); |
never@739 | 245 | r11_oop_opr = as_oop_opr(r11); |
never@739 | 246 | r12_oop_opr = as_oop_opr(r12); |
never@739 | 247 | r13_oop_opr = as_oop_opr(r13); |
never@739 | 248 | r14_oop_opr = as_oop_opr(r14); |
never@739 | 249 | #endif // _LP64 |
never@739 | 250 | |
duke@435 | 251 | VMRegPair regs; |
duke@435 | 252 | BasicType sig_bt = T_OBJECT; |
duke@435 | 253 | SharedRuntime::java_calling_convention(&sig_bt, ®s, 1, true); |
duke@435 | 254 | receiver_opr = as_oop_opr(regs.first()->as_Register()); |
never@739 | 255 | |
duke@435 | 256 | } |
duke@435 | 257 | |
duke@435 | 258 | |
duke@435 | 259 | Address FrameMap::make_new_address(ByteSize sp_offset) const { |
duke@435 | 260 | // for rbp, based address use this: |
duke@435 | 261 | // return Address(rbp, in_bytes(sp_offset) - (framesize() - 2) * 4); |
duke@435 | 262 | return Address(rsp, in_bytes(sp_offset)); |
duke@435 | 263 | } |
duke@435 | 264 | |
duke@435 | 265 | |
duke@435 | 266 | // ----------------mapping----------------------- |
duke@435 | 267 | // all mapping is based on rbp, addressing, except for simple leaf methods where we access |
duke@435 | 268 | // the locals rsp based (and no frame is built) |
duke@435 | 269 | |
duke@435 | 270 | |
duke@435 | 271 | // Frame for simple leaf methods (quick entries) |
duke@435 | 272 | // |
duke@435 | 273 | // +----------+ |
duke@435 | 274 | // | ret addr | <- TOS |
duke@435 | 275 | // +----------+ |
duke@435 | 276 | // | args | |
duke@435 | 277 | // | ...... | |
duke@435 | 278 | |
duke@435 | 279 | // Frame for standard methods |
duke@435 | 280 | // |
duke@435 | 281 | // | .........| <- TOS |
duke@435 | 282 | // | locals | |
duke@435 | 283 | // +----------+ |
duke@435 | 284 | // | old rbp, | <- EBP |
duke@435 | 285 | // +----------+ |
duke@435 | 286 | // | ret addr | |
duke@435 | 287 | // +----------+ |
duke@435 | 288 | // | args | |
duke@435 | 289 | // | .........| |
duke@435 | 290 | |
duke@435 | 291 | |
duke@435 | 292 | // For OopMaps, map a local variable or spill index to an VMRegImpl name. |
duke@435 | 293 | // This is the offset from sp() in the frame of the slot for the index, |
duke@435 | 294 | // skewed by VMRegImpl::stack0 to indicate a stack location (vs.a register.) |
duke@435 | 295 | // |
duke@435 | 296 | // framesize + |
duke@435 | 297 | // stack0 stack0 0 <- VMReg |
duke@435 | 298 | // | | <registers> | |
duke@435 | 299 | // ...........|..............|.............| |
duke@435 | 300 | // 0 1 2 3 x x 4 5 6 ... | <- local indices |
duke@435 | 301 | // ^ ^ sp() ( x x indicate link |
duke@435 | 302 | // | | and return addr) |
duke@435 | 303 | // arguments non-argument locals |
duke@435 | 304 | |
duke@435 | 305 | |
duke@435 | 306 | VMReg FrameMap::fpu_regname (int n) { |
duke@435 | 307 | // Return the OptoReg name for the fpu stack slot "n" |
duke@435 | 308 | // A spilled fpu stack slot comprises to two single-word OptoReg's. |
duke@435 | 309 | return as_FloatRegister(n)->as_VMReg(); |
duke@435 | 310 | } |
duke@435 | 311 | |
duke@435 | 312 | LIR_Opr FrameMap::stack_pointer() { |
duke@435 | 313 | return FrameMap::rsp_opr; |
duke@435 | 314 | } |
duke@435 | 315 | |
duke@435 | 316 | |
twisti@1919 | 317 | // JSR 292 |
twisti@1919 | 318 | LIR_Opr FrameMap::method_handle_invoke_SP_save_opr() { |
twisti@1919 | 319 | assert(rbp == rbp_mh_SP_save, "must be same register"); |
twisti@1919 | 320 | return rbp_opr; |
twisti@1919 | 321 | } |
twisti@1919 | 322 | |
twisti@1919 | 323 | |
duke@435 | 324 | bool FrameMap::validate_frame() { |
duke@435 | 325 | return true; |
duke@435 | 326 | } |