src/cpu/zero/vm/vmreg_zero.inline.hpp

Tue, 18 Nov 2014 19:17:16 +0100

author
simonis
date
Tue, 18 Nov 2014 19:17:16 +0100
changeset 7599
c6affd32651a
parent 2314
f95d63e2154a
child 6876
710a3c8b516e
permissions
-rw-r--r--

8064815: Zero+PPC64: Stack overflow when running Maven
Reviewed-by: kvn, simonis
Contributed-by: sgehwolf@redhat.com

never@1445 1 /*
stefank@2314 2 * Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved.
never@1445 3 * Copyright 2007 Red Hat, Inc.
never@1445 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
never@1445 5 *
never@1445 6 * This code is free software; you can redistribute it and/or modify it
never@1445 7 * under the terms of the GNU General Public License version 2 only, as
never@1445 8 * published by the Free Software Foundation.
never@1445 9 *
never@1445 10 * This code is distributed in the hope that it will be useful, but WITHOUT
never@1445 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
never@1445 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
never@1445 13 * version 2 for more details (a copy is included in the LICENSE file that
never@1445 14 * accompanied this code).
never@1445 15 *
never@1445 16 * You should have received a copy of the GNU General Public License version
never@1445 17 * 2 along with this work; if not, write to the Free Software Foundation,
never@1445 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
never@1445 19 *
trims@1907 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
trims@1907 21 * or visit www.oracle.com if you need additional information or have any
trims@1907 22 * questions.
never@1445 23 *
never@1445 24 */
never@1445 25
stefank@2314 26 #ifndef CPU_ZERO_VM_VMREG_ZERO_INLINE_HPP
stefank@2314 27 #define CPU_ZERO_VM_VMREG_ZERO_INLINE_HPP
stefank@2314 28
never@1445 29 inline VMReg RegisterImpl::as_VMReg() {
never@1445 30 return VMRegImpl::as_VMReg(encoding());
never@1445 31 }
never@1445 32
never@1445 33 inline VMReg FloatRegisterImpl::as_VMReg() {
never@1445 34 return VMRegImpl::as_VMReg(encoding() + ConcreteRegisterImpl::max_gpr);
never@1445 35 }
stefank@2314 36
stefank@2314 37 #endif // CPU_ZERO_VM_VMREG_ZERO_INLINE_HPP

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