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src/cpu/zero/vm/register_zero.hpp@c6affd32651a (annotated)

src/cpu/zero/vm/register_zero.hpp

Tue, 18 Nov 2014 19:17:16 +0100

author

simonis

date

Tue, 18 Nov 2014 19:17:16 +0100

changeset 7599

c6affd32651a

parent 4237

a3e2f723f2a5

child 6876

710a3c8b516e

permissions

-rw-r--r--

8064815: Zero+PPC64: Stack overflow when running Maven
Reviewed-by: kvn, simonis
Contributed-by: sgehwolf@redhat.com

never@1445	1	/*
stefank@2314	2	* Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved.
never@1445	3	* Copyright 2007 Red Hat, Inc.
never@1445	4	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
never@1445	5	*
never@1445	6	* This code is free software; you can redistribute it and/or modify it
never@1445	7	* under the terms of the GNU General Public License version 2 only, as
never@1445	8	* published by the Free Software Foundation.
never@1445	9	*
never@1445	10	* This code is distributed in the hope that it will be useful, but WITHOUT
never@1445	11	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
never@1445	12	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
never@1445	13	* version 2 for more details (a copy is included in the LICENSE file that
never@1445	14	* accompanied this code).
never@1445	15	*
never@1445	16	* You should have received a copy of the GNU General Public License version
never@1445	17	* 2 along with this work; if not, write to the Free Software Foundation,
never@1445	18	* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
never@1445	19	*
trims@1907	20	* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
trims@1907	21	* or visit www.oracle.com if you need additional information or have any
trims@1907	22	* questions.
never@1445	23	*
never@1445	24	*/
never@1445	25
stefank@2314	26	#ifndef CPU_ZERO_VM_REGISTER_ZERO_HPP
stefank@2314	27	#define CPU_ZERO_VM_REGISTER_ZERO_HPP
stefank@2314	28
stefank@2314	29	#include "asm/register.hpp"
stefank@2314	30	#include "vm_version_zero.hpp"
stefank@2314	31
never@1445	32	class VMRegImpl;
never@1445	33	typedef VMRegImpl* VMReg;
never@1445	34
never@1445	35	// Use Register as shortcut
never@1445	36	class RegisterImpl;
never@1445	37	typedef RegisterImpl* Register;
never@1445	38
never@1445	39	inline Register as_Register(int encoding) {
never@1445	40	return (Register)(intptr_t) encoding;
never@1445	41	}
never@1445	42
never@1445	43	// The implementation of integer registers for the zero architecture
never@1445	44	class RegisterImpl : public AbstractRegisterImpl {
never@1445	45	public:
never@1445	46	enum {
never@1445	47	number_of_registers = 0
never@1445	48	};
never@1445	49
never@1445	50	// construction
never@1445	51	inline friend Register as_Register(int encoding);
never@1445	52	VMReg as_VMReg();
never@1445	53
never@1445	54	// derived registers, offsets, and addresses
never@1445	55	Register successor() const {
never@1445	56	return as_Register(encoding() + 1);
never@1445	57	}
never@1445	58
never@1445	59	// accessors
never@1445	60	int encoding() const {
never@1445	61	assert(is_valid(), "invalid register");
never@1445	62	return (intptr_t)this;
never@1445	63	}
never@1445	64	bool is_valid() const {
never@1445	65	return 0 <= (intptr_t) this && (intptr_t)this < number_of_registers;
never@1445	66	}
never@1445	67	const char* name() const;
never@1445	68	};
never@1445	69
never@1445	70	// Use FloatRegister as shortcut
never@1445	71	class FloatRegisterImpl;
never@1445	72	typedef FloatRegisterImpl* FloatRegister;
never@1445	73
never@1445	74	inline FloatRegister as_FloatRegister(int encoding) {
never@1445	75	return (FloatRegister)(intptr_t) encoding;
never@1445	76	}
never@1445	77
never@1445	78	// The implementation of floating point registers for the zero architecture
never@1445	79	class FloatRegisterImpl : public AbstractRegisterImpl {
never@1445	80	public:
never@1445	81	enum {
never@1445	82	number_of_registers = 0
never@1445	83	};
never@1445	84
never@1445	85	// construction
never@1445	86	inline friend FloatRegister as_FloatRegister(int encoding);
never@1445	87	VMReg as_VMReg();
never@1445	88
never@1445	89	// derived registers, offsets, and addresses
never@1445	90	FloatRegister successor() const {
never@1445	91	return as_FloatRegister(encoding() + 1);
never@1445	92	}
never@1445	93
never@1445	94	// accessors
never@1445	95	int encoding() const {
never@1445	96	assert(is_valid(), "invalid register");
never@1445	97	return (intptr_t)this;
never@1445	98	}
never@1445	99	bool is_valid() const {
never@1445	100	return 0 <= (intptr_t) this && (intptr_t)this < number_of_registers;
never@1445	101	}
never@1445	102	const char* name() const;
never@1445	103	};
never@1445	104
never@1445	105	class ConcreteRegisterImpl : public AbstractRegisterImpl {
never@1445	106	public:
never@1445	107	enum {
never@1445	108	number_of_registers = RegisterImpl::number_of_registers +
never@1445	109	FloatRegisterImpl::number_of_registers
never@1445	110	};
never@1445	111
never@1445	112	static const int max_gpr;
never@1445	113	static const int max_fpr;
never@1445	114	};
never@1445	115
never@1445	116	CONSTANT_REGISTER_DECLARATION(Register, noreg, (-1));
twisti@4237	117	#ifndef DONT_USE_REGISTER_DEFINES
twisti@4237	118	#define noreg ((Register)(noreg_RegisterEnumValue))
twisti@4237	119	#endif
stefank@2314	120
stefank@2314	121	#endif // CPU_ZERO_VM_REGISTER_ZERO_HPP