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src/cpu/x86/vm/c1_FrameMap_x86.hpp@bb1da64b0492 (annotated)

src/cpu/x86/vm/c1_FrameMap_x86.hpp

Fri, 16 Aug 2019 16:50:17 +0200

author
eosterlund
date
Fri, 16 Aug 2019 16:50:17 +0200
changeset 9834
bb1da64b0492
parent 6198
55fb97c4c58d
child 6876
710a3c8b516e
permissions
-rw-r--r--

8229345: Memory leak due to vtable stubs not being shared on SPARC
Reviewed-by: mdoerr, dholmes, kvn

duke@435 1 /*
mikael@6198 2 * Copyright (c) 1999, 2013, Oracle and/or its affiliates. All rights reserved.
duke@435 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
duke@435 4 *
duke@435 5 * This code is free software; you can redistribute it and/or modify it
duke@435 6 * under the terms of the GNU General Public License version 2 only, as
duke@435 7 * published by the Free Software Foundation.
duke@435 8 *
duke@435 9 * This code is distributed in the hope that it will be useful, but WITHOUT
duke@435 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
duke@435 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
duke@435 12 * version 2 for more details (a copy is included in the LICENSE file that
duke@435 13 * accompanied this code).
duke@435 14 *
duke@435 15 * You should have received a copy of the GNU General Public License version
duke@435 16 * 2 along with this work; if not, write to the Free Software Foundation,
duke@435 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
duke@435 18 *
trims@1907 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
trims@1907 20 * or visit www.oracle.com if you need additional information or have any
trims@1907 21 * questions.
duke@435 22 *
duke@435 23 */
duke@435 24
stefank@2314 25 #ifndef CPU_X86_VM_C1_FRAMEMAP_X86_HPP
stefank@2314 26 #define CPU_X86_VM_C1_FRAMEMAP_X86_HPP
stefank@2314 27
duke@435 28 // On i486 the frame looks as follows:
duke@435 29 //
duke@435 30 // +-----------------------------+---------+----------------------------------------+----------------+-----------
duke@435 31 // | size_arguments-nof_reg_args | 2 words | size_locals-size_arguments+numreg_args | _size_monitors | spilling .
duke@435 32 // +-----------------------------+---------+----------------------------------------+----------------+-----------
duke@435 33 //
duke@435 34 // The FPU registers are mapped with their offset from TOS; therefore the
duke@435 35 // status of FPU stack must be updated during code emission.
duke@435 36
duke@435 37 public:
duke@435 38 static const int pd_c_runtime_reserved_arg_size;
duke@435 39
duke@435 40 enum {
duke@435 41 nof_xmm_regs = pd_nof_xmm_regs_frame_map,
duke@435 42 nof_caller_save_xmm_regs = pd_nof_caller_save_xmm_regs_frame_map,
duke@435 43 first_available_sp_in_frame = 0,
never@739 44 #ifndef _LP64
duke@435 45 frame_pad_in_bytes = 8,
duke@435 46 nof_reg_args = 2
never@739 47 #else
never@739 48 frame_pad_in_bytes = 16,
never@739 49 nof_reg_args = 6
never@739 50 #endif // _LP64
duke@435 51 };
duke@435 52
duke@435 53 private:
duke@435 54 static LIR_Opr _caller_save_xmm_regs [nof_caller_save_xmm_regs];
duke@435 55
duke@435 56 static XMMRegister _xmm_regs[nof_xmm_regs];
duke@435 57
duke@435 58 public:
duke@435 59 static LIR_Opr receiver_opr;
duke@435 60
duke@435 61 static LIR_Opr rsi_opr;
duke@435 62 static LIR_Opr rdi_opr;
duke@435 63 static LIR_Opr rbx_opr;
duke@435 64 static LIR_Opr rax_opr;
duke@435 65 static LIR_Opr rdx_opr;
duke@435 66 static LIR_Opr rcx_opr;
duke@435 67 static LIR_Opr rsp_opr;
duke@435 68 static LIR_Opr rbp_opr;
duke@435 69
duke@435 70 static LIR_Opr rsi_oop_opr;
duke@435 71 static LIR_Opr rdi_oop_opr;
duke@435 72 static LIR_Opr rbx_oop_opr;
duke@435 73 static LIR_Opr rax_oop_opr;
duke@435 74 static LIR_Opr rdx_oop_opr;
duke@435 75 static LIR_Opr rcx_oop_opr;
roland@4051 76
roland@4051 77 static LIR_Opr rsi_metadata_opr;
roland@4051 78 static LIR_Opr rdi_metadata_opr;
roland@4051 79 static LIR_Opr rbx_metadata_opr;
roland@4051 80 static LIR_Opr rax_metadata_opr;
roland@4051 81 static LIR_Opr rdx_metadata_opr;
roland@4051 82 static LIR_Opr rcx_metadata_opr;
roland@4051 83
never@739 84 #ifdef _LP64
duke@435 85
never@739 86 static LIR_Opr r8_opr;
never@739 87 static LIR_Opr r9_opr;
never@739 88 static LIR_Opr r10_opr;
never@739 89 static LIR_Opr r11_opr;
never@739 90 static LIR_Opr r12_opr;
never@739 91 static LIR_Opr r13_opr;
never@739 92 static LIR_Opr r14_opr;
never@739 93 static LIR_Opr r15_opr;
never@739 94
never@739 95 static LIR_Opr r8_oop_opr;
never@739 96 static LIR_Opr r9_oop_opr;
never@739 97
never@739 98 static LIR_Opr r11_oop_opr;
never@739 99 static LIR_Opr r12_oop_opr;
never@739 100 static LIR_Opr r13_oop_opr;
never@739 101 static LIR_Opr r14_oop_opr;
never@739 102
roland@4051 103 static LIR_Opr r8_metadata_opr;
roland@4051 104 static LIR_Opr r9_metadata_opr;
roland@4051 105
roland@4051 106 static LIR_Opr r11_metadata_opr;
roland@4051 107 static LIR_Opr r12_metadata_opr;
roland@4051 108 static LIR_Opr r13_metadata_opr;
roland@4051 109 static LIR_Opr r14_metadata_opr;
roland@4051 110
never@739 111 #endif // _LP64
never@739 112
never@739 113 static LIR_Opr long0_opr;
never@739 114 static LIR_Opr long1_opr;
duke@435 115 static LIR_Opr fpu0_float_opr;
duke@435 116 static LIR_Opr fpu0_double_opr;
duke@435 117 static LIR_Opr xmm0_float_opr;
duke@435 118 static LIR_Opr xmm0_double_opr;
duke@435 119
never@739 120 #ifdef _LP64
never@739 121 static LIR_Opr as_long_opr(Register r) {
never@739 122 return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r));
never@739 123 }
never@739 124 static LIR_Opr as_pointer_opr(Register r) {
never@739 125 return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r));
never@739 126 }
never@739 127 #else
duke@435 128 static LIR_Opr as_long_opr(Register r, Register r2) {
duke@435 129 return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r2));
duke@435 130 }
never@739 131 static LIR_Opr as_pointer_opr(Register r) {
never@739 132 return LIR_OprFact::single_cpu(cpu_reg2rnr(r));
never@739 133 }
never@739 134 #endif // _LP64
duke@435 135
duke@435 136 // VMReg name for spilled physical FPU stack slot n
duke@435 137 static VMReg fpu_regname (int n);
duke@435 138
duke@435 139 static XMMRegister nr2xmmreg(int rnr);
duke@435 140
duke@435 141 static bool is_caller_save_register (LIR_Opr opr) { return true; }
duke@435 142 static bool is_caller_save_register (Register r) { return true; }
duke@435 143
duke@435 144 static LIR_Opr caller_save_xmm_reg_at(int i) {
duke@435 145 assert(i >= 0 && i < nof_caller_save_xmm_regs, "out of bounds");
duke@435 146 return _caller_save_xmm_regs[i];
duke@435 147 }
stefank@2314 148
iveresov@2344 149 static int adjust_reg_range(int range) {
iveresov@2344 150 // Reduce the number of available regs (to free r12) in case of compressed oops
ehelin@5694 151 if (UseCompressedOops || UseCompressedClassPointers) return range - 1;
iveresov@2344 152 return range;
iveresov@2344 153 }
iveresov@2344 154
iveresov@2344 155 static int nof_caller_save_cpu_regs() { return adjust_reg_range(pd_nof_caller_save_cpu_regs_frame_map); }
iveresov@2344 156 static int last_cpu_reg() { return adjust_reg_range(pd_last_cpu_reg); }
iveresov@2344 157 static int last_byte_reg() { return adjust_reg_range(pd_last_byte_reg); }
iveresov@2344 158
stefank@2314 159 #endif // CPU_X86_VM_C1_FRAMEMAP_X86_HPP
iveresov@2344 160

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