src/cpu/x86/vm/assembler_x86.inline.hpp

Fri, 16 Aug 2019 16:50:17 +0200

author
eosterlund
date
Fri, 16 Aug 2019 16:50:17 +0200
changeset 9834
bb1da64b0492
parent 4318
cd3d6a6b95d9
child 6876
710a3c8b516e
permissions
-rw-r--r--

8229345: Memory leak due to vtable stubs not being shared on SPARC
Reviewed-by: mdoerr, dholmes, kvn

duke@435 1 /*
stefank@2314 2 * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.
duke@435 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
duke@435 4 *
duke@435 5 * This code is free software; you can redistribute it and/or modify it
duke@435 6 * under the terms of the GNU General Public License version 2 only, as
duke@435 7 * published by the Free Software Foundation.
duke@435 8 *
duke@435 9 * This code is distributed in the hope that it will be useful, but WITHOUT
duke@435 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
duke@435 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
duke@435 12 * version 2 for more details (a copy is included in the LICENSE file that
duke@435 13 * accompanied this code).
duke@435 14 *
duke@435 15 * You should have received a copy of the GNU General Public License version
duke@435 16 * 2 along with this work; if not, write to the Free Software Foundation,
duke@435 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
duke@435 18 *
trims@1907 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
trims@1907 20 * or visit www.oracle.com if you need additional information or have any
trims@1907 21 * questions.
duke@435 22 *
duke@435 23 */
duke@435 24
stefank@2314 25 #ifndef CPU_X86_VM_ASSEMBLER_X86_INLINE_HPP
stefank@2314 26 #define CPU_X86_VM_ASSEMBLER_X86_INLINE_HPP
stefank@2314 27
stefank@2314 28 #include "asm/assembler.inline.hpp"
stefank@2314 29 #include "asm/codeBuffer.hpp"
stefank@2314 30 #include "code/codeCache.hpp"
never@739 31
never@739 32 #ifndef _LP64
never@739 33 inline int Assembler::prefix_and_encode(int reg_enc, bool byteinst) { return reg_enc; }
never@739 34 inline int Assembler::prefixq_and_encode(int reg_enc) { return reg_enc; }
never@739 35
never@739 36 inline int Assembler::prefix_and_encode(int dst_enc, int src_enc, bool byteinst) { return dst_enc << 3 | src_enc; }
never@739 37 inline int Assembler::prefixq_and_encode(int dst_enc, int src_enc) { return dst_enc << 3 | src_enc; }
never@739 38
never@739 39 inline void Assembler::prefix(Register reg) {}
never@739 40 inline void Assembler::prefix(Address adr) {}
never@739 41 inline void Assembler::prefixq(Address adr) {}
never@739 42
never@739 43 inline void Assembler::prefix(Address adr, Register reg, bool byteinst) {}
never@739 44 inline void Assembler::prefixq(Address adr, Register reg) {}
never@739 45
never@739 46 inline void Assembler::prefix(Address adr, XMMRegister reg) {}
kvn@3388 47 inline void Assembler::prefixq(Address adr, XMMRegister reg) {}
never@739 48 #endif // _LP64
stefank@2314 49
stefank@2314 50 #endif // CPU_X86_VM_ASSEMBLER_X86_INLINE_HPP

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