• file
• revisions
• annotate
• diff
• comparison
• raw

src/cpu/x86/vm/c1_LinearScan_x86.hpp@b130b98db9cf (annotated)

src/cpu/x86/vm/c1_LinearScan_x86.hpp

Wed, 23 Apr 2008 11:20:36 -0700

author

kvn

date

Wed, 23 Apr 2008 11:20:36 -0700

changeset 559

b130b98db9cf

parent 435

a61af66fc99e

child 739

dc7f315e41f7

permissions

-rw-r--r--

6689060: Escape Analysis does not work with Compressed Oops
Summary: 64-bits VM crashes with -XX:+AggresiveOpts (Escape Analysis + Compressed Oops)
Reviewed-by: never, sgoldman

duke@435	1	/*
duke@435	2	* Copyright 2005-2006 Sun Microsystems, Inc. All Rights Reserved.
duke@435	3	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
duke@435	4	*
duke@435	5	* This code is free software; you can redistribute it and/or modify it
duke@435	6	* under the terms of the GNU General Public License version 2 only, as
duke@435	7	* published by the Free Software Foundation.
duke@435	8	*
duke@435	9	* This code is distributed in the hope that it will be useful, but WITHOUT
duke@435	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
duke@435	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
duke@435	12	* version 2 for more details (a copy is included in the LICENSE file that
duke@435	13	* accompanied this code).
duke@435	14	*
duke@435	15	* You should have received a copy of the GNU General Public License version
duke@435	16	* 2 along with this work; if not, write to the Free Software Foundation,
duke@435	17	* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
duke@435	18	*
duke@435	19	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
duke@435	20	* CA 95054 USA or visit www.sun.com if you need additional information or
duke@435	21	* have any questions.
duke@435	22	*
duke@435	23	*/
duke@435	24
duke@435	25	inline bool LinearScan::is_processed_reg_num(int reg_num) {
duke@435	26	// rsp and rbp (numbers 6 ancd 7) are ignored
duke@435	27	assert(FrameMap::rsp_opr->cpu_regnr() == 6, "wrong assumption below");
duke@435	28	assert(FrameMap::rbp_opr->cpu_regnr() == 7, "wrong assumption below");
duke@435	29	assert(reg_num >= 0, "invalid reg_num");
duke@435	30
duke@435	31	return reg_num < 6 || reg_num > 7;
duke@435	32	}
duke@435	33
duke@435	34	inline int LinearScan::num_physical_regs(BasicType type) {
duke@435	35	// Intel requires two cpu registers for long,
duke@435	36	// but requires only one fpu register for double
duke@435	37	if (type == T_LONG) {
duke@435	38	return 2;
duke@435	39	}
duke@435	40	return 1;
duke@435	41	}
duke@435	42
duke@435	43
duke@435	44	inline bool LinearScan::requires_adjacent_regs(BasicType type) {
duke@435	45	return false;
duke@435	46	}
duke@435	47
duke@435	48	inline bool LinearScan::is_caller_save(int assigned_reg) {
duke@435	49	assert(assigned_reg >= 0 && assigned_reg < nof_regs, "should call this only for registers");
duke@435	50	return true; // no callee-saved registers on Intel
duke@435	51
duke@435	52	}
duke@435	53
duke@435	54
duke@435	55	inline void LinearScan::pd_add_temps(LIR_Op* op) {
duke@435	56	switch (op->code()) {
duke@435	57	case lir_tan:
duke@435	58	case lir_sin:
duke@435	59	case lir_cos: {
duke@435	60	// The slow path for these functions may need to save and
duke@435	61	// restore all live registers but we don't want to save and
duke@435	62	// restore everything all the time, so mark the xmms as being
duke@435	63	// killed. If the slow path were explicit or we could propagate
duke@435	64	// live register masks down to the assembly we could do better
duke@435	65	// but we don't have any easy way to do that right now. We
duke@435	66	// could also consider not killing all xmm registers if we
duke@435	67	// assume that slow paths are uncommon but it's not clear that
duke@435	68	// would be a good idea.
duke@435	69	if (UseSSE > 0) {
duke@435	70	#ifndef PRODUCT
duke@435	71	if (TraceLinearScanLevel >= 2) {
duke@435	72	tty->print_cr("killing XMMs for trig");
duke@435	73	}
duke@435	74	#endif
duke@435	75	int op_id = op->id();
duke@435	76	for (int xmm = 0; xmm < FrameMap::nof_caller_save_xmm_regs; xmm++) {
duke@435	77	LIR_Opr opr = FrameMap::caller_save_xmm_reg_at(xmm);
duke@435	78	add_temp(reg_num(opr), op_id, noUse, T_ILLEGAL);
duke@435	79	}
duke@435	80	}
duke@435	81	break;
duke@435	82	}
duke@435	83	}
duke@435	84	}
duke@435	85
duke@435	86
duke@435	87	// Implementation of LinearScanWalker
duke@435	88
duke@435	89	inline bool LinearScanWalker::pd_init_regs_for_alloc(Interval* cur) {
duke@435	90	if (allocator()->gen()->is_vreg_flag_set(cur->reg_num(), LIRGenerator::byte_reg)) {
duke@435	91	assert(cur->type() != T_FLOAT && cur->type() != T_DOUBLE, "cpu regs only");
duke@435	92	_first_reg = pd_first_byte_reg;
duke@435	93	_last_reg = pd_last_byte_reg;
duke@435	94	return true;
duke@435	95	} else if ((UseSSE >= 1 && cur->type() == T_FLOAT) || (UseSSE >= 2 && cur->type() == T_DOUBLE)) {
duke@435	96	_first_reg = pd_first_xmm_reg;
duke@435	97	_last_reg = pd_last_xmm_reg;
duke@435	98	return true;
duke@435	99	}
duke@435	100
duke@435	101	return false;
duke@435	102	}
duke@435	103
duke@435	104
duke@435	105	class FpuStackAllocator VALUE_OBJ_CLASS_SPEC {
duke@435	106	private:
duke@435	107	Compilation* _compilation;
duke@435	108	LinearScan* _allocator;
duke@435	109
duke@435	110	LIR_OpVisitState visitor;
duke@435	111
duke@435	112	LIR_List* _lir;
duke@435	113	int _pos;
duke@435	114	FpuStackSim _sim;
duke@435	115	FpuStackSim _temp_sim;
duke@435	116
duke@435	117	bool _debug_information_computed;
duke@435	118
duke@435	119	LinearScan* allocator() { return _allocator; }
duke@435	120	Compilation* compilation() const { return _compilation; }
duke@435	121
duke@435	122	// unified bailout support
duke@435	123	void bailout(const char* msg) const { compilation()->bailout(msg); }
duke@435	124	bool bailed_out() const { return compilation()->bailed_out(); }
duke@435	125
duke@435	126	int pos() { return _pos; }
duke@435	127	void set_pos(int pos) { _pos = pos; }
duke@435	128	LIR_Op* cur_op() { return lir()->instructions_list()->at(pos()); }
duke@435	129	LIR_List* lir() { return _lir; }
duke@435	130	void set_lir(LIR_List* lir) { _lir = lir; }
duke@435	131	FpuStackSim* sim() { return &_sim; }
duke@435	132	FpuStackSim* temp_sim() { return &_temp_sim; }
duke@435	133
duke@435	134	int fpu_num(LIR_Opr opr);
duke@435	135	int tos_offset(LIR_Opr opr);
duke@435	136	LIR_Opr to_fpu_stack_top(LIR_Opr opr, bool dont_check_offset = false);
duke@435	137
duke@435	138	// Helper functions for handling operations
duke@435	139	void insert_op(LIR_Op* op);
duke@435	140	void insert_exchange(int offset);
duke@435	141	void insert_exchange(LIR_Opr opr);
duke@435	142	void insert_free(int offset);
duke@435	143	void insert_free_if_dead(LIR_Opr opr);
duke@435	144	void insert_free_if_dead(LIR_Opr opr, LIR_Opr ignore);
duke@435	145	void insert_copy(LIR_Opr from, LIR_Opr to);
duke@435	146	void do_rename(LIR_Opr from, LIR_Opr to);
duke@435	147	void do_push(LIR_Opr opr);
duke@435	148	void pop_if_last_use(LIR_Op* op, LIR_Opr opr);
duke@435	149	void pop_always(LIR_Op* op, LIR_Opr opr);
duke@435	150	void clear_fpu_stack(LIR_Opr preserve);
duke@435	151	void handle_op1(LIR_Op1* op1);
duke@435	152	void handle_op2(LIR_Op2* op2);
duke@435	153	void handle_opCall(LIR_OpCall* opCall);
duke@435	154	void compute_debug_information(LIR_Op* op);
duke@435	155	void allocate_exception_handler(XHandler* xhandler);
duke@435	156	void allocate_block(BlockBegin* block);
duke@435	157
duke@435	158	#ifndef PRODUCT
duke@435	159	void check_invalid_lir_op(LIR_Op* op);
duke@435	160	#endif
duke@435	161
duke@435	162	// Helper functions for merging of fpu stacks
duke@435	163	void merge_insert_add(LIR_List* instrs, FpuStackSim* cur_sim, int reg);
duke@435	164	void merge_insert_xchg(LIR_List* instrs, FpuStackSim* cur_sim, int slot);
duke@435	165	void merge_insert_pop(LIR_List* instrs, FpuStackSim* cur_sim);
duke@435	166	bool merge_rename(FpuStackSim* cur_sim, FpuStackSim* sux_sim, int start_slot, int change_slot);
duke@435	167	void merge_fpu_stack(LIR_List* instrs, FpuStackSim* cur_sim, FpuStackSim* sux_sim);
duke@435	168	void merge_cleanup_fpu_stack(LIR_List* instrs, FpuStackSim* cur_sim, BitMap& live_fpu_regs);
duke@435	169	bool merge_fpu_stack_with_successors(BlockBegin* block);
duke@435	170
duke@435	171	public:
duke@435	172	LIR_Opr to_fpu_stack(LIR_Opr opr); // used by LinearScan for creation of debug information
duke@435	173
duke@435	174	FpuStackAllocator(Compilation* compilation, LinearScan* allocator);
duke@435	175	void allocate();
duke@435	176	};