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src/cpu/sparc/vm/vmreg_sparc.inline.hpp@ac637b7220d1 (annotated)

src/cpu/sparc/vm/vmreg_sparc.inline.hpp

Tue, 30 Nov 2010 23:23:40 -0800

author

iveresov

date

Tue, 30 Nov 2010 23:23:40 -0800

changeset 2344

ac637b7220d1

parent 2314

f95d63e2154a

child 6876

710a3c8b516e

permissions

-rw-r--r--

6985015: C1 needs to support compressed oops
Summary: This change implements compressed oops for C1 for x64 and sparc. The changes are mostly on the codegen level, with a few exceptions when we do access things outside of the heap that are uncompressed from the IR. Compressed oops are now also enabled with tiered.
Reviewed-by: twisti, kvn, never, phh

duke@435	1	/*
stefank@2314	2	* Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved.
duke@435	3	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
duke@435	4	*
duke@435	5	* This code is free software; you can redistribute it and/or modify it
duke@435	6	* under the terms of the GNU General Public License version 2 only, as
duke@435	7	* published by the Free Software Foundation.
duke@435	8	*
duke@435	9	* This code is distributed in the hope that it will be useful, but WITHOUT
duke@435	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
duke@435	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
duke@435	12	* version 2 for more details (a copy is included in the LICENSE file that
duke@435	13	* accompanied this code).
duke@435	14	*
duke@435	15	* You should have received a copy of the GNU General Public License version
duke@435	16	* 2 along with this work; if not, write to the Free Software Foundation,
duke@435	17	* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
duke@435	18	*
trims@1907	19	* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
trims@1907	20	* or visit www.oracle.com if you need additional information or have any
trims@1907	21	* questions.
duke@435	22	*
duke@435	23	*/
duke@435	24
stefank@2314	25	#ifndef CPU_SPARC_VM_VMREG_SPARC_INLINE_HPP
stefank@2314	26	#define CPU_SPARC_VM_VMREG_SPARC_INLINE_HPP
stefank@2314	27
duke@435	28	inline VMReg RegisterImpl::as_VMReg() {
duke@435	29	if( this==noreg ) return VMRegImpl::Bad();
duke@435	30	return VMRegImpl::as_VMReg(encoding() << 1 );
duke@435	31	}
duke@435	32
duke@435	33	inline VMReg FloatRegisterImpl::as_VMReg() { return VMRegImpl::as_VMReg( ConcreteRegisterImpl::max_gpr + encoding() ); }
duke@435	34
duke@435	35
duke@435	36	inline bool VMRegImpl::is_Register() { return value() >= 0 && value() < ConcreteRegisterImpl::max_gpr; }
duke@435	37	inline bool VMRegImpl::is_FloatRegister() { return value() >= ConcreteRegisterImpl::max_gpr &&
duke@435	38	value() < ConcreteRegisterImpl::max_fpr; }
duke@435	39	inline Register VMRegImpl::as_Register() {
duke@435	40
duke@435	41	assert( is_Register() && is_even(value()), "even-aligned GPR name" );
duke@435	42	// Yuk
duke@435	43	return ::as_Register(value()>>1);
duke@435	44	}
duke@435	45
duke@435	46	inline FloatRegister VMRegImpl::as_FloatRegister() {
duke@435	47	assert( is_FloatRegister(), "must be" );
duke@435	48	// Yuk
duke@435	49	return ::as_FloatRegister( value() - ConcreteRegisterImpl::max_gpr );
duke@435	50	}
duke@435	51
duke@435	52	inline bool VMRegImpl::is_concrete() {
duke@435	53	assert(is_reg(), "must be");
duke@435	54	int v = value();
duke@435	55	if ( v < ConcreteRegisterImpl::max_gpr ) {
duke@435	56	return is_even(v);
duke@435	57	}
duke@435	58	// F0..F31
duke@435	59	if ( v <= ConcreteRegisterImpl::max_gpr + 31) return true;
duke@435	60	if ( v < ConcreteRegisterImpl::max_fpr) {
duke@435	61	return is_even(v);
duke@435	62	}
duke@435	63	assert(false, "what register?");
duke@435	64	return false;
duke@435	65	}
stefank@2314	66
stefank@2314	67	#endif // CPU_SPARC_VM_VMREG_SPARC_INLINE_HPP