src/cpu/sparc/vm/c1_LinearScan_sparc.hpp

Tue, 30 Nov 2010 23:23:40 -0800

author
iveresov
date
Tue, 30 Nov 2010 23:23:40 -0800
changeset 2344
ac637b7220d1
parent 2314
f95d63e2154a
child 4056
7edbe32b9802
permissions
-rw-r--r--

6985015: C1 needs to support compressed oops
Summary: This change implements compressed oops for C1 for x64 and sparc. The changes are mostly on the codegen level, with a few exceptions when we do access things outside of the heap that are uncompressed from the IR. Compressed oops are now also enabled with tiered.
Reviewed-by: twisti, kvn, never, phh

duke@435 1 /*
stefank@2314 2 * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
duke@435 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
duke@435 4 *
duke@435 5 * This code is free software; you can redistribute it and/or modify it
duke@435 6 * under the terms of the GNU General Public License version 2 only, as
duke@435 7 * published by the Free Software Foundation.
duke@435 8 *
duke@435 9 * This code is distributed in the hope that it will be useful, but WITHOUT
duke@435 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
duke@435 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
duke@435 12 * version 2 for more details (a copy is included in the LICENSE file that
duke@435 13 * accompanied this code).
duke@435 14 *
duke@435 15 * You should have received a copy of the GNU General Public License version
duke@435 16 * 2 along with this work; if not, write to the Free Software Foundation,
duke@435 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
duke@435 18 *
trims@1907 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
trims@1907 20 * or visit www.oracle.com if you need additional information or have any
trims@1907 21 * questions.
duke@435 22 *
duke@435 23 */
duke@435 24
stefank@2314 25 #ifndef CPU_SPARC_VM_C1_LINEARSCAN_SPARC_HPP
stefank@2314 26 #define CPU_SPARC_VM_C1_LINEARSCAN_SPARC_HPP
stefank@2314 27
duke@435 28 inline bool LinearScan::is_processed_reg_num(int reg_num) {
duke@435 29 return reg_num < 26 || reg_num > 31;
duke@435 30 }
duke@435 31
duke@435 32 inline int LinearScan::num_physical_regs(BasicType type) {
duke@435 33 // Sparc requires two cpu registers for long
duke@435 34 // and two cpu registers for double
duke@435 35 #ifdef _LP64
duke@435 36 if (type == T_DOUBLE) {
duke@435 37 #else
duke@435 38 if (type == T_DOUBLE || type == T_LONG) {
duke@435 39 #endif
duke@435 40 return 2;
duke@435 41 }
duke@435 42 return 1;
duke@435 43 }
duke@435 44
duke@435 45
duke@435 46 inline bool LinearScan::requires_adjacent_regs(BasicType type) {
duke@435 47 #ifdef _LP64
duke@435 48 return type == T_DOUBLE;
duke@435 49 #else
duke@435 50 return type == T_DOUBLE || type == T_LONG;
duke@435 51 #endif
duke@435 52 }
duke@435 53
duke@435 54 inline bool LinearScan::is_caller_save(int assigned_reg) {
duke@435 55 return assigned_reg > pd_last_callee_saved_reg && assigned_reg <= pd_last_fpu_reg;
duke@435 56 }
duke@435 57
duke@435 58
duke@435 59 inline void LinearScan::pd_add_temps(LIR_Op* op) {
duke@435 60 // No special case behaviours yet
duke@435 61 }
duke@435 62
duke@435 63
duke@435 64 inline bool LinearScanWalker::pd_init_regs_for_alloc(Interval* cur) {
duke@435 65 if (allocator()->gen()->is_vreg_flag_set(cur->reg_num(), LIRGenerator::callee_saved)) {
duke@435 66 assert(cur->type() != T_FLOAT && cur->type() != T_DOUBLE, "cpu regs only");
duke@435 67 _first_reg = pd_first_callee_saved_reg;
duke@435 68 _last_reg = pd_last_callee_saved_reg;
duke@435 69 return true;
roland@2206 70 } else if (cur->type() == T_INT || cur->type() == T_LONG || cur->type() == T_OBJECT || cur->type() == T_ADDRESS) {
duke@435 71 _first_reg = pd_first_cpu_reg;
duke@435 72 _last_reg = pd_last_allocatable_cpu_reg;
duke@435 73 return true;
duke@435 74 }
duke@435 75 return false;
duke@435 76 }
stefank@2314 77
stefank@2314 78 #endif // CPU_SPARC_VM_C1_LINEARSCAN_SPARC_HPP

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